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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch_helpers.h>
8#include <arm_def.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01009#include <assert.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <bl_common.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010011#include <debug.h>
12#include <desc_image_load.h>
Soby Mathew1ced6b82017-06-12 12:37:10 +010013#include <generic_delay_timer.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010014#ifdef SPD_opteed
15#include <optee_utils.h>
16#endif
Dan Handley9df48042015-03-19 18:58:55 +000017#include <plat_arm.h>
dp-arm7f297ca2017-05-02 11:49:33 +010018#include <platform.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010019#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000020#include <string.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000021#include <utils.h>
Dan Handley9df48042015-03-19 18:58:55 +000022
Dan Handley9df48042015-03-19 18:58:55 +000023/* Data structure which holds the extents of the trusted SRAM for BL2 */
24static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
25
Soby Mathewc44110d2018-02-20 12:50:47 +000026/*
Soby Mathewaf14b462018-06-01 16:53:38 +010027 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is
28 * for `meminfo_t` data structure and fw_configs passed from BL1.
Soby Mathewc44110d2018-02-20 12:50:47 +000029 */
Soby Mathewaf14b462018-06-01 16:53:38 +010030CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
Soby Mathewc44110d2018-02-20 12:50:47 +000031
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010032/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000033#pragma weak bl2_early_platform_setup2
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010034#pragma weak bl2_platform_setup
35#pragma weak bl2_plat_arch_setup
36#pragma weak bl2_plat_sec_mem_layout
37
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010038#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
39 bl2_tzram_layout.total_base, \
40 bl2_tzram_layout.total_size, \
41 MT_MEMORY | MT_RW | MT_SECURE)
42
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010043#if LOAD_IMAGE_V2
44
Daniel Boulby07d26872018-06-27 16:45:48 +010045#pragma weak arm_bl2_plat_handle_post_image_load
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010046
47#else /* LOAD_IMAGE_V2 */
48
Dan Handley9df48042015-03-19 18:58:55 +000049/*******************************************************************************
50 * This structure represents the superset of information that is passed to
Juan Castillo7d199412015-12-14 09:35:25 +000051 * BL31, e.g. while passing control to it from BL2, bl31_params
Dan Handley9df48042015-03-19 18:58:55 +000052 * and other platform specific params
53 ******************************************************************************/
54typedef struct bl2_to_bl31_params_mem {
55 bl31_params_t bl31_params;
56 image_info_t bl31_image_info;
57 image_info_t bl32_image_info;
58 image_info_t bl33_image_info;
59 entry_point_info_t bl33_ep_info;
60 entry_point_info_t bl32_ep_info;
61 entry_point_info_t bl31_ep_info;
62} bl2_to_bl31_params_mem_t;
63
64
65static bl2_to_bl31_params_mem_t bl31_params_mem;
66
67
68/* Weak definitions may be overridden in specific ARM standard platform */
Dan Handley9df48042015-03-19 18:58:55 +000069#pragma weak bl2_plat_get_bl31_params
70#pragma weak bl2_plat_get_bl31_ep_info
71#pragma weak bl2_plat_flush_bl31_params
72#pragma weak bl2_plat_set_bl31_ep_info
Juan Castilloa72b6472015-12-10 15:49:17 +000073#pragma weak bl2_plat_get_scp_bl2_meminfo
Dan Handley9df48042015-03-19 18:58:55 +000074#pragma weak bl2_plat_get_bl32_meminfo
75#pragma weak bl2_plat_set_bl32_ep_info
76#pragma weak bl2_plat_get_bl33_meminfo
77#pragma weak bl2_plat_set_bl33_ep_info
78
David Wang0ba499f2016-03-07 11:02:57 +080079#if ARM_BL31_IN_DRAM
80meminfo_t *bl2_plat_sec_mem_layout(void)
81{
82 static meminfo_t bl2_dram_layout
83 __aligned(CACHE_WRITEBACK_GRANULE) = {
84 .total_base = BL31_BASE,
85 .total_size = (ARM_AP_TZC_DRAM1_BASE +
86 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE,
87 .free_base = BL31_BASE,
88 .free_size = (ARM_AP_TZC_DRAM1_BASE +
89 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE
90 };
Dan Handley9df48042015-03-19 18:58:55 +000091
David Wang0ba499f2016-03-07 11:02:57 +080092 return &bl2_dram_layout;
93}
94#else
Dan Handley9df48042015-03-19 18:58:55 +000095meminfo_t *bl2_plat_sec_mem_layout(void)
96{
97 return &bl2_tzram_layout;
98}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010099#endif /* ARM_BL31_IN_DRAM */
Dan Handley9df48042015-03-19 18:58:55 +0000100
101/*******************************************************************************
102 * This function assigns a pointer to the memory that the platform has kept
103 * aside to pass platform specific and trusted firmware related information
104 * to BL31. This memory is allocated by allocating memory to
105 * bl2_to_bl31_params_mem_t structure which is a superset of all the
106 * structure whose information is passed to BL31
107 * NOTE: This function should be called only once and should be done
108 * before generating params to BL31
109 ******************************************************************************/
110bl31_params_t *bl2_plat_get_bl31_params(void)
111{
112 bl31_params_t *bl2_to_bl31_params;
113
114 /*
115 * Initialise the memory for all the arguments that needs to
Juan Castillo7d199412015-12-14 09:35:25 +0000116 * be passed to BL31
Dan Handley9df48042015-03-19 18:58:55 +0000117 */
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000118 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
Dan Handley9df48042015-03-19 18:58:55 +0000119
120 /* Assign memory for TF related information */
121 bl2_to_bl31_params = &bl31_params_mem.bl31_params;
122 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
123
Juan Castillo7d199412015-12-14 09:35:25 +0000124 /* Fill BL31 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000125 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
126 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
127 VERSION_1, 0);
128
Juan Castillo7d199412015-12-14 09:35:25 +0000129 /* Fill BL32 related information if it exists */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100130#ifdef BL32_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000131 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
132 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
133 VERSION_1, 0);
134 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
135 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
136 VERSION_1, 0);
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100137#endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000138
Juan Castillo7d199412015-12-14 09:35:25 +0000139 /* Fill BL33 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000140 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
141 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
142 PARAM_EP, VERSION_1, 0);
143
Juan Castillo7d199412015-12-14 09:35:25 +0000144 /* BL33 expects to receive the primary CPU MPID (through x0) */
Dan Handley9df48042015-03-19 18:58:55 +0000145 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
146
147 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
148 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
149 VERSION_1, 0);
150
151 return bl2_to_bl31_params;
152}
153
154/* Flush the TF params and the TF plat params */
155void bl2_plat_flush_bl31_params(void)
156{
157 flush_dcache_range((unsigned long)&bl31_params_mem,
158 sizeof(bl2_to_bl31_params_mem_t));
159}
160
161/*******************************************************************************
162 * This function returns a pointer to the shared memory that the platform
163 * has kept to point to entry point information of BL31 to BL2
164 ******************************************************************************/
165struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
166{
167#if DEBUG
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000168 bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL;
Dan Handley9df48042015-03-19 18:58:55 +0000169#endif
170
171 return &bl31_params_mem.bl31_ep_info;
172}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100173#endif /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +0000174
175/*******************************************************************************
176 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
177 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
178 * Copy it to a safe location before its reclaimed by later BL2 functionality.
179 ******************************************************************************/
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +0200180void arm_bl2_early_platform_setup(uintptr_t tb_fw_config,
181 struct meminfo *mem_layout)
Dan Handley9df48042015-03-19 18:58:55 +0000182{
183 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100184 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +0000185
186 /* Setup the BL2 memory layout */
187 bl2_tzram_layout = *mem_layout;
188
189 /* Initialise the IO layer and register platform IO devices */
190 plat_arm_io_setup();
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000191
192#if LOAD_IMAGE_V2
Soby Mathewcc364842018-02-21 01:16:39 +0000193 if (tb_fw_config != 0U)
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000194 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config);
195#endif
Dan Handley9df48042015-03-19 18:58:55 +0000196}
197
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000198void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +0000199{
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000200 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
201
Soby Mathew1ced6b82017-06-12 12:37:10 +0100202 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +0000203}
204
205/*
Soby Mathew45e39e22018-03-26 15:16:46 +0100206 * Perform BL2 preload setup. Currently we initialise the dynamic
207 * configuration here.
Dan Handley9df48042015-03-19 18:58:55 +0000208 */
Soby Mathew45e39e22018-03-26 15:16:46 +0100209void bl2_plat_preload_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000210{
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000211#if LOAD_IMAGE_V2
212 arm_bl2_dyn_cfg_init();
213#endif
Soby Mathew45e39e22018-03-26 15:16:46 +0100214}
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000215
Soby Mathew45e39e22018-03-26 15:16:46 +0100216/*
217 * Perform ARM standard platform setup.
218 */
219void arm_bl2_platform_setup(void)
220{
Dan Handley9df48042015-03-19 18:58:55 +0000221 /* Initialize the secure environment */
222 plat_arm_security_setup();
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100223
224#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargas550eb082018-01-05 16:00:05 +0000225 arm_nor_psci_do_static_mem_protect();
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100226#endif
Dan Handley9df48042015-03-19 18:58:55 +0000227}
228
229void bl2_platform_setup(void)
230{
231 arm_bl2_platform_setup();
232}
233
234/*******************************************************************************
235 * Perform the very early platform specific architectural setup here. At the
236 * moment this is only initializes the mmu in a quick and dirty way.
237 ******************************************************************************/
238void arm_bl2_plat_arch_setup(void)
239{
Soby Mathewb9856482018-09-18 11:42:42 +0100240#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
241 /*
242 * Ensure ARM platforms don't use coherent memory in BL2 unless
243 * cryptocell integration is enabled.
244 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100245 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000246#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100247
248 const mmap_region_t bl_regions[] = {
249 MAP_BL2_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100250 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100251#if USE_ROMLIB
252 ARM_MAP_ROMLIB_CODE,
253 ARM_MAP_ROMLIB_DATA,
254#endif
Soby Mathewb9856482018-09-18 11:42:42 +0100255#if ARM_CRYPTOCELL_INTEG
256 ARM_MAP_BL_COHERENT_RAM,
257#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100258 {0}
259 };
260
261 arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100262
263#ifdef AARCH32
Antonio Nino Diaz533d3a82018-08-07 16:35:19 +0100264 enable_mmu_svc_mon(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100265#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100266 enable_mmu_el1(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100267#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100268
269 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000270}
271
272void bl2_plat_arch_setup(void)
273{
274 arm_bl2_plat_arch_setup();
275}
276
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100277#if LOAD_IMAGE_V2
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000278int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100279{
280 int err = 0;
281 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100282#ifdef SPD_opteed
283 bl_mem_params_node_t *pager_mem_params = NULL;
284 bl_mem_params_node_t *paged_mem_params = NULL;
285#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100286 assert(bl_mem_params);
287
288 switch (image_id) {
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100289#ifdef AARCH64
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100290 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100291#ifdef SPD_opteed
292 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
293 assert(pager_mem_params);
294
295 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
296 assert(paged_mem_params);
297
298 err = parse_optee_header(&bl_mem_params->ep_info,
299 &pager_mem_params->image_info,
300 &paged_mem_params->image_info);
301 if (err != 0) {
302 WARN("OPTEE header parse error.\n");
303 }
304#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100305 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
306 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100307#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100308
309 case BL33_IMAGE_ID:
310 /* BL33 expects to receive the primary CPU MPID (through r0) */
311 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
312 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
313 break;
314
315#ifdef SCP_BL2_BASE
316 case SCP_BL2_IMAGE_ID:
317 /* The subsequent handling of SCP_BL2 is platform specific */
318 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
319 if (err) {
320 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
321 }
322 break;
323#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000324 default:
325 /* Do nothing in default case */
326 break;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100327 }
328
329 return err;
330}
331
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000332/*******************************************************************************
333 * This function can be used by the platforms to update/use image
334 * information for given `image_id`.
335 ******************************************************************************/
Daniel Boulby07d26872018-06-27 16:45:48 +0100336int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000337{
338 return arm_bl2_handle_post_image_load(image_id);
339}
340
Daniel Boulby07d26872018-06-27 16:45:48 +0100341int bl2_plat_handle_post_image_load(unsigned int image_id)
342{
343 return arm_bl2_plat_handle_post_image_load(image_id);
344}
345
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100346#else /* LOAD_IMAGE_V2 */
347
Dan Handley9df48042015-03-19 18:58:55 +0000348/*******************************************************************************
Juan Castilloa72b6472015-12-10 15:49:17 +0000349 * Populate the extents of memory available for loading SCP_BL2 (if used),
Dan Handley9df48042015-03-19 18:58:55 +0000350 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
351 ******************************************************************************/
Juan Castilloa72b6472015-12-10 15:49:17 +0000352void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
Dan Handley9df48042015-03-19 18:58:55 +0000353{
Juan Castilloa72b6472015-12-10 15:49:17 +0000354 *scp_bl2_meminfo = bl2_tzram_layout;
Dan Handley9df48042015-03-19 18:58:55 +0000355}
356
357/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000358 * Before calling this function BL31 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000359 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000360 * the entrypoint of BL31 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000361 * On ARM standard platforms we only set the security state of the entrypoint
362 ******************************************************************************/
363void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
364 entry_point_info_t *bl31_ep_info)
365{
366 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
367 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
368 DISABLE_ALL_EXCEPTIONS);
369}
370
371
372/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000373 * Before calling this function BL32 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000374 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000375 * the entrypoint of BL32 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000376 * On ARM standard platforms we only set the security state of the entrypoint
377 ******************************************************************************/
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100378#ifdef BL32_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000379void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
380 entry_point_info_t *bl32_ep_info)
381{
382 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
383 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
384}
385
386/*******************************************************************************
Dan Handley9df48042015-03-19 18:58:55 +0000387 * Populate the extents of memory available for loading BL32
388 ******************************************************************************/
389void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
390{
391 /*
392 * Populate the extents of memory available for loading BL32.
393 */
394 bl32_meminfo->total_base = BL32_BASE;
395 bl32_meminfo->free_base = BL32_BASE;
396 bl32_meminfo->total_size =
397 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
398 bl32_meminfo->free_size =
399 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
400}
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100401#endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000402
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100403/*******************************************************************************
404 * Before calling this function BL33 is loaded in memory and its entrypoint
405 * is set by load_image. This is a placeholder for the platform to change
406 * the entrypoint of BL33 and set SPSR and security state.
407 * On ARM standard platforms we only set the security state of the entrypoint
408 ******************************************************************************/
409void bl2_plat_set_bl33_ep_info(image_info_t *image,
410 entry_point_info_t *bl33_ep_info)
411{
412 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
413 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
414}
Dan Handley9df48042015-03-19 18:58:55 +0000415
416/*******************************************************************************
417 * Populate the extents of memory available for loading BL33
418 ******************************************************************************/
419void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
420{
421 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
422 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
423 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
424 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
425}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100426
427#endif /* LOAD_IMAGE_V2 */