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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Louis Mayencourt1c819c32020-01-24 13:30:28 +00002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00006
7#include <assert.h>
8
9#include <platform_def.h>
10
Dan Handley9df48042015-03-19 18:58:55 +000011#include <arch.h>
12#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <common/debug.h>
14#include <common/romlib.h>
15#include <lib/mmio.h>
Manish V Badarkhe3e9bd742020-07-24 03:26:05 +010016#include <lib/smccc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <lib/xlat_tables/xlat_tables_compat.h>
Manish V Badarkhe3e9bd742020-07-24 03:26:05 +010018#include <services/arm_arch_svc.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000019#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <plat/common/platform.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021
Dan Handley9df48042015-03-19 18:58:55 +000022/* Weak definitions may be overridden in specific ARM standard platform */
23#pragma weak plat_get_ns_image_entrypoint
Vikram Kanigiri07035432015-11-12 18:52:34 +000024#pragma weak plat_arm_get_mmap
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010025
26/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
27 * conflicts with the definition in plat/common. */
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010028#pragma weak plat_get_syscnt_freq2
Roberto Vargase3adc372018-05-23 09:27:06 +010029
Manish V Badarkhef809c6e2020-02-22 08:43:00 +000030/* Get ARM SOC-ID */
31#pragma weak plat_arm_get_soc_id
32
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +000033/*******************************************************************************
34 * Changes the memory attributes for the region of mapped memory where the BL
35 * image's translation tables are located such that the tables will have
36 * read-only permissions.
37 ******************************************************************************/
38#if PLAT_RO_XLAT_TABLES
39void arm_xlat_make_tables_readonly(void)
40{
41 int rc = xlat_make_tables_readonly();
42
43 if (rc != 0) {
44 ERROR("Failed to make translation tables read-only at EL%u.\n",
45 get_current_el());
46 panic();
47 }
48
49 INFO("Translation tables are now read-only at EL%u.\n",
50 get_current_el());
51}
52#endif
Roberto Vargase3adc372018-05-23 09:27:06 +010053
54void arm_setup_romlib(void)
55{
56#if USE_ROMLIB
57 if (!rom_lib_init(ROMLIB_VERSION))
58 panic();
59#endif
60}
Dan Handley9df48042015-03-19 18:58:55 +000061
Soby Mathew21f93612016-03-23 10:11:10 +000062uintptr_t plat_get_ns_image_entrypoint(void)
Dan Handley9df48042015-03-19 18:58:55 +000063{
Soby Mathew4876ae32016-05-09 17:20:10 +010064#ifdef PRELOADED_BL33_BASE
65 return PRELOADED_BL33_BASE;
66#else
Sandrine Bailleuxafa91db2019-01-31 15:01:32 +010067 return PLAT_ARM_NS_IMAGE_BASE;
Soby Mathew4876ae32016-05-09 17:20:10 +010068#endif
Dan Handley9df48042015-03-19 18:58:55 +000069}
70
71/*******************************************************************************
72 * Gets SPSR for BL32 entry
73 ******************************************************************************/
74uint32_t arm_get_spsr_for_bl32_entry(void)
75{
76 /*
77 * The Secure Payload Dispatcher service is responsible for
Juan Castillo7d199412015-12-14 09:35:25 +000078 * setting the SPSR prior to entry into the BL32 image.
Dan Handley9df48042015-03-19 18:58:55 +000079 */
80 return 0;
81}
82
83/*******************************************************************************
84 * Gets SPSR for BL33 entry
85 ******************************************************************************/
Julius Werner8e0ef0f2019-07-09 14:02:43 -070086#ifdef __aarch64__
Dan Handley9df48042015-03-19 18:58:55 +000087uint32_t arm_get_spsr_for_bl33_entry(void)
88{
Dan Handley9df48042015-03-19 18:58:55 +000089 unsigned int mode;
90 uint32_t spsr;
91
92 /* Figure out what mode we enter the non-secure world in */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000093 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
Dan Handley9df48042015-03-19 18:58:55 +000094
95 /*
96 * TODO: Consider the possibility of specifying the SPSR in
97 * the FIP ToC and allowing the platform to have a say as
98 * well.
99 */
100 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
101 return spsr;
102}
Soby Mathew0d268dc2016-07-11 14:13:56 +0100103#else
104/*******************************************************************************
105 * Gets SPSR for BL33 entry
106 ******************************************************************************/
107uint32_t arm_get_spsr_for_bl33_entry(void)
108{
109 unsigned int hyp_status, mode, spsr;
110
111 hyp_status = GET_VIRT_EXT(read_id_pfr1());
112
113 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
114
115 /*
116 * TODO: Consider the possibility of specifying the SPSR in
117 * the FIP ToC and allowing the platform to have a say as
118 * well.
119 */
120 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
121 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
122 return spsr;
123}
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700124#endif /* __aarch64__ */
Dan Handley9df48042015-03-19 18:58:55 +0000125
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100126/*******************************************************************************
127 * Configures access to the system counter timer module.
128 ******************************************************************************/
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800129#ifdef ARM_SYS_TIMCTL_BASE
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100130void arm_configure_sys_timer(void)
131{
132 unsigned int reg_val;
133
Soby Mathew2d9f7952018-06-11 16:21:30 +0100134 /* Read the frequency of the system counter */
135 unsigned int freq_val = plat_get_syscnt_freq2();
136
Juan Castilloaadf19a2015-11-06 16:02:32 +0000137#if ARM_CONFIG_CNTACR
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000138 reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT);
139 reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT);
140 reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100141 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
Juan Castilloaadf19a2015-11-06 16:02:32 +0000142#endif /* ARM_CONFIG_CNTACR */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100143
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000144 reg_val = (1U << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100145 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
Soby Mathew2d9f7952018-06-11 16:21:30 +0100146
147 /*
148 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ
149 * system register initialized during psci_arch_setup() is different
150 * from this and has to be updated independently.
151 */
152 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
153
Sami Mujawar5eb649d2019-05-10 08:52:07 +0100154#if defined(PLAT_juno) || defined(PLAT_n1sdp)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100155 /*
156 * Initialize CNTFRQ register in Non-secure CNTBase frame.
Sami Mujawar5eb649d2019-05-10 08:52:07 +0100157 * This is only required for Juno and N1SDP, because they do not
158 * follow ARM ARM in that the value updated in CNTFRQ is not
159 * reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
Soby Mathew2d9f7952018-06-11 16:21:30 +0100160 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000161 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val);
Soby Mathew2d9f7952018-06-11 16:21:30 +0100162#endif
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100163}
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800164#endif /* ARM_SYS_TIMCTL_BASE */
Vikram Kanigiri07035432015-11-12 18:52:34 +0000165
166/*******************************************************************************
167 * Returns ARM platform specific memory map regions.
168 ******************************************************************************/
169const mmap_region_t *plat_arm_get_mmap(void)
170{
171 return plat_arm_mmap;
172}
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100173
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100174#ifdef ARM_SYS_CNTCTL_BASE
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100175
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100176unsigned int plat_get_syscnt_freq2(void)
177{
Sandrine Bailleuxa8ef6652016-06-03 15:00:46 +0100178 unsigned int counter_base_frequency;
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100179
180 /* Read the frequency from Frequency modes table */
181 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
182
183 /* The first entry of the frequency modes table must not be 0 */
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000184 if (counter_base_frequency == 0U)
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100185 panic();
186
187 return counter_base_frequency;
188}
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100189
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100190#endif /* ARM_SYS_CNTCTL_BASE */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100191
192#if SDEI_SUPPORT
193/*
194 * Translate SDEI entry point to PA, and perform standard ARM entry point
195 * validation on it.
196 */
197int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode)
198{
199 uint64_t par, pa;
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000200 u_register_t scr_el3;
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100201
202 /* Doing Non-secure address translation requires SCR_EL3.NS set */
203 scr_el3 = read_scr_el3();
204 write_scr_el3(scr_el3 | SCR_NS_BIT);
205 isb();
206
207 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1));
208 if (client_mode == MODE_EL2) {
209 /*
210 * Translate entry point to Physical Address using the EL2
211 * translation regime.
212 */
213 ats1e2r(ep);
214 } else {
215 /*
216 * Translate entry point to Physical Address using the EL1&0
217 * translation regime, including stage 2.
218 */
219 ats12e1r(ep);
220 }
221 isb();
222 par = read_par_el1();
223
224 /* Restore original SCRL_EL3 */
225 write_scr_el3(scr_el3);
226 isb();
227
228 /* If the translation resulted in fault, return failure */
229 if ((par & PAR_F_MASK) != 0)
230 return -1;
231
232 /* Extract Physical Address from PAR */
233 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT));
234
235 /* Perform NS entry point validation on the physical address */
236 return arm_validate_ns_entrypoint(pa);
237}
238#endif
Manish V Badarkhef809c6e2020-02-22 08:43:00 +0000239