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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigiri07035432015-11-12 18:52:34 +00002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#include <arch.h>
31#include <arch_helpers.h>
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010032#include <assert.h>
Yatharth Kochar3c0087a2016-04-14 14:49:37 +010033#include <debug.h>
Dan Handley9df48042015-03-19 18:58:55 +000034#include <mmio.h>
35#include <plat_arm.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +010036#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000037#include <xlat_tables.h>
38
Vikram Kanigiri07035432015-11-12 18:52:34 +000039extern const mmap_region_t plat_arm_mmap[];
Dan Handley9df48042015-03-19 18:58:55 +000040
Dan Handley9df48042015-03-19 18:58:55 +000041/* Weak definitions may be overridden in specific ARM standard platform */
42#pragma weak plat_get_ns_image_entrypoint
Vikram Kanigiri07035432015-11-12 18:52:34 +000043#pragma weak plat_arm_get_mmap
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010044
45/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
46 * conflicts with the definition in plat/common. */
47#if ERROR_DEPRECATED
48#pragma weak plat_get_syscnt_freq2
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010049#endif
Dan Handley9df48042015-03-19 18:58:55 +000050
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010051/*
52 * Set up the page tables for the generic and platform-specific memory regions.
53 * The extents of the generic memory regions are specified by the function
54 * arguments and consist of:
55 * - Trusted SRAM seen by the BL image;
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010056 * - Code section;
57 * - Read-only data section;
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010058 * - Coherent memory region, if applicable.
59 */
Soby Mathewa0fedc42016-06-16 14:52:04 +010060void arm_setup_page_tables(uintptr_t total_base,
61 size_t total_size,
62 uintptr_t code_start,
63 uintptr_t code_limit,
64 uintptr_t rodata_start,
65 uintptr_t rodata_limit
Dan Handley9df48042015-03-19 18:58:55 +000066#if USE_COHERENT_MEM
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010067 ,
Soby Mathewa0fedc42016-06-16 14:52:04 +010068 uintptr_t coh_start,
69 uintptr_t coh_limit
Dan Handley9df48042015-03-19 18:58:55 +000070#endif
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010071 )
72{
73 /*
74 * Map the Trusted SRAM with appropriate memory attributes.
75 * Subsequent mappings will adjust the attributes for specific regions.
76 */
Sandrine Bailleux12997c52016-06-20 13:57:10 +010077 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
78 (void *) total_base, (void *) (total_base + total_size));
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010079 mmap_add_region(total_base, total_base,
80 total_size,
81 MT_MEMORY | MT_RW | MT_SECURE);
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010082
83 /* Re-map the code section */
Sandrine Bailleux12997c52016-06-20 13:57:10 +010084 VERBOSE("Code region: %p - %p\n",
85 (void *) code_start, (void *) code_limit);
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010086 mmap_add_region(code_start, code_start,
87 code_limit - code_start,
88 MT_CODE | MT_SECURE);
89
90 /* Re-map the read-only data section */
Sandrine Bailleux12997c52016-06-20 13:57:10 +010091 VERBOSE("Read-only data region: %p - %p\n",
92 (void *) rodata_start, (void *) rodata_limit);
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010093 mmap_add_region(rodata_start, rodata_start,
94 rodata_limit - rodata_start,
95 MT_RO_DATA | MT_SECURE);
96
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010097#if USE_COHERENT_MEM
98 /* Re-map the coherent memory region */
Sandrine Bailleux12997c52016-06-20 13:57:10 +010099 VERBOSE("Coherent region: %p - %p\n",
100 (void *) coh_start, (void *) coh_limit);
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100101 mmap_add_region(coh_start, coh_start,
102 coh_limit - coh_start,
103 MT_DEVICE | MT_RW | MT_SECURE);
104#endif
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100105
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100106 /* Now (re-)map the platform-specific memory regions */
107 mmap_add(plat_arm_get_mmap());
Dan Handley9df48042015-03-19 18:58:55 +0000108
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100109 /* Create the page tables to reflect the above mappings */
110 init_xlat_tables();
111}
Dan Handley9df48042015-03-19 18:58:55 +0000112
Soby Mathew21f93612016-03-23 10:11:10 +0000113uintptr_t plat_get_ns_image_entrypoint(void)
Dan Handley9df48042015-03-19 18:58:55 +0000114{
Soby Mathew4876ae32016-05-09 17:20:10 +0100115#ifdef PRELOADED_BL33_BASE
116 return PRELOADED_BL33_BASE;
117#else
Dan Handley9df48042015-03-19 18:58:55 +0000118 return PLAT_ARM_NS_IMAGE_OFFSET;
Soby Mathew4876ae32016-05-09 17:20:10 +0100119#endif
Dan Handley9df48042015-03-19 18:58:55 +0000120}
121
122/*******************************************************************************
123 * Gets SPSR for BL32 entry
124 ******************************************************************************/
125uint32_t arm_get_spsr_for_bl32_entry(void)
126{
127 /*
128 * The Secure Payload Dispatcher service is responsible for
Juan Castillo7d199412015-12-14 09:35:25 +0000129 * setting the SPSR prior to entry into the BL32 image.
Dan Handley9df48042015-03-19 18:58:55 +0000130 */
131 return 0;
132}
133
134/*******************************************************************************
135 * Gets SPSR for BL33 entry
136 ******************************************************************************/
Soby Mathew0d268dc2016-07-11 14:13:56 +0100137#ifndef AARCH32
Dan Handley9df48042015-03-19 18:58:55 +0000138uint32_t arm_get_spsr_for_bl33_entry(void)
139{
140 unsigned long el_status;
141 unsigned int mode;
142 uint32_t spsr;
143
144 /* Figure out what mode we enter the non-secure world in */
145 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
146 el_status &= ID_AA64PFR0_ELX_MASK;
147
148 mode = (el_status) ? MODE_EL2 : MODE_EL1;
149
150 /*
151 * TODO: Consider the possibility of specifying the SPSR in
152 * the FIP ToC and allowing the platform to have a say as
153 * well.
154 */
155 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
156 return spsr;
157}
Soby Mathew0d268dc2016-07-11 14:13:56 +0100158#else
159/*******************************************************************************
160 * Gets SPSR for BL33 entry
161 ******************************************************************************/
162uint32_t arm_get_spsr_for_bl33_entry(void)
163{
164 unsigned int hyp_status, mode, spsr;
165
166 hyp_status = GET_VIRT_EXT(read_id_pfr1());
167
168 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
169
170 /*
171 * TODO: Consider the possibility of specifying the SPSR in
172 * the FIP ToC and allowing the platform to have a say as
173 * well.
174 */
175 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
176 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
177 return spsr;
178}
179#endif /* AARCH32 */
Dan Handley9df48042015-03-19 18:58:55 +0000180
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100181/*******************************************************************************
182 * Configures access to the system counter timer module.
183 ******************************************************************************/
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800184#ifdef ARM_SYS_TIMCTL_BASE
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100185void arm_configure_sys_timer(void)
186{
187 unsigned int reg_val;
188
Juan Castilloaadf19a2015-11-06 16:02:32 +0000189#if ARM_CONFIG_CNTACR
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100190 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
191 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
192 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
193 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
Juan Castilloaadf19a2015-11-06 16:02:32 +0000194#endif /* ARM_CONFIG_CNTACR */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100195
196 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
197 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
198}
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800199#endif /* ARM_SYS_TIMCTL_BASE */
Vikram Kanigiri07035432015-11-12 18:52:34 +0000200
201/*******************************************************************************
202 * Returns ARM platform specific memory map regions.
203 ******************************************************************************/
204const mmap_region_t *plat_arm_get_mmap(void)
205{
206 return plat_arm_mmap;
207}
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100208
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100209#ifdef ARM_SYS_CNTCTL_BASE
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100210
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100211unsigned int plat_get_syscnt_freq2(void)
212{
Sandrine Bailleuxa8ef6652016-06-03 15:00:46 +0100213 unsigned int counter_base_frequency;
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100214
215 /* Read the frequency from Frequency modes table */
216 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
217
218 /* The first entry of the frequency modes table must not be 0 */
219 if (counter_base_frequency == 0)
220 panic();
221
222 return counter_base_frequency;
223}
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100224
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100225#endif /* ARM_SYS_CNTCTL_BASE */