Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | #include <arch.h> |
| 31 | #include <arch_helpers.h> |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 32 | #include <assert.h> |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 33 | #include <debug.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 34 | #include <mmio.h> |
| 35 | #include <plat_arm.h> |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 36 | #include <platform_def.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 37 | #include <xlat_tables.h> |
| 38 | |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 39 | extern const mmap_region_t plat_arm_mmap[]; |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 40 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 41 | /* Weak definitions may be overridden in specific ARM standard platform */ |
| 42 | #pragma weak plat_get_ns_image_entrypoint |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 43 | #pragma weak plat_arm_get_mmap |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 44 | |
| 45 | /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid |
| 46 | * conflicts with the definition in plat/common. */ |
| 47 | #if ERROR_DEPRECATED |
| 48 | #pragma weak plat_get_syscnt_freq2 |
| 49 | #else |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 50 | #pragma weak plat_get_syscnt_freq |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 51 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 52 | |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 53 | /* |
| 54 | * Set up the page tables for the generic and platform-specific memory regions. |
| 55 | * The extents of the generic memory regions are specified by the function |
| 56 | * arguments and consist of: |
| 57 | * - Trusted SRAM seen by the BL image; |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame^] | 58 | * - Code section; |
| 59 | * - Read-only data section; |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 60 | * - Coherent memory region, if applicable. |
| 61 | */ |
| 62 | void arm_setup_page_tables(unsigned long total_base, |
| 63 | unsigned long total_size, |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame^] | 64 | unsigned long code_start, |
| 65 | unsigned long code_limit, |
| 66 | unsigned long rodata_start, |
| 67 | unsigned long rodata_limit |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 68 | #if USE_COHERENT_MEM |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 69 | , |
| 70 | unsigned long coh_start, |
| 71 | unsigned long coh_limit |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 72 | #endif |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 73 | ) |
| 74 | { |
| 75 | /* |
| 76 | * Map the Trusted SRAM with appropriate memory attributes. |
| 77 | * Subsequent mappings will adjust the attributes for specific regions. |
| 78 | */ |
| 79 | mmap_add_region(total_base, total_base, |
| 80 | total_size, |
| 81 | MT_MEMORY | MT_RW | MT_SECURE); |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame^] | 82 | |
| 83 | /* Re-map the code section */ |
| 84 | mmap_add_region(code_start, code_start, |
| 85 | code_limit - code_start, |
| 86 | MT_CODE | MT_SECURE); |
| 87 | |
| 88 | /* Re-map the read-only data section */ |
| 89 | mmap_add_region(rodata_start, rodata_start, |
| 90 | rodata_limit - rodata_start, |
| 91 | MT_RO_DATA | MT_SECURE); |
| 92 | |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 93 | #if USE_COHERENT_MEM |
| 94 | /* Re-map the coherent memory region */ |
| 95 | mmap_add_region(coh_start, coh_start, |
| 96 | coh_limit - coh_start, |
| 97 | MT_DEVICE | MT_RW | MT_SECURE); |
| 98 | #endif |
Sandrine Bailleux | ecdc4d3 | 2016-07-08 14:38:16 +0100 | [diff] [blame^] | 99 | |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 100 | /* Now (re-)map the platform-specific memory regions */ |
| 101 | mmap_add(plat_arm_get_mmap()); |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 102 | |
Sandrine Bailleux | 4a1267a | 2016-05-18 16:11:47 +0100 | [diff] [blame] | 103 | /* Create the page tables to reflect the above mappings */ |
| 104 | init_xlat_tables(); |
| 105 | } |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 106 | |
Soby Mathew | 21f9361 | 2016-03-23 10:11:10 +0000 | [diff] [blame] | 107 | uintptr_t plat_get_ns_image_entrypoint(void) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 108 | { |
| 109 | return PLAT_ARM_NS_IMAGE_OFFSET; |
| 110 | } |
| 111 | |
| 112 | /******************************************************************************* |
| 113 | * Gets SPSR for BL32 entry |
| 114 | ******************************************************************************/ |
| 115 | uint32_t arm_get_spsr_for_bl32_entry(void) |
| 116 | { |
| 117 | /* |
| 118 | * The Secure Payload Dispatcher service is responsible for |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 119 | * setting the SPSR prior to entry into the BL32 image. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 120 | */ |
| 121 | return 0; |
| 122 | } |
| 123 | |
| 124 | /******************************************************************************* |
| 125 | * Gets SPSR for BL33 entry |
| 126 | ******************************************************************************/ |
| 127 | uint32_t arm_get_spsr_for_bl33_entry(void) |
| 128 | { |
| 129 | unsigned long el_status; |
| 130 | unsigned int mode; |
| 131 | uint32_t spsr; |
| 132 | |
| 133 | /* Figure out what mode we enter the non-secure world in */ |
| 134 | el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; |
| 135 | el_status &= ID_AA64PFR0_ELX_MASK; |
| 136 | |
| 137 | mode = (el_status) ? MODE_EL2 : MODE_EL1; |
| 138 | |
| 139 | /* |
| 140 | * TODO: Consider the possibility of specifying the SPSR in |
| 141 | * the FIP ToC and allowing the platform to have a say as |
| 142 | * well. |
| 143 | */ |
| 144 | spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 145 | return spsr; |
| 146 | } |
| 147 | |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 148 | /******************************************************************************* |
| 149 | * Configures access to the system counter timer module. |
| 150 | ******************************************************************************/ |
Soren Brinkmann | 3d80b71 | 2016-03-06 20:23:39 -0800 | [diff] [blame] | 151 | #ifdef ARM_SYS_TIMCTL_BASE |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 152 | void arm_configure_sys_timer(void) |
| 153 | { |
| 154 | unsigned int reg_val; |
| 155 | |
Juan Castillo | aadf19a | 2015-11-06 16:02:32 +0000 | [diff] [blame] | 156 | #if ARM_CONFIG_CNTACR |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 157 | reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); |
| 158 | reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); |
| 159 | reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); |
| 160 | mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); |
Juan Castillo | aadf19a | 2015-11-06 16:02:32 +0000 | [diff] [blame] | 161 | #endif /* ARM_CONFIG_CNTACR */ |
Soby Mathew | 61e8d0b | 2015-10-12 17:32:29 +0100 | [diff] [blame] | 162 | |
| 163 | reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); |
| 164 | mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); |
| 165 | } |
Soren Brinkmann | 3d80b71 | 2016-03-06 20:23:39 -0800 | [diff] [blame] | 166 | #endif /* ARM_SYS_TIMCTL_BASE */ |
Vikram Kanigiri | 0703543 | 2015-11-12 18:52:34 +0000 | [diff] [blame] | 167 | |
| 168 | /******************************************************************************* |
| 169 | * Returns ARM platform specific memory map regions. |
| 170 | ******************************************************************************/ |
| 171 | const mmap_region_t *plat_arm_get_mmap(void) |
| 172 | { |
| 173 | return plat_arm_mmap; |
| 174 | } |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 175 | |
Yatharth Kochar | 0b49fb7 | 2016-04-26 10:36:29 +0100 | [diff] [blame] | 176 | #ifdef ARM_SYS_CNTCTL_BASE |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 177 | |
| 178 | #if ERROR_DEPRECATED |
| 179 | unsigned int plat_get_syscnt_freq2(void) |
| 180 | { |
Sandrine Bailleux | a8ef665 | 2016-06-03 15:00:46 +0100 | [diff] [blame] | 181 | unsigned int counter_base_frequency; |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 182 | #else |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 183 | unsigned long long plat_get_syscnt_freq(void) |
| 184 | { |
| 185 | unsigned long long counter_base_frequency; |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 186 | #endif /* ERROR_DEPRECATED */ |
Yatharth Kochar | 3c0087a | 2016-04-14 14:49:37 +0100 | [diff] [blame] | 187 | |
| 188 | /* Read the frequency from Frequency modes table */ |
| 189 | counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); |
| 190 | |
| 191 | /* The first entry of the frequency modes table must not be 0 */ |
| 192 | if (counter_base_frequency == 0) |
| 193 | panic(); |
| 194 | |
| 195 | return counter_base_frequency; |
| 196 | } |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 197 | |
Yatharth Kochar | 0b49fb7 | 2016-04-26 10:36:29 +0100 | [diff] [blame] | 198 | #endif /* ARM_SYS_CNTCTL_BASE */ |