Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 1 | /* |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __ZYNQMP_DEF_H__ |
| 8 | #define __ZYNQMP_DEF_H__ |
| 9 | |
| 10 | #include <common_def.h> |
| 11 | |
Soren Brinkmann | 99c0d7b | 2016-06-10 09:57:14 -0700 | [diff] [blame] | 12 | #define ZYNQMP_CONSOLE_ID_cadence 1 |
| 13 | #define ZYNQMP_CONSOLE_ID_cadence0 1 |
| 14 | #define ZYNQMP_CONSOLE_ID_cadence1 2 |
| 15 | #define ZYNQMP_CONSOLE_ID_dcc 3 |
| 16 | |
| 17 | #define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) |
| 18 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 19 | /* Firmware Image Package */ |
| 20 | #define ZYNQMP_PRIMARY_CPU 0 |
| 21 | |
| 22 | /* Memory location options for Shared data and TSP in ZYNQMP */ |
| 23 | #define ZYNQMP_IN_TRUSTED_SRAM 0 |
| 24 | #define ZYNQMP_IN_TRUSTED_DRAM 1 |
| 25 | |
| 26 | /******************************************************************************* |
| 27 | * ZYNQMP memory map related constants |
| 28 | ******************************************************************************/ |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 29 | /* Aggregate of all devices in the first GB */ |
| 30 | #define DEVICE0_BASE 0xFF000000 |
| 31 | #define DEVICE0_SIZE 0x00E00000 |
| 32 | #define DEVICE1_BASE 0xF9000000 |
Soren Brinkmann | 845cd5c | 2016-04-22 10:02:46 -0700 | [diff] [blame] | 33 | #define DEVICE1_SIZE 0x00800000 |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 34 | |
| 35 | /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ |
| 36 | #define CRF_APB_BASE 0xFD1A0000 |
| 37 | #define CRF_APB_SIZE 0x00600000 |
| 38 | |
| 39 | /* CRF registers and bitfields */ |
| 40 | #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) |
| 41 | |
| 42 | #define CRF_APB_RST_FPD_APU_ACPU_RESET (1 << 0) |
| 43 | #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (1 << 10) |
| 44 | |
| 45 | /* CRL registers and bitfields */ |
| 46 | #define CRL_APB_BASE 0xFF5E0000 |
| 47 | #define CRL_APB_RPLL_CTRL (CRL_APB_BASE + 0x30) |
Soren Brinkmann | b43d943 | 2016-04-18 11:49:42 -0700 | [diff] [blame] | 48 | #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 49 | #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 50 | #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 51 | |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 52 | #define CRL_APB_RPU_AMBA_RESET (1 << 2) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 53 | #define CRL_APB_RPLL_CTRL_BYPASS (1 << 3) |
| 54 | |
| 55 | #define CRL_APB_RESET_CTRL_SOFT_RESET (1 << 4) |
| 56 | |
Soren Brinkmann | b43d943 | 2016-04-18 11:49:42 -0700 | [diff] [blame] | 57 | #define CRL_APB_BOOT_MODE_MASK (0xf << 0) |
| 58 | #define ZYNQMP_BOOTMODE_JTAG 0 |
| 59 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 60 | /* system counter registers and bitfields */ |
| 61 | #define IOU_SCNTRS_BASE 0xFF260000 |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 62 | #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) |
| 63 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 64 | /* APU registers and bitfields */ |
| 65 | #define APU_BASE 0xFD5C0000 |
| 66 | #define APU_CONFIG_0 (APU_BASE + 0x20) |
| 67 | #define APU_RVBAR_L_0 (APU_BASE + 0x40) |
| 68 | #define APU_RVBAR_H_0 (APU_BASE + 0x44) |
| 69 | #define APU_PWRCTL (APU_BASE + 0x90) |
| 70 | |
| 71 | #define APU_CONFIG_0_VINITHI_SHIFT 8 |
| 72 | #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 |
| 73 | #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 |
| 74 | #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 |
| 75 | #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 |
| 76 | |
| 77 | /* PMU registers and bitfields */ |
| 78 | #define PMU_GLOBAL_BASE 0xFFD80000 |
| 79 | #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) |
Michal Simek | ef8f559 | 2015-06-15 14:22:50 +0200 | [diff] [blame] | 80 | #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 81 | #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) |
| 82 | #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) |
| 83 | #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) |
| 84 | #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) |
| 85 | |
| 86 | #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) |
| 87 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 88 | /******************************************************************************* |
| 89 | * CCI-400 related constants |
| 90 | ******************************************************************************/ |
| 91 | #define PLAT_ARM_CCI_BASE 0xFD6E0000 |
| 92 | #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 |
| 93 | #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 |
| 94 | |
| 95 | /******************************************************************************* |
| 96 | * GIC-400 & interrupt handling related constants |
| 97 | ******************************************************************************/ |
| 98 | #define BASE_GICD_BASE 0xF9010000 |
| 99 | #define BASE_GICC_BASE 0xF9020000 |
| 100 | #define BASE_GICH_BASE 0xF9040000 |
| 101 | #define BASE_GICV_BASE 0xF9060000 |
| 102 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 103 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
| 104 | |
| 105 | #define ARM_IRQ_SEC_SGI_0 8 |
| 106 | #define ARM_IRQ_SEC_SGI_1 9 |
| 107 | #define ARM_IRQ_SEC_SGI_2 10 |
| 108 | #define ARM_IRQ_SEC_SGI_3 11 |
| 109 | #define ARM_IRQ_SEC_SGI_4 12 |
| 110 | #define ARM_IRQ_SEC_SGI_5 13 |
| 111 | #define ARM_IRQ_SEC_SGI_6 14 |
| 112 | #define ARM_IRQ_SEC_SGI_7 15 |
| 113 | |
| 114 | #define MAX_INTR_EL3 128 |
| 115 | |
| 116 | /******************************************************************************* |
| 117 | * UART related constants |
| 118 | ******************************************************************************/ |
| 119 | #define ZYNQMP_UART0_BASE 0xFF000000 |
Soren Brinkmann | 836418d | 2016-05-27 08:56:53 -0700 | [diff] [blame] | 120 | #define ZYNQMP_UART1_BASE 0xFF010000 |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 121 | |
Soren Brinkmann | 99c0d7b | 2016-06-10 09:57:14 -0700 | [diff] [blame] | 122 | #if ZYNQMP_CONSOLE_IS(cadence) |
| 123 | # define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE |
| 124 | #elif ZYNQMP_CONSOLE_IS(cadence1) |
| 125 | # define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE |
| 126 | #else |
| 127 | # error "invalid ZYNQMP_CONSOLE" |
| 128 | #endif |
| 129 | |
| 130 | #define PLAT_ARM_CRASH_UART_BASE ZYNQMP_UART_BASE |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 131 | /* impossible to call C routine how it is done now - hardcode any value */ |
| 132 | #define PLAT_ARM_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */ |
| 133 | |
| 134 | /* Must be non zero */ |
| 135 | #define ZYNQMP_UART_BAUDRATE 115200 |
| 136 | #define ARM_CONSOLE_BAUDRATE ZYNQMP_UART_BAUDRATE |
| 137 | |
| 138 | /* Silicon version detection */ |
| 139 | #define ZYNQMP_SILICON_VER_MASK 0xF000 |
| 140 | #define ZYNQMP_SILICON_VER_SHIFT 12 |
| 141 | #define ZYNQMP_CSU_VERSION_SILICON 0 |
| 142 | #define ZYNQMP_CSU_VERSION_EP108 1 |
| 143 | #define ZYNQMP_CSU_VERSION_VELOCE 2 |
| 144 | #define ZYNQMP_CSU_VERSION_QEMU 3 |
| 145 | |
| 146 | #define ZYNQMP_RTL_VER_MASK 0xFF0 |
| 147 | #define ZYNQMP_RTL_VER_SHIFT 4 |
| 148 | |
| 149 | #define ZYNQMP_PS_VER_MASK 0xF |
| 150 | #define ZYNQMP_PS_VER_SHIFT 0 |
| 151 | |
| 152 | #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 |
| 153 | #define ZYNQMP_CSU_IDCODE_OFFSET 0x40 |
| 154 | |
| 155 | #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0 |
| 156 | #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFF << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) |
| 157 | #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 |
| 158 | |
| 159 | #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 |
| 160 | #define ZYNQMP_CSU_IDCODE_SVD_MASK (0xE << ZYNQMP_CSU_IDCODE_SVD_SHIFT) |
| 161 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 |
| 162 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xF << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) |
| 163 | #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19 |
| 164 | #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3 << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) |
| 165 | #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21 |
| 166 | #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7F << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) |
| 167 | #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 |
| 168 | |
| 169 | #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28 |
| 170 | #define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xF << ZYNQMP_CSU_IDCODE_REVISION_SHIFT) |
| 171 | #define ZYNQMP_CSU_IDCODE_REVISION 0 |
| 172 | |
| 173 | #define ZYNQMP_CSU_VERSION_OFFSET 0x44 |
| 174 | |
Naga Sureshkumar Relli | cf4e714 | 2016-07-01 12:46:43 +0530 | [diff] [blame] | 175 | /* Access control register defines */ |
| 176 | #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) |
| 177 | #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) |
| 178 | |
Rajan Vaja | 0ac2be1 | 2018-01-17 02:39:21 -0800 | [diff] [blame] | 179 | #define IOU_SLCR_BASEADDR 0xFF180000 |
| 180 | |
Rajan Vaja | 5529a01 | 2018-01-17 02:39:23 -0800 | [diff] [blame] | 181 | #define ZYNQMP_RPU_GLBL_CNTL 0xFF9A0000 |
| 182 | #define ZYNQMP_RPU0_CFG 0xFF9A0100 |
| 183 | #define ZYNQMP_RPU1_CFG 0xFF9A0200 |
| 184 | #define ZYNQMP_SLSPLIT_MASK 0x08 |
| 185 | #define ZYNQMP_TCM_COMB_MASK 0x40 |
| 186 | #define ZYNQMP_SLCLAMP_MASK 0x10 |
| 187 | #define ZYNQMP_VINITHI_MASK 0x04 |
| 188 | |
Rajan Vaja | aea41bb | 2018-01-17 02:39:24 -0800 | [diff] [blame] | 189 | /* Tap delay bypass */ |
| 190 | #define IOU_TAPDLY_BYPASS 0XFF180390 |
| 191 | #define TAP_DELAY_MASK 0x7 |
| 192 | |
| 193 | /* SGMII mode */ |
| 194 | #define IOU_GEM_CTRL 0xFF180360 |
| 195 | #define IOU_GEM_CLK_CTRL 0xFF180308 |
| 196 | #define SGMII_SD_MASK 0x3 |
| 197 | #define SGMII_SD_OFFSET 2 |
| 198 | #define SGMII_PCS_SD_0 0x0 |
| 199 | #define SGMII_PCS_SD_1 0x1 |
| 200 | #define SGMII_PCS_SD_PHY 0x2 |
| 201 | #define GEM_SGMII_MASK 0x4 |
| 202 | #define GEM_CLK_CTRL_MASK 0xF |
| 203 | #define GEM_CLK_CTRL_OFFSET 5 |
| 204 | #define GEM_RX_SRC_SEL_GTR 0x1 |
| 205 | #define GEM_SGMII_MODE 0x4 |
| 206 | |
| 207 | /* SD DLL reset */ |
| 208 | #define ZYNQMP_SD_DLL_CTRL 0xFF180358 |
| 209 | #define ZYNQMP_SD0_DLL_RST_MASK 0x00000004 |
| 210 | #define ZYNQMP_SD0_DLL_RST 0x00000004 |
| 211 | #define ZYNQMP_SD1_DLL_RST_MASK 0x00040000 |
| 212 | #define ZYNQMP_SD1_DLL_RST 0x00040000 |
| 213 | |
| 214 | /* SD tap delay */ |
| 215 | #define ZYNQMP_SD_DLL_CTRL 0xFF180358 |
| 216 | #define ZYNQMP_SD_ITAP_DLY 0xFF180314 |
| 217 | #define ZYNQMP_SD_OTAP_DLY 0xFF180318 |
| 218 | #define ZYNQMP_SD_TAP_OFFSET 16 |
| 219 | #define ZYNQMP_SD_ITAPCHGWIN_MASK 0x200 |
| 220 | #define ZYNQMP_SD_ITAPCHGWIN 0x200 |
| 221 | #define ZYNQMP_SD_ITAPDLYENA_MASK 0x100 |
| 222 | #define ZYNQMP_SD_ITAPDLYENA 0x100 |
| 223 | #define ZYNQMP_SD_ITAPDLYSEL_MASK 0xFF |
| 224 | #define ZYNQMP_SD_OTAPDLYSEL_MASK 0x3F |
| 225 | #define ZYNQMP_SD_OTAPDLYENA_MASK 0x40 |
| 226 | #define ZYNQMP_SD_OTAPDLYENA 0x40 |
| 227 | |
Soren Brinkmann | 76fcae3 | 2016-03-06 20:16:27 -0800 | [diff] [blame] | 228 | #endif /* __ZYNQMP_DEF_H__ */ |