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Dan Handley610e7e12018-03-01 18:44:00 +00001Trusted Firmware-A User Guide
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
Dan Handley610e7e12018-03-01 18:44:00 +000010This document describes how to build Trusted Firmware-A (TF-A) and run it with a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010011tested set of other software components using defined configurations on the Juno
Dan Handley610e7e12018-03-01 18:44:00 +000012Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
Douglas Raillardd7c21b72017-06-28 15:23:03 +010013possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
Joel Huttonfe027712018-03-19 11:59:57 +000041The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
Douglas Raillardd7c21b72017-06-28 15:23:03 +010042building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
Dan Handley610e7e12018-03-01 18:44:00 +000051Install the required packages to build TF-A with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010052
53::
54
Sathees Balya2d0aeb02018-07-10 14:46:51 +010055 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
Douglas Raillardd7c21b72017-06-28 15:23:03 +010056
David Cunado05845bf2017-12-19 16:33:25 +000057TF-A has been tested with Linaro Release 18.04.
David Cunadob2de0992017-06-29 12:01:33 +010058
Douglas Raillardd7c21b72017-06-28 15:23:03 +010059Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010060The `Linaro Release Notes`_ documents which version of the compiler to use for a
61given Linaro Release. Also, these `Linaro instructions`_ provide further
62guidance and a script, which can be used to download Linaro deliverables
63automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010064
Roberto Vargas0489bc02018-04-16 15:43:26 +010065Optionally, TF-A can be built using clang version 4.0 or newer or Arm
66Compiler 6. See instructions below on how to switch the default compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010067
68In addition, the following optional packages and tools may be needed:
69
Sathees Balya017a67e2018-08-17 10:22:01 +010070- ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
71 Tree (FDT) source files (``.dts`` files) provided with this software. The
72 version of dtc must be 1.4.6 or above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010073
Dan Handley610e7e12018-03-01 18:44:00 +000074- For debugging, Arm `Development Studio 5 (DS-5)`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010075
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010076- To create and modify the diagram files included in the documentation, `Dia`_.
77 This tool can be found in most Linux distributions. Inkscape is needed to
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010078 generate the actual \*.png files.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010079
Dan Handley610e7e12018-03-01 18:44:00 +000080Getting the TF-A source code
81----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010082
Dan Handley610e7e12018-03-01 18:44:00 +000083Download the TF-A source code from Github:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010084
85::
86
87 git clone https://github.com/ARM-software/arm-trusted-firmware.git
88
Paul Beesley8b4bdeb2019-01-21 12:06:24 +000089Checking source code style
90~~~~~~~~~~~~~~~~~~~~~~~~~~
91
92Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the
93source, for submission to the project, the source must be in compliance with
94this style guide.
95
96Additional, project-specific guidelines are defined in the `Trusted Firmware-A
97Coding Guidelines`_ document.
98
99To assist with coding style compliance, the project Makefile contains two
100targets which both utilise the `checkpatch.pl` script that ships with the Linux
101source tree. The project also defines certain *checkpatch* options in the
102``.checkpatch.conf`` file in the top-level directory.
103
104**Note:** Checkpatch errors will gate upstream merging of pull requests.
105Checkpatch warnings will not gate merging but should be reviewed and fixed if
106possible.
107
108To check the entire source tree, you must first download copies of
109``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
110in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
111environment variable to point to ``checkpatch.pl`` (with the other 2 files in
112the same directory) and build the `checkcodebase` target:
113
114::
115
116 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
117
118To just check the style on the files that differ between your local branch and
119the remote master, use:
120
121::
122
123 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
124
125If you wish to check your patch against something other than the remote master,
126set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
127is set to ``origin/master``.
128
Dan Handley610e7e12018-03-01 18:44:00 +0000129Building TF-A
130-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100131
Dan Handley610e7e12018-03-01 18:44:00 +0000132- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
133 to the Linaro cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100134
135 For AArch64:
136
137 ::
138
139 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
140
141 For AArch32:
142
143 ::
144
145 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
146
Roberto Vargas07b1e242018-04-23 08:38:12 +0100147 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
148 ``CC`` needs to point to the clang or armclang binary, which will
149 also select the clang or armclang assembler. Be aware that the
150 GNU linker is used by default. In case of being needed the linker
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000151 can be overridden using the ``LD`` variable. Clang linker version 6 is
Roberto Vargas07b1e242018-04-23 08:38:12 +0100152 known to work with TF-A.
153
154 In both cases ``CROSS_COMPILE`` should be set as described above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100155
Dan Handley610e7e12018-03-01 18:44:00 +0000156 Arm Compiler 6 will be selected when the base name of the path assigned
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100157 to ``CC`` matches the string 'armclang'.
158
Dan Handley610e7e12018-03-01 18:44:00 +0000159 For AArch64 using Arm Compiler 6:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100160
161 ::
162
163 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
164 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
165
166 Clang will be selected when the base name of the path assigned to ``CC``
167 contains the string 'clang'. This is to allow both clang and clang-X.Y
168 to work.
169
170 For AArch64 using clang:
171
172 ::
173
174 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
175 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
176
Dan Handley610e7e12018-03-01 18:44:00 +0000177- Change to the root directory of the TF-A source tree and build.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100178
179 For AArch64:
180
181 ::
182
183 make PLAT=<platform> all
184
185 For AArch32:
186
187 ::
188
189 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
190
191 Notes:
192
193 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
194 `Summary of build options`_ for more information on available build
195 options.
196
197 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
198
199 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
200 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
Dan Handley610e7e12018-03-01 18:44:00 +0000201 provided by TF-A to demonstrate how PSCI Library can be integrated with
202 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
203 include other runtime services, for example Trusted OS services. A guide
204 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
205 `here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
207 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
208 image, is not compiled in by default. Refer to the
209 `Building the Test Secure Payload`_ section below.
210
211 - By default this produces a release version of the build. To produce a
212 debug version instead, refer to the "Debugging options" section below.
213
214 - The build process creates products in a ``build`` directory tree, building
215 the objects and binaries for each boot loader stage in separate
216 sub-directories. The following boot loader binary files are created
217 from the corresponding ELF files:
218
219 - ``build/<platform>/<build-type>/bl1.bin``
220 - ``build/<platform>/<build-type>/bl2.bin``
221 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
222 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
223
224 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
225 is either ``debug`` or ``release``. The actual number of images might differ
226 depending on the platform.
227
228- Build products for a specific build variant can be removed using:
229
230 ::
231
232 make DEBUG=<D> PLAT=<platform> clean
233
234 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
235
236 The build tree can be removed completely using:
237
238 ::
239
240 make realclean
241
242Summary of build options
243~~~~~~~~~~~~~~~~~~~~~~~~
244
Dan Handley610e7e12018-03-01 18:44:00 +0000245The TF-A build system supports the following build options. Unless mentioned
246otherwise, these options are expected to be specified at the build command
247line and are not to be modified in any component makefiles. Note that the
248build system doesn't track dependency for build options. Therefore, if any of
249the build options are changed from a previous build, a clean build must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100250performed.
251
252Common build options
253^^^^^^^^^^^^^^^^^^^^
254
Antonio Nino Diaz80914a82018-08-08 16:28:43 +0100255- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
256 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
257 code having a smaller resulting size.
258
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100259- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
260 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
261 directory containing the SP source, relative to the ``bl32/``; the directory
262 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
263
Dan Handley610e7e12018-03-01 18:44:00 +0000264- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
265 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
266 ``aarch64``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100267
Dan Handley610e7e12018-03-01 18:44:00 +0000268- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
269 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
270 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
271 `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100272
Dan Handley610e7e12018-03-01 18:44:00 +0000273- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
274 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
275 *Armv8 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100276
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100277- ``BL2``: This is an optional build option which specifies the path to BL2
Dan Handley610e7e12018-03-01 18:44:00 +0000278 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
279 built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100280
281- ``BL2U``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000282 BL2U image. In this case, the BL2U in TF-A will not be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100283
John Tsichritzisee10e792018-06-06 09:38:10 +0100284- ``BL2_AT_EL3``: This is an optional build option that enables the use of
Roberto Vargasb1584272017-11-20 13:36:10 +0000285 BL2 at EL3 execution level.
286
John Tsichritzisee10e792018-06-06 09:38:10 +0100287- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000288 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
289 the RW sections in RAM, while leaving the RO sections in place. This option
290 enable this use-case. For now, this option is only supported when BL2_AT_EL3
291 is set to '1'.
292
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100293- ``BL31``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000294 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
295 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100296
297- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
298 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
299 this file name will be used to save the key.
300
301- ``BL32``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000302 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
303 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100304
John Tsichritzisee10e792018-06-06 09:38:10 +0100305- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100306 Trusted OS Extra1 image for the ``fip`` target.
307
John Tsichritzisee10e792018-06-06 09:38:10 +0100308- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100309 Trusted OS Extra2 image for the ``fip`` target.
310
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100311- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
312 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
313 this file name will be used to save the key.
314
315- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
Dan Handley610e7e12018-03-01 18:44:00 +0000316 ``fip`` target in case TF-A BL2 is used.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100317
318- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
319 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
320 this file name will be used to save the key.
321
322- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
323 compilation of each build. It must be set to a C string (including quotes
324 where applicable). Defaults to a string that contains the time and date of
325 the compilation.
326
Dan Handley610e7e12018-03-01 18:44:00 +0000327- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF-A
328 build to be uniquely identified. Defaults to the current git commit id.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100329
330- ``CFLAGS``: Extra user options appended on the compiler's command line in
331 addition to the options set by the build system.
332
333- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
334 release several CPUs out of reset. It can take either 0 (several CPUs may be
335 brought up) or 1 (only one CPU will ever be brought up during cold reset).
336 Default is 0. If the platform always brings up a single CPU, there is no
337 need to distinguish between primary and secondary CPUs and the boot path can
338 be optimised. The ``plat_is_my_cpu_primary()`` and
339 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
340 to be implemented in this case.
341
342- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
343 register state when an unexpected exception occurs during execution of
344 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
345 this is only enabled for a debug build of the firmware.
346
347- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
348 certificate generation tool to create new keys in case no valid keys are
349 present or specified. Allowed options are '0' or '1'. Default is '1'.
350
351- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
352 the AArch32 system registers to be included when saving and restoring the
353 CPU context. The option must be set to 0 for AArch64-only platforms (that
354 is on hardware that does not implement AArch32, or at least not at EL1 and
355 higher ELs). Default value is 1.
356
357- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
358 registers to be included when saving and restoring the CPU context. Default
359 is 0.
360
361- ``DEBUG``: Chooses between a debug and release build. It can take either 0
362 (release) or 1 (debug) as values. 0 is the default.
363
John Tsichritzisee10e792018-06-06 09:38:10 +0100364- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
365 Board Boot authentication at runtime. This option is meant to be enabled only
Roberto Vargas025946a2018-09-24 17:20:48 +0100366 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
367 flag has to be enabled. 0 is the default.
Soby Mathew9fe88042018-03-26 12:43:37 +0100368
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100369- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
370 the normal boot flow. It must specify the entry point address of the EL3
371 payload. Please refer to the "Booting an EL3 payload" section for more
372 details.
373
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100374- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100375 This is an optional architectural feature available on v8.4 onwards. Some
376 v8.2 implementations also implement an AMU and this option can be used to
377 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100378
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100379- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
380 are compiled out. For debug builds, this option defaults to 1, and calls to
381 ``assert()`` are left in place. For release builds, this option defaults to 0
382 and calls to ``assert()`` function are compiled out. This option can be set
383 independently of ``DEBUG``. It can also be used to hide any auxiliary code
384 that is only required for the assertion and does not fit in the assertion
385 itself.
386
Douglas Raillard77414632018-08-21 12:54:45 +0100387- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
388 dumps or not. It is supported in both AArch64 and AArch32. However, in
389 AArch32 the format of the frame records are not defined in the AAPCS and they
390 are defined by the implementation. This implementation of backtrace only
391 supports the format used by GCC when T32 interworking is disabled. For this
392 reason enabling this option in AArch32 will force the compiler to only
393 generate A32 code. This option is enabled by default only in AArch64 debug
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000394 builds, but this behaviour can be overridden in each platform's Makefile or
395 in the build command line.
Douglas Raillard77414632018-08-21 12:54:45 +0100396
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100397- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
398 feature. MPAM is an optional Armv8.4 extension that enables various memory
399 system components and resources to define partitions; software running at
400 various ELs can assign themselves to desired partition to control their
401 performance aspects.
402
403 When this option is set to ``1``, EL3 allows lower ELs to access their own
404 MPAM registers without trapping into EL3. This option doesn't make use of
405 partitioning in EL3, however. Platform initialisation code should configure
406 and use partitions in EL3 as required. This option defaults to ``0``.
407
Soby Mathew078f1a42018-08-28 11:13:55 +0100408- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
409 support within generic code in TF-A. This option is currently only supported
410 in BL31. Default is 0.
411
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100412- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
413 Measurement Framework(PMF). Default is 0.
414
415- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
416 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
417 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
418 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
419 software.
420
421- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000422 instrumentation which injects timestamp collection points into TF-A to
423 allow runtime performance to be measured. Currently, only PSCI is
424 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
425 as well. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100426
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100427- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100428 extensions. This is an optional architectural feature for AArch64.
429 The default is 1 but is automatically disabled when the target architecture
430 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100431
Sandrine Bailleux604f0a42018-09-20 12:44:39 +0200432- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
433 Refer to the `Secure Partition Manager Design guide`_ for more details about
434 this feature. Default is 0.
435
David Cunadoce88eee2017-10-20 11:30:57 +0100436- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
437 (SVE) for the Non-secure world only. SVE is an optional architectural feature
438 for AArch64. Note that when SVE is enabled for the Non-secure world, access
439 to SIMD and floating-point functionality from the Secure world is disabled.
440 This is to avoid corruption of the Non-secure world data in the Z-registers
441 which are aliased by the SIMD and FP registers. The build option is not
442 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
443 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
444 1. The default is 1 but is automatically disabled when the target
445 architecture is AArch32.
446
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100447- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
448 checks in GCC. Allowed values are "all", "strong" and "0" (default).
449 "strong" is the recommended stack protection level if this feature is
450 desired. 0 disables the stack protection. For all values other than 0, the
451 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
452 The value is passed as the last component of the option
453 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
454
455- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
456 deprecated platform APIs, helper functions or drivers within Trusted
457 Firmware as error. It can take the value 1 (flag the use of deprecated
458 APIs as error) or 0. The default is 0.
459
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100460- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
461 targeted at EL3. When set ``0`` (default), no exceptions are expected or
462 handled at EL3, and a panic will result. This is supported only for AArch64
463 builds.
464
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000465- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000466 injection from lower ELs, and this build option enables lower ELs to use
467 Error Records accessed via System Registers to inject faults. This is
468 applicable only to AArch64 builds.
469
470 This feature is intended for testing purposes only, and is advisable to keep
471 disabled for production images.
472
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100473- ``FIP_NAME``: This is an optional build option which specifies the FIP
474 filename for the ``fip`` target. Default is ``fip.bin``.
475
476- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
477 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
478
479- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
480 tool to create certificates as per the Chain of Trust described in
481 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
482 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
483
484 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
485 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
486 the corresponding certificates, and to include those certificates in the
487 FIP and FWU\_FIP.
488
489 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
490 images will not include support for Trusted Board Boot. The FIP will still
491 include the corresponding certificates. This FIP can be used to verify the
492 Chain of Trust on the host machine through other mechanisms.
493
494 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
495 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
496 will not include the corresponding certificates, causing a boot failure.
497
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100498- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
499 inherent support for specific EL3 type interrupts. Setting this build option
500 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
501 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
502 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
503 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
504 the Secure Payload interrupts needs to be synchronously handed over to Secure
505 EL1 for handling. The default value of this option is ``0``, which means the
506 Group 0 interrupts are assumed to be handled by Secure EL1.
507
508 .. __: `platform-interrupt-controller-API.rst`
509 .. __: `interrupt-framework-design.rst`
510
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700511- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
512 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
513 ``0`` (default), these exceptions will be trapped in the current exception
514 level (or in EL1 if the current exception level is EL0).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100515
Dan Handley610e7e12018-03-01 18:44:00 +0000516- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100517 software operations are required for CPUs to enter and exit coherency.
518 However, there exists newer systems where CPUs' entry to and exit from
519 coherency is managed in hardware. Such systems require software to only
520 initiate the operations, and the rest is managed in hardware, minimizing
Dan Handley610e7e12018-03-01 18:44:00 +0000521 active software management. In such systems, this boolean option enables
522 TF-A to carry out build and run-time optimizations during boot and power
523 management operations. This option defaults to 0 and if it is enabled,
524 then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100525
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100526 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
527 translation library (xlat tables v2) must be used; version 1 of translation
528 library is not supported.
529
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100530- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
531 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
532 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
533 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
534 images.
535
Soby Mathew13b16052017-08-31 11:49:32 +0100536- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
537 used for generating the PKCS keys and subsequent signing of the certificate.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800538 It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is
Soby Mathew2fd70f62017-08-31 11:50:29 +0100539 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
540 retained only for compatibility. The default value of this flag is ``rsa``
541 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100542
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800543- ``HASH_ALG``: This build flag enables the user to select the secure hash
544 algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``.
545 The default value of this flag is ``sha256``.
546
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100547- ``LDFLAGS``: Extra user options appended to the linkers' command line in
548 addition to the one set by the build system.
549
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100550- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
551 output compiled into the build. This should be one of the following:
552
553 ::
554
555 0 (LOG_LEVEL_NONE)
Daniel Boulby86c6b072018-06-14 10:07:40 +0100556 10 (LOG_LEVEL_ERROR)
557 20 (LOG_LEVEL_NOTICE)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100558 30 (LOG_LEVEL_WARNING)
559 40 (LOG_LEVEL_INFO)
560 50 (LOG_LEVEL_VERBOSE)
561
John Tsichritzis35006c42018-10-05 12:02:29 +0100562 All log output up to and including the selected log level is compiled into
563 the build. The default value is 40 in debug builds and 20 in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100564
565- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
566 specifies the file that contains the Non-Trusted World private key in PEM
567 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
568
569- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
570 optional. It is only needed if the platform makefile specifies that it
571 is required in order to build the ``fwu_fip`` target.
572
573- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
574 contents upon world switch. It can take either 0 (don't save and restore) or
575 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
576 wants the timer registers to be saved and restored.
577
Varun Wadekar3f9002c2019-01-31 09:22:30 -0800578- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
579 for the BL image. It can be either 0 (include) or 1 (remove). The default
580 value is 0.
581
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100582- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
583 the underlying hardware is not a full PL011 UART but a minimally compliant
584 generic UART, which is a subset of the PL011. The driver will not access
585 any register that is not part of the SBSA generic UART specification.
586 Default value is 0 (a full PL011 compliant UART is present).
587
Dan Handley610e7e12018-03-01 18:44:00 +0000588- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
589 must be subdirectory of any depth under ``plat/``, and must contain a
590 platform makefile named ``platform.mk``. For example, to build TF-A for the
591 Arm Juno board, select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100592
593- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
594 instead of the normal boot flow. When defined, it must specify the entry
595 point address for the preloaded BL33 image. This option is incompatible with
596 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
597 over ``PRELOADED_BL33_BASE``.
598
599- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
600 vector address can be programmed or is fixed on the platform. It can take
601 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
602 programmable reset address, it is expected that a CPU will start executing
603 code directly at the right address, both on a cold and warm reset. In this
604 case, there is no need to identify the entrypoint on boot and the boot path
605 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
606 does not need to be implemented in this case.
607
608- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
609 possible for the PSCI power-state parameter viz original and extended
610 State-ID formats. This flag if set to 1, configures the generic PSCI layer
611 to use the extended format. The default value of this flag is 0, which
612 means by default the original power-state format is used by the PSCI
613 implementation. This flag should be specified by the platform makefile
614 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
Dan Handley610e7e12018-03-01 18:44:00 +0000615 smc function id. When this option is enabled on Arm platforms, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100616 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
617
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100618- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
619 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
620 or later CPUs.
621
622 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
623 set to ``1``.
624
625 This option is disabled by default.
626
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100627- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
628 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
629 entrypoint) or 1 (CPU reset to BL31 entrypoint).
630 The default value is 0.
631
Dan Handley610e7e12018-03-01 18:44:00 +0000632- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided
633 in TF-A. This flag configures SP\_MIN entrypoint as the CPU reset vector
634 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
635 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default value is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100636
637- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
638 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
639 file name will be used to save the key.
640
641- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
642 certificate generation tool to save the keys used to establish the Chain of
643 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
644
645- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
646 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
647 target.
648
649- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
650 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
651 this file name will be used to save the key.
652
653- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
654 optional. It is only needed if the platform makefile specifies that it
655 is required in order to build the ``fwu_fip`` target.
656
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100657- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
658 Delegated Exception Interface to BL31 image. This defaults to ``0``.
659
660 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
661 set to ``1``.
662
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100663- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
664 isolated on separate memory pages. This is a trade-off between security and
665 memory usage. See "Isolating code and read-only data on separate memory
666 pages" section in `Firmware Design`_. This flag is disabled by default and
667 affects all BL images.
668
Dan Handley610e7e12018-03-01 18:44:00 +0000669- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
670 This build option is only valid if ``ARCH=aarch64``. The value should be
671 the path to the directory containing the SPD source, relative to
672 ``services/spd/``; the directory is expected to contain a makefile called
673 ``<spd-value>.mk``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100674
675- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
676 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
677 execution in BL1 just before handing over to BL31. At this point, all
678 firmware images have been loaded in memory, and the MMU and caches are
679 turned off. Refer to the "Debugging options" section for more details.
680
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100681- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200682 secure interrupts (caught through the FIQ line). Platforms can enable
683 this directive if they need to handle such interruption. When enabled,
684 the FIQ are handled in monitor mode and non secure world is not allowed
685 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
686 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
687
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100688- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
689 Boot feature. When set to '1', BL1 and BL2 images include support to load
690 and verify the certificates and images in a FIP, and BL1 includes support
691 for the Firmware Update. The default value is '0'. Generation and inclusion
692 of certificates in the FIP and FWU\_FIP depends upon the value of the
693 ``GENERATE_COT`` option.
694
695 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
696 already exist in disk, they will be overwritten without further notice.
697
698- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
699 specifies the file that contains the Trusted World private key in PEM
700 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
701
702- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
703 synchronous, (see "Initializing a BL32 Image" section in
704 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
705 synchronous method) or 1 (BL32 is initialized using asynchronous method).
706 Default is 0.
707
708- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
709 routing model which routes non-secure interrupts asynchronously from TSP
710 to EL3 causing immediate preemption of TSP. The EL3 is responsible
711 for saving and restoring the TSP context in this routing model. The
712 default routing model (when the value is 0) is to route non-secure
713 interrupts to TSP allowing it to save its context and hand over
714 synchronously to EL3 via an SMC.
715
Jeenu Viswambharan2f40f322018-01-11 14:30:22 +0000716 Note: when ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
717 must also be set to ``1``.
718
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100719- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
720 memory region in the BL memory map or not (see "Use of Coherent memory in
Dan Handley610e7e12018-03-01 18:44:00 +0000721 TF-A" section in `Firmware Design`_). It can take the value 1
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100722 (Coherent memory region is included) or 0 (Coherent memory region is
723 excluded). Default is 1.
724
725- ``V``: Verbose build. If assigned anything other than 0, the build commands
726 are printed. Default is 0.
727
Dan Handley610e7e12018-03-01 18:44:00 +0000728- ``VERSION_STRING``: String used in the log output for each TF-A image.
729 Defaults to a string formed by concatenating the version number, build type
730 and build string.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100731
732- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
733 the CPU after warm boot. This is applicable for platforms which do not
734 require interconnect programming to enable cache coherency (eg: single
735 cluster platforms). If this option is enabled, then warm boot path
736 enables D-caches immediately after enabling MMU. This option defaults to 0.
737
Dan Handley610e7e12018-03-01 18:44:00 +0000738Arm development platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100739^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
740
741- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
742 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
743 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
744 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
745 flag.
746
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100747- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
748 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
749 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
750 match the frame used by the Non-Secure image (normally the Linux kernel).
751 Default is true (access to the frame is allowed).
752
753- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
Dan Handley610e7e12018-03-01 18:44:00 +0000754 By default, Arm platforms use a watchdog to trigger a system reset in case
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100755 an error is encountered during the boot process (for example, when an image
756 could not be loaded or authenticated). The watchdog is enabled in the early
757 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
758 Trusted Watchdog may be disabled at build time for testing or development
759 purposes.
760
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100761- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
762 have specific values at boot. This boolean option allows the Trusted Firmware
763 to have a Linux kernel image as BL33 by preparing the registers to these
Manish Pandey37c4ec22018-11-02 13:28:25 +0000764 values before jumping to BL33. This option defaults to 0 (disabled). For
765 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
766 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
767 to the location of a device tree blob (DTB) already loaded in memory. The
768 Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
769 option.
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100770
Sandrine Bailleux281f8f72019-01-31 13:12:41 +0100771- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
772 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
773 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
774 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
775 this flag is 0. Note that this option is not used on FVP platforms.
776
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100777- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
778 for the construction of composite state-ID in the power-state parameter.
779 The existing PSCI clients currently do not support this encoding of
780 State-ID yet. Hence this flag is used to configure whether to use the
781 recommended State-ID encoding or not. The default value of this flag is 0,
782 in which case the platform is configured to expect NULL in the State-ID
783 field of power-state parameter.
784
785- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
786 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
Dan Handley610e7e12018-03-01 18:44:00 +0000787 for Arm platforms. Depending on the selected option, the proper private key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100788 must be specified using the ``ROT_KEY`` option when building the Trusted
789 Firmware. This private key will be used by the certificate generation tool
790 to sign the BL2 and Trusted Key certificates. Available options for
791 ``ARM_ROTPK_LOCATION`` are:
792
793 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
794 registers. The private key corresponding to this ROTPK hash is not
795 currently available.
796 - ``devel_rsa`` : return a development public key hash embedded in the BL1
797 and BL2 binaries. This hash has been obtained from the RSA public key
798 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
799 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
800 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800801 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
802 and BL2 binaries. This hash has been obtained from the ECDSA public key
803 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
804 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
805 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100806
807- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
808
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800809 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100810 - ``tdram`` : Trusted DRAM (if available)
John Tsichritzisee10e792018-06-06 09:38:10 +0100811 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
812 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100813
Dan Handley610e7e12018-03-01 18:44:00 +0000814- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
815 of the translation tables library instead of version 2. It is set to 0 by
816 default, which selects version 2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100817
Dan Handley610e7e12018-03-01 18:44:00 +0000818- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
819 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
820 platforms. If this option is specified, then the path to the CryptoCell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100821 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
822
Dan Handley610e7e12018-03-01 18:44:00 +0000823For a better understanding of these options, the Arm development platform memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100824map is explained in the `Firmware Design`_.
825
Dan Handley610e7e12018-03-01 18:44:00 +0000826Arm CSS platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100827^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
828
829- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
830 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
831 compatible change to the MTL protocol, used for AP/SCP communication.
Dan Handley610e7e12018-03-01 18:44:00 +0000832 TF-A no longer supports earlier SCP versions. If this option is set to 1
833 then TF-A will detect if an earlier version is in use. Default is 1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100834
835- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
836 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
837 during boot. Default is 1.
838
Soby Mathew1ced6b82017-06-12 12:37:10 +0100839- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
840 instead of SCPI/BOM driver for communicating with the SCP during power
841 management operations and for SCP RAM Firmware transfer. If this option
842 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100843
Dan Handley610e7e12018-03-01 18:44:00 +0000844Arm FVP platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100845^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
846
847- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
Dan Handley610e7e12018-03-01 18:44:00 +0000848 build the topology tree within TF-A. By default TF-A is configured for dual
849 cluster topology and this option can be used to override the default value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100850
851- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
852 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
853 explained in the options below:
854
855 - ``FVP_CCI`` : The CCI driver is selected. This is the default
856 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
857 - ``FVP_CCN`` : The CCN driver is selected. This is the default
858 if ``FVP_CLUSTER_COUNT`` > 2.
859
Jeenu Viswambharan75421132018-01-31 14:52:08 +0000860- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
861 a single cluster. This option defaults to 4.
862
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000863- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
864 in the system. This option defaults to 1. Note that the build option
865 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
866
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100867- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
868
869 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
870 - ``FVP_GICV2`` : The GICv2 only driver is selected
871 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100872
873- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
874 for functions that wait for an arbitrary time length (udelay and mdelay).
875 The default value is 0.
876
Soby Mathewb1bf0442018-02-16 14:52:52 +0000877- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
878 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
879 details on HW_CONFIG. By default, this is initialized to a sensible DTS
880 file in ``fdts/`` folder depending on other build options. But some cases,
881 like shifted affinity format for MPIDR, cannot be detected at build time
882 and this option is needed to specify the appropriate DTS file.
883
884- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
885 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
886 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
887 HW_CONFIG blob instead of the DTS file. This option is useful to override
888 the default HW_CONFIG selected by the build system.
889
Summer Qin13b95c22018-03-02 15:51:14 +0800890ARM JUNO platform specific build options
891^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
892
893- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
894 Media Protection (TZ-MP1). Default value of this flag is 0.
895
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100896Debugging options
897~~~~~~~~~~~~~~~~~
898
899To compile a debug version and make the build more verbose use
900
901::
902
903 make PLAT=<platform> DEBUG=1 V=1 all
904
905AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
906example DS-5) might not support this and may need an older version of DWARF
907symbols to be emitted by GCC. This can be achieved by using the
908``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
909version to 2 is recommended for DS-5 versions older than 5.16.
910
911When debugging logic problems it might also be useful to disable all compiler
912optimizations by using ``-O0``.
913
914NOTE: Using ``-O0`` could cause output images to be larger and base addresses
Dan Handley610e7e12018-03-01 18:44:00 +0000915might need to be recalculated (see the **Memory layout on Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100916platforms** section in the `Firmware Design`_).
917
918Extra debug options can be passed to the build system by setting ``CFLAGS`` or
919``LDFLAGS``:
920
921.. code:: makefile
922
923 CFLAGS='-O0 -gdwarf-2' \
924 make PLAT=<platform> DEBUG=1 V=1 all
925
926Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
927ignored as the linker is called directly.
928
929It is also possible to introduce an infinite loop to help in debugging the
Dan Handley610e7e12018-03-01 18:44:00 +0000930post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
931``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100932section. In this case, the developer may take control of the target using a
933debugger when indicated by the console output. When using DS-5, the following
934commands can be used:
935
936::
937
938 # Stop target execution
939 interrupt
940
941 #
942 # Prepare your debugging environment, e.g. set breakpoints
943 #
944
945 # Jump over the debug loop
946 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
947
948 # Resume execution
949 continue
950
951Building the Test Secure Payload
952~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
953
954The TSP is coupled with a companion runtime service in the BL31 firmware,
955called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
956must be recompiled as well. For more information on SPs and SPDs, see the
957`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
958
Dan Handley610e7e12018-03-01 18:44:00 +0000959First clean the TF-A build directory to get rid of any previous BL31 binary.
960Then to build the TSP image use:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100961
962::
963
964 make PLAT=<platform> SPD=tspd all
965
966An additional boot loader binary file is created in the ``build`` directory:
967
968::
969
970 build/<platform>/<build-type>/bl32.bin
971
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100972
973Building and using the FIP tool
974~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
975
Dan Handley610e7e12018-03-01 18:44:00 +0000976Firmware Image Package (FIP) is a packaging format used by TF-A to package
977firmware images in a single binary. The number and type of images that should
978be packed in a FIP is platform specific and may include TF-A images and other
979firmware images required by the platform. For example, most platforms require
980a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
981U-Boot).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100982
Dan Handley610e7e12018-03-01 18:44:00 +0000983The TF-A build system provides the make target ``fip`` to create a FIP file
984for the specified platform using the FIP creation tool included in the TF-A
985project. Examples below show how to build a FIP file for FVP, packaging TF-A
986and BL33 images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100987
988For AArch64:
989
990::
991
992 make PLAT=fvp BL33=<path/to/bl33.bin> fip
993
994For AArch32:
995
996::
997
998 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
999
1000Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
1001UEFI, on FVP is not available upstream. Hence custom solutions are required to
1002allow Linux boot on FVP. These instructions assume such a custom boot loader
1003(BL33) is available.
1004
1005The resulting FIP may be found in:
1006
1007::
1008
1009 build/fvp/<build-type>/fip.bin
1010
1011For advanced operations on FIP files, it is also possible to independently build
1012the tool and create or modify FIPs using this tool. To do this, follow these
1013steps:
1014
1015It is recommended to remove old artifacts before building the tool:
1016
1017::
1018
1019 make -C tools/fiptool clean
1020
1021Build the tool:
1022
1023::
1024
1025 make [DEBUG=1] [V=1] fiptool
1026
1027The tool binary can be located in:
1028
1029::
1030
1031 ./tools/fiptool/fiptool
1032
1033Invoking the tool with ``--help`` will print a help message with all available
1034options.
1035
1036Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1037
1038::
1039
1040 ./tools/fiptool/fiptool create \
1041 --tb-fw build/<platform>/<build-type>/bl2.bin \
1042 --soc-fw build/<platform>/<build-type>/bl31.bin \
1043 fip.bin
1044
1045Example 2: view the contents of an existing Firmware package:
1046
1047::
1048
1049 ./tools/fiptool/fiptool info <path-to>/fip.bin
1050
1051Example 3: update the entries of an existing Firmware package:
1052
1053::
1054
1055 # Change the BL2 from Debug to Release version
1056 ./tools/fiptool/fiptool update \
1057 --tb-fw build/<platform>/release/bl2.bin \
1058 build/<platform>/debug/fip.bin
1059
1060Example 4: unpack all entries from an existing Firmware package:
1061
1062::
1063
1064 # Images will be unpacked to the working directory
1065 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1066
1067Example 5: remove an entry from an existing Firmware package:
1068
1069::
1070
1071 ./tools/fiptool/fiptool remove \
1072 --tb-fw build/<platform>/debug/fip.bin
1073
1074Note that if the destination FIP file exists, the create, update and
1075remove operations will automatically overwrite it.
1076
1077The unpack operation will fail if the images already exist at the
1078destination. In that case, use -f or --force to continue.
1079
1080More information about FIP can be found in the `Firmware Design`_ document.
1081
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001082Building FIP images with support for Trusted Board Boot
1083~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1084
1085Trusted Board Boot primarily consists of the following two features:
1086
1087- Image Authentication, described in `Trusted Board Boot`_, and
1088- Firmware Update, described in `Firmware Update`_
1089
1090The following steps should be followed to build FIP and (optionally) FWU\_FIP
1091images with support for these features:
1092
1093#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1094 modules by checking out a recent version of the `mbed TLS Repository`_. It
Dan Handley610e7e12018-03-01 18:44:00 +00001095 is important to use a version that is compatible with TF-A and fixes any
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001096 known security vulnerabilities. See `mbed TLS Security Center`_ for more
Dan Handley610e7e12018-03-01 18:44:00 +00001097 information. The latest version of TF-A is tested with tag
David Cunado05845bf2017-12-19 16:33:25 +00001098 ``mbedtls-2.12.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001099
1100 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1101 source files the modules depend upon.
1102 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1103 options required to build the mbed TLS sources.
1104
1105 Note that the mbed TLS library is licensed under the Apache version 2.0
Dan Handley610e7e12018-03-01 18:44:00 +00001106 license. Using mbed TLS source code will affect the licensing of TF-A
1107 binaries that are built using this library.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001108
1109#. To build the FIP image, ensure the following command line variables are set
Dan Handley610e7e12018-03-01 18:44:00 +00001110 while invoking ``make`` to build TF-A:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001111
1112 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1113 - ``TRUSTED_BOARD_BOOT=1``
1114 - ``GENERATE_COT=1``
1115
Dan Handley610e7e12018-03-01 18:44:00 +00001116 In the case of Arm platforms, the location of the ROTPK hash must also be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001117 specified at build time. Two locations are currently supported (see
1118 ``ARM_ROTPK_LOCATION`` build option):
1119
1120 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1121 root-key storage registers present in the platform. On Juno, this
1122 registers are read-only. On FVP Base and Cortex models, the registers
1123 are read-only, but the value can be specified using the command line
1124 option ``bp.trusted_key_storage.public_key`` when launching the model.
1125 On both Juno and FVP models, the default value corresponds to an
1126 ECDSA-SECP256R1 public key hash, whose private part is not currently
1127 available.
1128
1129 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001130 in the Arm platform port. The private/public RSA key pair may be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001131 found in ``plat/arm/board/common/rotpk``.
1132
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001133 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001134 in the Arm platform port. The private/public ECDSA key pair may be
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001135 found in ``plat/arm/board/common/rotpk``.
1136
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001137 Example of command line using RSA development keys:
1138
1139 ::
1140
1141 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1142 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1143 ARM_ROTPK_LOCATION=devel_rsa \
1144 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1145 BL33=<path-to>/<bl33_image> \
1146 all fip
1147
1148 The result of this build will be the bl1.bin and the fip.bin binaries. This
1149 FIP will include the certificates corresponding to the Chain of Trust
1150 described in the TBBR-client document. These certificates can also be found
1151 in the output build directory.
1152
1153#. The optional FWU\_FIP contains any additional images to be loaded from
1154 Non-Volatile storage during the `Firmware Update`_ process. To build the
1155 FWU\_FIP, any FWU images required by the platform must be specified on the
Dan Handley610e7e12018-03-01 18:44:00 +00001156 command line. On Arm development platforms like Juno, these are:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001157
1158 - NS\_BL2U. The AP non-secure Firmware Updater image.
1159 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1160
1161 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1162 targets using RSA development:
1163
1164 ::
1165
1166 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1167 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1168 ARM_ROTPK_LOCATION=devel_rsa \
1169 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1170 BL33=<path-to>/<bl33_image> \
1171 SCP_BL2=<path-to>/<scp_bl2_image> \
1172 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1173 NS_BL2U=<path-to>/<ns_bl2u_image> \
1174 all fip fwu_fip
1175
1176 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1177 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1178 to the command line above.
1179
1180 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1181 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1182
1183 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1184 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1185 Chain of Trust described in the TBBR-client document. These certificates
1186 can also be found in the output build directory.
1187
1188Building the Certificate Generation Tool
1189~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1190
Dan Handley610e7e12018-03-01 18:44:00 +00001191The ``cert_create`` tool is built as part of the TF-A build process when the
1192``fip`` make target is specified and TBB is enabled (as described in the
1193previous section), but it can also be built separately with the following
1194command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001195
1196::
1197
1198 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1199
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001200For platforms that require their own IDs in certificate files, the generic
1201'cert\_create' tool can be built with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001202
1203::
1204
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001205 make USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001206
1207``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1208verbose. The following command should be used to obtain help about the tool:
1209
1210::
1211
1212 ./tools/cert_create/cert_create -h
1213
1214Building a FIP for Juno and FVP
1215-------------------------------
1216
1217This section provides Juno and FVP specific instructions to build Trusted
1218Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001219a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001220
David Cunadob2de0992017-06-29 12:01:33 +01001221Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1222onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001223
Joel Huttonfe027712018-03-19 11:59:57 +00001224Note: Follow the full instructions for one platform before switching to a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001225different one. Mixing instructions for different platforms may result in
1226corrupted binaries.
1227
Joel Huttonfe027712018-03-19 11:59:57 +00001228Note: The uboot image downloaded by the Linaro workspace script does not always
1229match the uboot image packaged as BL33 in the corresponding fip file. It is
1230recommended to use the version that is packaged in the fip file using the
1231instructions below.
1232
Soby Mathewecd94ad2018-05-09 13:59:29 +01001233Note: For the FVP, the kernel FDT is packaged in FIP during build and loaded
1234by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1235section for more info on selecting the right FDT to use.
1236
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001237#. Clean the working directory
1238
1239 ::
1240
1241 make realclean
1242
1243#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1244
1245 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1246 package included in the Linaro release:
1247
1248 ::
1249
1250 # Build the fiptool
1251 make [DEBUG=1] [V=1] fiptool
1252
1253 # Unpack firmware images from Linaro FIP
1254 ./tools/fiptool/fiptool unpack \
1255 <path/to/linaro/release>/fip.bin
1256
1257 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001258 current working directory. The SCP\_BL2 image corresponds to
1259 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001260
Joel Huttonfe027712018-03-19 11:59:57 +00001261 Note: The fiptool will complain if the images to be unpacked already
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001262 exist in the current directory. If that is the case, either delete those
1263 files or use the ``--force`` option to overwrite.
1264
Joel Huttonfe027712018-03-19 11:59:57 +00001265 Note: For AArch32, the instructions below assume that nt-fw.bin is a custom
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001266 Normal world boot loader that supports AArch32.
1267
Dan Handley610e7e12018-03-01 18:44:00 +00001268#. Build TF-A images and create a new FIP for FVP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001269
1270 ::
1271
1272 # AArch64
1273 make PLAT=fvp BL33=nt-fw.bin all fip
1274
1275 # AArch32
1276 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1277
Dan Handley610e7e12018-03-01 18:44:00 +00001278#. Build TF-A images and create a new FIP for Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001279
1280 For AArch64:
1281
1282 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1283 as a build parameter.
1284
1285 ::
1286
1287 make PLAT=juno all fip \
1288 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1289 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1290
1291 For AArch32:
1292
1293 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1294 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1295 separately for AArch32.
1296
1297 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1298 to the AArch32 Linaro cross compiler.
1299
1300 ::
1301
1302 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1303
1304 - Build BL32 in AArch32.
1305
1306 ::
1307
1308 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1309 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1310
1311 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1312 must point to the AArch64 Linaro cross compiler.
1313
1314 ::
1315
1316 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1317
1318 - The following parameters should be used to build BL1 and BL2 in AArch64
1319 and point to the BL32 file.
1320
1321 ::
1322
Soby Mathew97b1bff2018-09-27 16:46:41 +01001323 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001324 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
Soby Mathewbf169232017-11-14 14:10:10 +00001325 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001326 BL32=<path-to-bl32>/bl32.bin all fip
1327
1328The resulting BL1 and FIP images may be found in:
1329
1330::
1331
1332 # Juno
1333 ./build/juno/release/bl1.bin
1334 ./build/juno/release/fip.bin
1335
1336 # FVP
1337 ./build/fvp/release/bl1.bin
1338 ./build/fvp/release/fip.bin
1339
Roberto Vargas096f3a02017-10-17 10:19:00 +01001340
1341Booting Firmware Update images
1342-------------------------------------
1343
1344When Firmware Update (FWU) is enabled there are at least 2 new images
1345that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1346FWU FIP.
1347
1348Juno
1349~~~~
1350
1351The new images must be programmed in flash memory by adding
1352an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1353on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1354Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1355programming" for more information. User should ensure these do not
1356overlap with any other entries in the file.
1357
1358::
1359
1360 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1361 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1362 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1363 NOR10LOAD: 00000000 ;Image Load Address
1364 NOR10ENTRY: 00000000 ;Image Entry Point
1365
1366 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1367 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1368 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1369 NOR11LOAD: 00000000 ;Image Load Address
1370
1371The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1372In the same way, the address ns_bl2u_base_address is the value of
1373NS_BL2U_BASE - 0x8000000.
1374
1375FVP
1376~~~
1377
1378The additional fip images must be loaded with:
1379
1380::
1381
1382 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1383 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1384
1385The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1386In the same way, the address ns_bl2u_base_address is the value of
1387NS_BL2U_BASE.
1388
1389
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001390EL3 payloads alternative boot flow
1391----------------------------------
1392
1393On a pre-production system, the ability to execute arbitrary, bare-metal code at
1394the highest exception level is required. It allows full, direct access to the
1395hardware, for example to run silicon soak tests.
1396
1397Although it is possible to implement some baremetal secure firmware from
1398scratch, this is a complex task on some platforms, depending on the level of
1399configuration required to put the system in the expected state.
1400
1401Rather than booting a baremetal application, a possible compromise is to boot
Dan Handley610e7e12018-03-01 18:44:00 +00001402``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1403boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1404other BL images and passing control to BL31. It reduces the complexity of
1405developing EL3 baremetal code by:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001406
1407- putting the system into a known architectural state;
1408- taking care of platform secure world initialization;
1409- loading the SCP\_BL2 image if required by the platform.
1410
Dan Handley610e7e12018-03-01 18:44:00 +00001411When booting an EL3 payload on Arm standard platforms, the configuration of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001412TrustZone controller is simplified such that only region 0 is enabled and is
1413configured to permit secure access only. This gives full access to the whole
1414DRAM to the EL3 payload.
1415
1416The system is left in the same state as when entering BL31 in the default boot
1417flow. In particular:
1418
1419- Running in EL3;
1420- Current state is AArch64;
1421- Little-endian data access;
1422- All exceptions disabled;
1423- MMU disabled;
1424- Caches disabled.
1425
1426Booting an EL3 payload
1427~~~~~~~~~~~~~~~~~~~~~~
1428
1429The EL3 payload image is a standalone image and is not part of the FIP. It is
Dan Handley610e7e12018-03-01 18:44:00 +00001430not loaded by TF-A. Therefore, there are 2 possible scenarios:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001431
1432- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1433 place. In this case, booting it is just a matter of specifying the right
Dan Handley610e7e12018-03-01 18:44:00 +00001434 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001435
1436- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1437 run-time.
1438
1439To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1440used. The infinite loop that it introduces in BL1 stops execution at the right
1441moment for a debugger to take control of the target and load the payload (for
1442example, over JTAG).
1443
1444It is expected that this loading method will work in most cases, as a debugger
1445connection is usually available in a pre-production system. The user is free to
1446use any other platform-specific mechanism to load the EL3 payload, though.
1447
1448Booting an EL3 payload on FVP
1449^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1450
1451The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1452the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1453is undefined on the FVP platform and the FVP platform code doesn't clear it.
1454Therefore, one must modify the way the model is normally invoked in order to
1455clear the mailbox at start-up.
1456
1457One way to do that is to create an 8-byte file containing all zero bytes using
1458the following command:
1459
1460::
1461
1462 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1463
1464and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1465using the following model parameters:
1466
1467::
1468
1469 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1470 --data=mailbox.dat@0x04000000 [Foundation FVP]
1471
1472To provide the model with the EL3 payload image, the following methods may be
1473used:
1474
1475#. If the EL3 payload is able to execute in place, it may be programmed into
1476 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1477 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1478 used for the FIP):
1479
1480 ::
1481
1482 -C bp.flashloader1.fname="/path/to/el3-payload"
1483
1484 On Foundation FVP, there is no flash loader component and the EL3 payload
1485 may be programmed anywhere in flash using method 3 below.
1486
1487#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1488 command may be used to load the EL3 payload ELF image over JTAG:
1489
1490 ::
1491
1492 load /path/to/el3-payload.elf
1493
1494#. The EL3 payload may be pre-loaded in volatile memory using the following
1495 model parameters:
1496
1497 ::
1498
1499 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1500 --data="/path/to/el3-payload"@address [Foundation FVP]
1501
1502 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
Dan Handley610e7e12018-03-01 18:44:00 +00001503 used when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001504
1505Booting an EL3 payload on Juno
1506^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1507
1508If the EL3 payload is able to execute in place, it may be programmed in flash
1509memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1510on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1511Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1512programming" for more information.
1513
1514Alternatively, the same DS-5 command mentioned in the FVP section above can
1515be used to load the EL3 payload's ELF file over JTAG on Juno.
1516
1517Preloaded BL33 alternative boot flow
1518------------------------------------
1519
1520Some platforms have the ability to preload BL33 into memory instead of relying
Dan Handley610e7e12018-03-01 18:44:00 +00001521on TF-A to load it. This may simplify packaging of the normal world code and
1522improve performance in a development environment. When secure world cold boot
1523is complete, TF-A simply jumps to a BL33 base address provided at build time.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001524
1525For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
Dan Handley610e7e12018-03-01 18:44:00 +00001526used when compiling TF-A. For example, the following command will create a FIP
1527without a BL33 and prepare to jump to a BL33 image loaded at address
15280x80000000:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001529
1530::
1531
1532 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1533
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001534Boot of a preloaded kernel image on Base FVP
1535~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001536
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001537The following example uses a simplified boot flow by directly jumping from the
1538TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1539useful if both the kernel and the device tree blob (DTB) are already present in
1540memory (like in FVP).
1541
1542For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1543address ``0x82000000``, the firmware can be built like this:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001544
1545::
1546
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001547 CROSS_COMPILE=aarch64-linux-gnu- \
1548 make PLAT=fvp DEBUG=1 \
1549 RESET_TO_BL31=1 \
1550 ARM_LINUX_KERNEL_AS_BL33=1 \
1551 PRELOADED_BL33_BASE=0x80080000 \
1552 ARM_PRELOADED_DTB_BASE=0x82000000 \
1553 all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001554
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001555Now, it is needed to modify the DTB so that the kernel knows the address of the
1556ramdisk. The following script generates a patched DTB from the provided one,
1557assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1558script assumes that the user is using a ramdisk image prepared for U-Boot, like
1559the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1560offset in ``INITRD_START`` has to be removed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001561
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001562.. code:: bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001563
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001564 #!/bin/bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001565
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001566 # Path to the input DTB
1567 KERNEL_DTB=<path-to>/<fdt>
1568 # Path to the output DTB
1569 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1570 # Base address of the ramdisk
1571 INITRD_BASE=0x84000000
1572 # Path to the ramdisk
1573 INITRD=<path-to>/<ramdisk.img>
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001574
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001575 # Skip uboot header (64 bytes)
1576 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1577 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1578 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1579
1580 CHOSEN_NODE=$(echo \
1581 "/ { \
1582 chosen { \
1583 linux,initrd-start = <${INITRD_START}>; \
1584 linux,initrd-end = <${INITRD_END}>; \
1585 }; \
1586 };")
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001587
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001588 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1589 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001590
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001591And the FVP binary can be run with the following command:
1592
1593::
1594
1595 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1596 -C pctl.startup=0.0.0.0 \
1597 -C bp.secure_memory=1 \
1598 -C cluster0.NUM_CORES=4 \
1599 -C cluster1.NUM_CORES=4 \
1600 -C cache_state_modelled=1 \
1601 -C cluster0.cpu0.RVBAR=0x04020000 \
1602 -C cluster0.cpu1.RVBAR=0x04020000 \
1603 -C cluster0.cpu2.RVBAR=0x04020000 \
1604 -C cluster0.cpu3.RVBAR=0x04020000 \
1605 -C cluster1.cpu0.RVBAR=0x04020000 \
1606 -C cluster1.cpu1.RVBAR=0x04020000 \
1607 -C cluster1.cpu2.RVBAR=0x04020000 \
1608 -C cluster1.cpu3.RVBAR=0x04020000 \
1609 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1610 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1611 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1612 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1613
1614Boot of a preloaded kernel image on Juno
1615~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001616
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001617The Trusted Firmware must be compiled in a similar way as for FVP explained
1618above. The process to load binaries to memory is the one explained in
1619`Booting an EL3 payload on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001620
1621Running the software on FVP
1622---------------------------
1623
David Cunado7c032642018-03-12 18:47:05 +00001624The latest version of the AArch64 build of TF-A has been tested on the following
1625Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1626(64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001627
David Cunado05845bf2017-12-19 16:33:25 +00001628NOTE: Unless otherwise stated, the model version is Version 11.4 Build 37.
David Cunado124415e2017-06-27 17:31:12 +01001629
David Cunado05845bf2017-12-19 16:33:25 +00001630- ``FVP_Base_Aresx4``
1631- ``FVP_Base_AEMv8A-AEMv8A``
1632- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
1633- ``FVP_Base_AEMv8A-AEMv8A``
1634- ``FVP_Base_RevC-2xAEMv8A``
1635- ``FVP_Base_Cortex-A32x4``
David Cunado124415e2017-06-27 17:31:12 +01001636- ``FVP_Base_Cortex-A35x4``
1637- ``FVP_Base_Cortex-A53x4``
David Cunado05845bf2017-12-19 16:33:25 +00001638- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1639- ``FVP_Base_Cortex-A55x4``
David Cunado124415e2017-06-27 17:31:12 +01001640- ``FVP_Base_Cortex-A57x4-A53x4``
1641- ``FVP_Base_Cortex-A57x4``
1642- ``FVP_Base_Cortex-A72x4-A53x4``
1643- ``FVP_Base_Cortex-A72x4``
1644- ``FVP_Base_Cortex-A73x4-A53x4``
1645- ``FVP_Base_Cortex-A73x4``
David Cunado05845bf2017-12-19 16:33:25 +00001646- ``FVP_Base_Cortex-A75x4``
1647- ``FVP_Base_Cortex-A76x4``
1648- ``FVP_CSS_SGI-575`` (Version 11.3 build 40)
1649- ``Foundation_Platform``
David Cunado7c032642018-03-12 18:47:05 +00001650
1651The latest version of the AArch32 build of TF-A has been tested on the following
1652Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1653(64-bit host machine only).
1654
1655- ``FVP_Base_AEMv8A-AEMv8A``
David Cunado124415e2017-06-27 17:31:12 +01001656- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001657
David Cunado7c032642018-03-12 18:47:05 +00001658NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1659is not compatible with legacy GIC configurations. Therefore this FVP does not
1660support these legacy GIC configurations.
1661
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001662NOTE: The build numbers quoted above are those reported by launching the FVP
1663with the ``--version`` parameter.
1664
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001665NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1666file systems that can be downloaded separately. To run an FVP with a virtio
1667file system image an additional FVP configuration option
1668``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1669used.
1670
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001671NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1672The commands below would report an ``unhandled argument`` error in this case.
1673
1674NOTE: FVPs can be launched with ``--cadi-server`` option such that a
Dan Handley610e7e12018-03-01 18:44:00 +00001675CADI-compliant debugger (for example, Arm DS-5) can connect to and control its
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001676execution.
1677
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001678NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001679the internal synchronisation timings changed compared to older versions of the
1680models. The models can be launched with ``-Q 100`` option if they are required
1681to match the run time characteristics of the older versions.
1682
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001683The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
Dan Handley610e7e12018-03-01 18:44:00 +00001684downloaded for free from `Arm's website`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001685
David Cunado124415e2017-06-27 17:31:12 +01001686The Cortex-A models listed above are also available to download from
Dan Handley610e7e12018-03-01 18:44:00 +00001687`Arm's website`_.
David Cunado124415e2017-06-27 17:31:12 +01001688
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001689Please refer to the FVP documentation for a detailed description of the model
Dan Handley610e7e12018-03-01 18:44:00 +00001690parameter options. A brief description of the important ones that affect TF-A
1691and normal world software behavior is provided below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001692
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001693Obtaining the Flattened Device Trees
1694~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1695
1696Depending on the FVP configuration and Linux configuration used, different
Soby Mathewecd94ad2018-05-09 13:59:29 +01001697FDT files are required. FDT source files for the Foundation and Base FVPs can
1698be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1699a subset of the Base FVP components. For example, the Foundation FVP lacks
1700CLCD and MMC support, and has only one CPU cluster.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001701
1702Note: It is not recommended to use the FDTs built along the kernel because not
1703all FDTs are available from there.
1704
Soby Mathewecd94ad2018-05-09 13:59:29 +01001705The dynamic configuration capability is enabled in the firmware for FVPs.
1706This means that the firmware can authenticate and load the FDT if present in
1707FIP. A default FDT is packaged into FIP during the build based on
1708the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1709or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1710`Arm FVP platform specific build options`_ section for detail on the options).
1711
1712- ``fvp-base-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001713
David Cunado7c032642018-03-12 18:47:05 +00001714 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1715 affinities and with Base memory map configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001716
Soby Mathewecd94ad2018-05-09 13:59:29 +01001717- ``fvp-base-gicv2-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001718
David Cunado7c032642018-03-12 18:47:05 +00001719 For use with models such as the Cortex-A32 Base FVPs without shifted
1720 affinities and running Linux in AArch32 state with Base memory map
1721 configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001722
Soby Mathewecd94ad2018-05-09 13:59:29 +01001723- ``fvp-base-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001724
David Cunado7c032642018-03-12 18:47:05 +00001725 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1726 affinities and with Base memory map configuration and Linux GICv3 support.
1727
Soby Mathewecd94ad2018-05-09 13:59:29 +01001728- ``fvp-base-gicv3-psci-1t.dts``
David Cunado7c032642018-03-12 18:47:05 +00001729
1730 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1731 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1732
Soby Mathewecd94ad2018-05-09 13:59:29 +01001733- ``fvp-base-gicv3-psci-dynamiq.dts``
David Cunado7c032642018-03-12 18:47:05 +00001734
1735 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1736 single cluster, single threaded CPUs, Base memory map configuration and Linux
1737 GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001738
Soby Mathewecd94ad2018-05-09 13:59:29 +01001739- ``fvp-base-gicv3-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001740
David Cunado7c032642018-03-12 18:47:05 +00001741 For use with models such as the Cortex-A32 Base FVPs without shifted
1742 affinities and running Linux in AArch32 state with Base memory map
1743 configuration and Linux GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001744
Soby Mathewecd94ad2018-05-09 13:59:29 +01001745- ``fvp-foundation-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001746
1747 For use with Foundation FVP with Base memory map configuration.
1748
Soby Mathewecd94ad2018-05-09 13:59:29 +01001749- ``fvp-foundation-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001750
1751 (Default) For use with Foundation FVP with Base memory map configuration
1752 and Linux GICv3 support.
1753
1754Running on the Foundation FVP with reset to BL1 entrypoint
1755~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1756
1757The following ``Foundation_Platform`` parameters should be used to boot Linux with
Dan Handley610e7e12018-03-01 18:44:00 +000017584 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001759
1760::
1761
1762 <path-to>/Foundation_Platform \
1763 --cores=4 \
Antonio Nino Diazb44eda52018-02-23 11:01:31 +00001764 --arm-v8.0 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001765 --secure-memory \
1766 --visualization \
1767 --gicv3 \
1768 --data="<path-to>/<bl1-binary>"@0x0 \
1769 --data="<path-to>/<FIP-binary>"@0x08000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001770 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001771 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001772
1773Notes:
1774
1775- BL1 is loaded at the start of the Trusted ROM.
1776- The Firmware Image Package is loaded at the start of NOR FLASH0.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001777- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1778 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001779- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1780 and enable the GICv3 device in the model. Note that without this option,
1781 the Foundation FVP defaults to legacy (Versatile Express) memory map which
Dan Handley610e7e12018-03-01 18:44:00 +00001782 is not supported by TF-A.
1783- In order for TF-A to run correctly on the Foundation FVP, the architecture
1784 versions must match. The Foundation FVP defaults to the highest v8.x
1785 version it supports but the default build for TF-A is for v8.0. To avoid
1786 issues either start the Foundation FVP to use v8.0 architecture using the
1787 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1788 ``ARM_ARCH_MINOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001789
1790Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1791~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1792
David Cunado7c032642018-03-12 18:47:05 +00001793The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001794with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001795
1796::
1797
David Cunado7c032642018-03-12 18:47:05 +00001798 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001799 -C pctl.startup=0.0.0.0 \
1800 -C bp.secure_memory=1 \
1801 -C bp.tzc_400.diagnostics=1 \
1802 -C cluster0.NUM_CORES=4 \
1803 -C cluster1.NUM_CORES=4 \
1804 -C cache_state_modelled=1 \
1805 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1806 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001807 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001808 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001809
1810Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1811~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1812
1813The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001814with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001815
1816::
1817
1818 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1819 -C pctl.startup=0.0.0.0 \
1820 -C bp.secure_memory=1 \
1821 -C bp.tzc_400.diagnostics=1 \
1822 -C cluster0.NUM_CORES=4 \
1823 -C cluster1.NUM_CORES=4 \
1824 -C cache_state_modelled=1 \
1825 -C cluster0.cpu0.CONFIG64=0 \
1826 -C cluster0.cpu1.CONFIG64=0 \
1827 -C cluster0.cpu2.CONFIG64=0 \
1828 -C cluster0.cpu3.CONFIG64=0 \
1829 -C cluster1.cpu0.CONFIG64=0 \
1830 -C cluster1.cpu1.CONFIG64=0 \
1831 -C cluster1.cpu2.CONFIG64=0 \
1832 -C cluster1.cpu3.CONFIG64=0 \
1833 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1834 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001835 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001836 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001837
1838Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1839~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1840
1841The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001842boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001843
1844::
1845
1846 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1847 -C pctl.startup=0.0.0.0 \
1848 -C bp.secure_memory=1 \
1849 -C bp.tzc_400.diagnostics=1 \
1850 -C cache_state_modelled=1 \
1851 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1852 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001853 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001854 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001855
1856Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1857~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1858
1859The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001860boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001861
1862::
1863
1864 <path-to>/FVP_Base_Cortex-A32x4 \
1865 -C pctl.startup=0.0.0.0 \
1866 -C bp.secure_memory=1 \
1867 -C bp.tzc_400.diagnostics=1 \
1868 -C cache_state_modelled=1 \
1869 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1870 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001871 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001872 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001873
1874Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1875~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1876
David Cunado7c032642018-03-12 18:47:05 +00001877The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001878with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001879
1880::
1881
David Cunado7c032642018-03-12 18:47:05 +00001882 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001883 -C pctl.startup=0.0.0.0 \
1884 -C bp.secure_memory=1 \
1885 -C bp.tzc_400.diagnostics=1 \
1886 -C cluster0.NUM_CORES=4 \
1887 -C cluster1.NUM_CORES=4 \
1888 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00001889 -C cluster0.cpu0.RVBAR=0x04010000 \
1890 -C cluster0.cpu1.RVBAR=0x04010000 \
1891 -C cluster0.cpu2.RVBAR=0x04010000 \
1892 -C cluster0.cpu3.RVBAR=0x04010000 \
1893 -C cluster1.cpu0.RVBAR=0x04010000 \
1894 -C cluster1.cpu1.RVBAR=0x04010000 \
1895 -C cluster1.cpu2.RVBAR=0x04010000 \
1896 -C cluster1.cpu3.RVBAR=0x04010000 \
1897 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
1898 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001899 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001900 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001901 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001902 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001903
1904Notes:
1905
Soby Mathewba678c32018-12-12 14:54:23 +00001906- Since Position Independent Executable (PIE) support is enabled for BL31
1907 in this config, it can be loaded at any valid address for execution.
1908
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001909- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1910 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1911 parameter is needed to load the individual bootloader images in memory.
1912 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Soby Mathewecd94ad2018-05-09 13:59:29 +01001913 Payload. For the same reason, the FDT needs to be compiled from the DT source
1914 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
1915 parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001916
1917- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1918 X and Y are the cluster and CPU numbers respectively, is used to set the
1919 reset vector for each core.
1920
1921- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1922 changing the value of
1923 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1924 ``BL32_BASE``.
1925
1926Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1927~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1928
1929The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001930with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001931
1932::
1933
1934 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1935 -C pctl.startup=0.0.0.0 \
1936 -C bp.secure_memory=1 \
1937 -C bp.tzc_400.diagnostics=1 \
1938 -C cluster0.NUM_CORES=4 \
1939 -C cluster1.NUM_CORES=4 \
1940 -C cache_state_modelled=1 \
1941 -C cluster0.cpu0.CONFIG64=0 \
1942 -C cluster0.cpu1.CONFIG64=0 \
1943 -C cluster0.cpu2.CONFIG64=0 \
1944 -C cluster0.cpu3.CONFIG64=0 \
1945 -C cluster1.cpu0.CONFIG64=0 \
1946 -C cluster1.cpu1.CONFIG64=0 \
1947 -C cluster1.cpu2.CONFIG64=0 \
1948 -C cluster1.cpu3.CONFIG64=0 \
Soby Mathewba678c32018-12-12 14:54:23 +00001949 -C cluster0.cpu0.RVBAR=0x04002000 \
1950 -C cluster0.cpu1.RVBAR=0x04002000 \
1951 -C cluster0.cpu2.RVBAR=0x04002000 \
1952 -C cluster0.cpu3.RVBAR=0x04002000 \
1953 -C cluster1.cpu0.RVBAR=0x04002000 \
1954 -C cluster1.cpu1.RVBAR=0x04002000 \
1955 -C cluster1.cpu2.RVBAR=0x04002000 \
1956 -C cluster1.cpu3.RVBAR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001957 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001958 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001959 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001960 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001961 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001962
1963Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1964It should match the address programmed into the RVBAR register as well.
1965
1966Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1967~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1968
1969The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001970boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001971
1972::
1973
1974 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1975 -C pctl.startup=0.0.0.0 \
1976 -C bp.secure_memory=1 \
1977 -C bp.tzc_400.diagnostics=1 \
1978 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00001979 -C cluster0.cpu0.RVBARADDR=0x04010000 \
1980 -C cluster0.cpu1.RVBARADDR=0x04010000 \
1981 -C cluster0.cpu2.RVBARADDR=0x04010000 \
1982 -C cluster0.cpu3.RVBARADDR=0x04010000 \
1983 -C cluster1.cpu0.RVBARADDR=0x04010000 \
1984 -C cluster1.cpu1.RVBARADDR=0x04010000 \
1985 -C cluster1.cpu2.RVBARADDR=0x04010000 \
1986 -C cluster1.cpu3.RVBARADDR=0x04010000 \
1987 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
1988 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001989 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001990 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001991 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001992 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001993
1994Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1995~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1996
1997The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001998boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001999
2000::
2001
2002 <path-to>/FVP_Base_Cortex-A32x4 \
2003 -C pctl.startup=0.0.0.0 \
2004 -C bp.secure_memory=1 \
2005 -C bp.tzc_400.diagnostics=1 \
2006 -C cache_state_modelled=1 \
Soby Mathewba678c32018-12-12 14:54:23 +00002007 -C cluster0.cpu0.RVBARADDR=0x04002000 \
2008 -C cluster0.cpu1.RVBARADDR=0x04002000 \
2009 -C cluster0.cpu2.RVBARADDR=0x04002000 \
2010 -C cluster0.cpu3.RVBARADDR=0x04002000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01002011 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002012 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002013 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002014 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002015 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002016
2017Running the software on Juno
2018----------------------------
2019
Dan Handley610e7e12018-03-01 18:44:00 +00002020This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002021
2022To execute the software stack on Juno, the version of the Juno board recovery
2023image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2024earlier version installed or are unsure which version is installed, please
2025re-install the recovery image by following the
2026`Instructions for using Linaro's deliverables on Juno`_.
2027
Dan Handley610e7e12018-03-01 18:44:00 +00002028Preparing TF-A images
2029~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002030
Dan Handley610e7e12018-03-01 18:44:00 +00002031After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2032``SOFTWARE/`` directory of the Juno SD card.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002033
2034Other Juno software information
2035~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2036
Dan Handley610e7e12018-03-01 18:44:00 +00002037Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002038software information. Please also refer to the `Juno Getting Started Guide`_ to
Dan Handley610e7e12018-03-01 18:44:00 +00002039get more detailed information about the Juno Arm development platform and how to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002040configure it.
2041
2042Testing SYSTEM SUSPEND on Juno
2043~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2044
2045The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2046to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2047on Juno, at the linux shell prompt, issue the following command:
2048
2049::
2050
2051 echo +10 > /sys/class/rtc/rtc0/wakealarm
2052 echo -n mem > /sys/power/state
2053
2054The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2055wakeup interrupt from RTC.
2056
2057--------------
2058
Antonio Nino Diaz0e402d32019-01-30 16:01:49 +00002059*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002060
David Cunadob2de0992017-06-29 12:01:33 +01002061.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002062.. _Linaro Release: `Linaro Release Notes`_
David Cunado82509be2017-12-19 16:33:25 +00002063.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes
David Cunado82509be2017-12-19 16:33:25 +00002064.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables
2065.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Dan Handley610e7e12018-03-01 18:44:00 +00002066.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002067.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Paul Beesley8b4bdeb2019-01-21 12:06:24 +00002068.. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
Sandrine Bailleux771535b2018-09-20 10:27:13 +02002069.. _Linux master tree: https://github.com/torvalds/linux/tree/master/
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002070.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002071.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002072.. _Trusted Board Boot: trusted-board-boot.rst
Soby Mathewecd94ad2018-05-09 13:59:29 +01002073.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002074.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002075.. _Firmware Update: firmware-update.rst
2076.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002077.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2078.. _mbed TLS Security Center: https://tls.mbed.org/security
Dan Handley610e7e12018-03-01 18:44:00 +00002079.. _Arm's website: `FVP models`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002080.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002081.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01002082.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Sandrine Bailleux604f0a42018-09-20 12:44:39 +02002083.. _Secure Partition Manager Design guide: secure-partition-manager-design.rst
Paul Beesley8b4bdeb2019-01-21 12:06:24 +00002084.. _`Trusted Firmware-A Coding Guidelines`: coding-guidelines.rst