Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Roberto Vargas | 1a6eed3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 7 | #include <assert.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 8 | #include <errno.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | |
| 10 | #include <arch_helpers.h> |
| 11 | #include <common/debug.h> |
| 12 | #include <drivers/arm/gicv3.h> |
Antonio Nino Diaz | f13d09a | 2019-01-23 21:50:09 +0000 | [diff] [blame] | 13 | #include <drivers/arm/fvp/fvp_pwrc.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <lib/extensions/spe.h> |
| 15 | #include <lib/mmio.h> |
| 16 | #include <lib/psci/psci.h> |
Antonio Nino Diaz | bd7b740 | 2019-01-25 14:30:04 +0000 | [diff] [blame] | 17 | #include <plat/arm/common/arm_config.h> |
| 18 | #include <plat/arm/common/plat_arm.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 19 | #include <plat/common/platform.h> |
Antonio Nino Diaz | a320ecd | 2019-01-15 14:19:50 +0000 | [diff] [blame] | 20 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 21 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 22 | #include "fvp_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 23 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 24 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 25 | #if ARM_RECOM_STATE_ID_ENC |
| 26 | /* |
| 27 | * The table storing the valid idle power states. Ensure that the |
| 28 | * array entries are populated in ascending order of state-id to |
| 29 | * enable us to use binary search during power state validation. |
| 30 | * The table must be terminated by a NULL entry. |
| 31 | */ |
| 32 | const unsigned int arm_pm_idle_states[] = { |
| 33 | /* State-id - 0x01 */ |
| 34 | arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, |
| 35 | ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), |
| 36 | /* State-id - 0x02 */ |
| 37 | arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, |
| 38 | ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), |
| 39 | /* State-id - 0x22 */ |
| 40 | arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, |
| 41 | ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 42 | /* State-id - 0x222 */ |
| 43 | arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, |
| 44 | ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 45 | 0, |
| 46 | }; |
| 47 | #endif |
| 48 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 49 | /******************************************************************************* |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 50 | * Function which implements the common FVP specific operations to power down a |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 51 | * cluster in response to a CPU_OFF or CPU_SUSPEND request. |
| 52 | ******************************************************************************/ |
Sandrine Bailleux | a64a854 | 2015-03-05 10:54:34 +0000 | [diff] [blame] | 53 | static void fvp_cluster_pwrdwn_common(void) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 54 | { |
| 55 | uint64_t mpidr = read_mpidr_el1(); |
| 56 | |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 57 | #if ENABLE_SPE_FOR_LOWER_ELS |
| 58 | /* |
| 59 | * On power down we need to disable statistical profiling extensions |
| 60 | * before exiting coherency. |
| 61 | */ |
Dimitris Papastamos | 5bdbb47 | 2017-10-13 12:06:06 +0100 | [diff] [blame] | 62 | spe_disable(); |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 63 | #endif |
| 64 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 65 | /* Disable coherency if this cluster is to be turned off */ |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 66 | fvp_interconnect_disable(); |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 67 | |
| 68 | /* Program the power controller to turn the cluster off */ |
| 69 | fvp_pwrc_write_pcoffr(mpidr); |
| 70 | } |
| 71 | |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 72 | /* |
| 73 | * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit |
| 74 | * on ARM GICv3 implementations on FVP. This is required, because FVP does not |
| 75 | * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up |
| 76 | * from `fake` system suspend the GIC must not be powered off. |
| 77 | */ |
Roberto Vargas | 1a6eed3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 78 | void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num) |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 79 | {} |
| 80 | |
Roberto Vargas | 1a6eed3 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 81 | void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num) |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 82 | {} |
| 83 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 84 | static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) |
| 85 | { |
| 86 | unsigned long mpidr; |
| 87 | |
| 88 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 89 | ARM_LOCAL_STATE_OFF); |
| 90 | |
| 91 | /* Get the mpidr for this cpu */ |
| 92 | mpidr = read_mpidr_el1(); |
| 93 | |
| 94 | /* Perform the common cluster specific operations */ |
| 95 | if (target_state->pwr_domain_state[ARM_PWR_LVL1] == |
| 96 | ARM_LOCAL_STATE_OFF) { |
| 97 | /* |
| 98 | * This CPU might have woken up whilst the cluster was |
| 99 | * attempting to power down. In this case the FVP power |
| 100 | * controller will have a pending cluster power off request |
| 101 | * which needs to be cleared by writing to the PPONR register. |
| 102 | * This prevents the power controller from interpreting a |
| 103 | * subsequent entry of this cpu into a simple wfi as a power |
| 104 | * down request. |
| 105 | */ |
| 106 | fvp_pwrc_write_pponr(mpidr); |
| 107 | |
| 108 | /* Enable coherency if this cluster was off */ |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 109 | fvp_interconnect_enable(); |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 110 | } |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 111 | /* Perform the common system specific operations */ |
| 112 | if (target_state->pwr_domain_state[ARM_PWR_LVL2] == |
| 113 | ARM_LOCAL_STATE_OFF) |
| 114 | arm_system_pwr_domain_resume(); |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * Clear PWKUPR.WEN bit to ensure interrupts do not interfere |
| 118 | * with a cpu power down unless the bit is set again |
| 119 | */ |
| 120 | fvp_pwrc_clr_wen(mpidr); |
| 121 | } |
| 122 | |
| 123 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 124 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 125 | * FVP handler called when a CPU is about to enter standby. |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 126 | ******************************************************************************/ |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 127 | static void fvp_cpu_standby(plat_local_state_t cpu_state) |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 128 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 129 | |
| 130 | assert(cpu_state == ARM_LOCAL_STATE_RET); |
| 131 | |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 132 | /* |
| 133 | * Enter standby state |
| 134 | * dsb is good practice before using wfi to enter low power states |
| 135 | */ |
| 136 | dsb(); |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 137 | wfi(); |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 141 | * FVP handler called when a power domain is about to be turned on. The |
| 142 | * mpidr determines the CPU to be turned on. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 143 | ******************************************************************************/ |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 144 | static int fvp_pwr_domain_on(u_register_t mpidr) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 145 | { |
| 146 | int rc = PSCI_E_SUCCESS; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 147 | unsigned int psysr; |
| 148 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 149 | /* |
Sandrine Bailleux | 7175bde | 2015-12-08 14:18:24 +0000 | [diff] [blame] | 150 | * Ensure that we do not cancel an inflight power off request for the |
| 151 | * target cpu. That would leave it in a zombie wfi. Wait for it to power |
| 152 | * off and then program the power controller to turn that CPU on. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 153 | */ |
| 154 | do { |
| 155 | psysr = fvp_pwrc_read_psysr(mpidr); |
Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 156 | } while ((psysr & PSYSR_AFF_L0) != 0U); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 157 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 158 | fvp_pwrc_write_pponr(mpidr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 159 | return rc; |
| 160 | } |
| 161 | |
| 162 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 163 | * FVP handler called when a power domain is about to be turned off. The |
| 164 | * target_state encodes the power state that each level should transition to. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 165 | ******************************************************************************/ |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 166 | static void fvp_pwr_domain_off(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 167 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 168 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 169 | ARM_LOCAL_STATE_OFF); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 170 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 171 | /* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 172 | * If execution reaches this stage then this power domain will be |
| 173 | * suspended. Perform at least the cpu specific actions followed |
| 174 | * by the cluster specific operations if applicable. |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 175 | */ |
Jeenu Viswambharan | 6ad3548 | 2016-12-09 11:14:34 +0000 | [diff] [blame] | 176 | |
| 177 | /* Prevent interrupts from spuriously waking up this cpu */ |
| 178 | plat_arm_gic_cpuif_disable(); |
| 179 | |
| 180 | /* Turn redistributor off */ |
| 181 | plat_arm_gic_redistif_off(); |
| 182 | |
| 183 | /* Program the power controller to power off this cpu. */ |
| 184 | fvp_pwrc_write_ppoffr(read_mpidr_el1()); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 185 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 186 | if (target_state->pwr_domain_state[ARM_PWR_LVL1] == |
| 187 | ARM_LOCAL_STATE_OFF) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 188 | fvp_cluster_pwrdwn_common(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 189 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 193 | * FVP handler called when a power domain is about to be suspended. The |
| 194 | * target_state encodes the power state that each level should transition to. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 195 | ******************************************************************************/ |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 196 | static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 197 | { |
Soby Mathew | ffb4ab1 | 2014-09-26 15:08:52 +0100 | [diff] [blame] | 198 | unsigned long mpidr; |
| 199 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 200 | /* |
| 201 | * FVP has retention only at cpu level. Just return |
| 202 | * as nothing is to be done for retention. |
| 203 | */ |
| 204 | if (target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 205 | ARM_LOCAL_STATE_RET) |
Soby Mathew | 74e52a7 | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 206 | return; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 207 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 208 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 209 | ARM_LOCAL_STATE_OFF); |
| 210 | |
Soby Mathew | ffb4ab1 | 2014-09-26 15:08:52 +0100 | [diff] [blame] | 211 | /* Get the mpidr for this cpu */ |
| 212 | mpidr = read_mpidr_el1(); |
| 213 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 214 | /* Program the power controller to enable wakeup interrupts. */ |
| 215 | fvp_pwrc_set_wen(mpidr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 216 | |
Jeenu Viswambharan | 6ad3548 | 2016-12-09 11:14:34 +0000 | [diff] [blame] | 217 | /* Prevent interrupts from spuriously waking up this cpu */ |
| 218 | plat_arm_gic_cpuif_disable(); |
| 219 | |
| 220 | /* |
| 221 | * The Redistributor is not powered off as it can potentially prevent |
| 222 | * wake up events reaching the CPUIF and/or might lead to losing |
| 223 | * register context. |
| 224 | */ |
| 225 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 226 | /* Perform the common cluster specific operations */ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 227 | if (target_state->pwr_domain_state[ARM_PWR_LVL1] == |
| 228 | ARM_LOCAL_STATE_OFF) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 229 | fvp_cluster_pwrdwn_common(); |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 230 | |
| 231 | /* Perform the common system specific operations */ |
| 232 | if (target_state->pwr_domain_state[ARM_PWR_LVL2] == |
| 233 | ARM_LOCAL_STATE_OFF) |
| 234 | arm_system_pwr_domain_save(); |
| 235 | |
| 236 | /* Program the power controller to power off this cpu. */ |
| 237 | fvp_pwrc_write_ppoffr(read_mpidr_el1()); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 238 | } |
| 239 | |
| 240 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 241 | * FVP handler called when a power domain has just been powered on after |
| 242 | * being turned off earlier. The target_state encodes the low power state that |
| 243 | * each level has woken up from. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 244 | ******************************************************************************/ |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 245 | static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 246 | { |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 247 | fvp_power_domain_on_finish_common(target_state); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 248 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 249 | /* Enable the gic cpu interface */ |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 250 | plat_arm_gic_pcpu_init(); |
| 251 | |
| 252 | /* Program the gic per-cpu distributor or re-distributor interface */ |
| 253 | plat_arm_gic_cpuif_enable(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 257 | * FVP handler called when a power domain has just been powered on after |
| 258 | * having been suspended earlier. The target_state encodes the low power state |
| 259 | * that each level has woken up from. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 260 | * TODO: At the moment we reuse the on finisher and reinitialize the secure |
| 261 | * context. Need to implement a separate suspend finisher. |
| 262 | ******************************************************************************/ |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 263 | static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 264 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 265 | /* |
| 266 | * Nothing to be done on waking up from retention from CPU level. |
| 267 | */ |
| 268 | if (target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 269 | ARM_LOCAL_STATE_RET) |
| 270 | return; |
| 271 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 272 | fvp_power_domain_on_finish_common(target_state); |
| 273 | |
| 274 | /* Enable the gic cpu interface */ |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 275 | plat_arm_gic_cpuif_enable(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 276 | } |
| 277 | |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 278 | /******************************************************************************* |
| 279 | * FVP handlers to shutdown/reboot the system |
| 280 | ******************************************************************************/ |
| 281 | static void __dead2 fvp_system_off(void) |
| 282 | { |
| 283 | /* Write the System Configuration Control Register */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 284 | mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| 285 | V2M_CFGCTRL_START | |
| 286 | V2M_CFGCTRL_RW | |
| 287 | V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 288 | wfi(); |
| 289 | ERROR("FVP System Off: operation not handled.\n"); |
| 290 | panic(); |
| 291 | } |
| 292 | |
| 293 | static void __dead2 fvp_system_reset(void) |
| 294 | { |
| 295 | /* Write the System Configuration Control Register */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 296 | mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| 297 | V2M_CFGCTRL_START | |
| 298 | V2M_CFGCTRL_RW | |
| 299 | V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 300 | wfi(); |
| 301 | ERROR("FVP System Reset: operation not handled.\n"); |
| 302 | panic(); |
| 303 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 304 | |
Jeenu Viswambharan | 095529a | 2016-08-04 09:43:15 +0100 | [diff] [blame] | 305 | static int fvp_node_hw_state(u_register_t target_cpu, |
| 306 | unsigned int power_level) |
| 307 | { |
| 308 | unsigned int psysr; |
| 309 | int ret; |
| 310 | |
| 311 | /* |
| 312 | * The format of 'power_level' is implementation-defined, but 0 must |
| 313 | * mean a CPU. We also allow 1 to denote the cluster |
| 314 | */ |
Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 315 | if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1)) |
Jeenu Viswambharan | 095529a | 2016-08-04 09:43:15 +0100 | [diff] [blame] | 316 | return PSCI_E_INVALID_PARAMS; |
| 317 | |
| 318 | /* |
| 319 | * Read the status of the given MPDIR from FVP power controller. The |
| 320 | * power controller only gives us on/off status, so map that to expected |
| 321 | * return values of the PSCI call |
| 322 | */ |
| 323 | psysr = fvp_pwrc_read_psysr(target_cpu); |
| 324 | if (psysr == PSYSR_INVALID) |
| 325 | return PSCI_E_INVALID_PARAMS; |
| 326 | |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 327 | if (power_level == ARM_PWR_LVL0) { |
Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 328 | ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF; |
Jonathan Wright | ff957ed | 2018-03-14 15:24:00 +0000 | [diff] [blame] | 329 | } else { |
| 330 | /* power_level == ARM_PWR_LVL1 */ |
Sathees Balya | 50905c7 | 2018-10-05 13:30:59 +0100 | [diff] [blame] | 331 | ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF; |
Jeenu Viswambharan | 095529a | 2016-08-04 09:43:15 +0100 | [diff] [blame] | 332 | } |
| 333 | |
| 334 | return ret; |
| 335 | } |
| 336 | |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 337 | /* |
| 338 | * The FVP doesn't truly support power management at SYSTEM power domain. The |
| 339 | * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform |
| 340 | * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver |
| 341 | * save and restore sequences on FVP. |
| 342 | */ |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 343 | #if !ARM_BL31_IN_DRAM |
| 344 | static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state) |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 345 | { |
| 346 | unsigned int i; |
| 347 | |
| 348 | for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) |
| 349 | req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; |
| 350 | } |
Roberto Vargas | 2ca18d9 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 351 | #endif |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 352 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 353 | /******************************************************************************* |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 354 | * Handler to filter PSCI requests. |
| 355 | ******************************************************************************/ |
| 356 | /* |
| 357 | * The system power domain suspend is only supported only via |
| 358 | * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain |
| 359 | * will be downgraded to the lower level. |
| 360 | */ |
| 361 | static int fvp_validate_power_state(unsigned int power_state, |
| 362 | psci_power_state_t *req_state) |
| 363 | { |
| 364 | int rc; |
| 365 | rc = arm_validate_power_state(power_state, req_state); |
| 366 | |
| 367 | /* |
| 368 | * Ensure that the system power domain level is never suspended |
| 369 | * via PSCI CPU SUSPEND API. Currently system suspend is only |
| 370 | * supported via PSCI SYSTEM SUSPEND API. |
| 371 | */ |
| 372 | req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN; |
| 373 | return rc; |
| 374 | } |
| 375 | |
| 376 | /* |
| 377 | * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the |
| 378 | * `fvp_validate_power_state`, we do not downgrade the system power |
| 379 | * domain level request in `power_state` as it will be used to query the |
| 380 | * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. |
| 381 | */ |
| 382 | static int fvp_translate_power_state_by_mpidr(u_register_t mpidr, |
| 383 | unsigned int power_state, |
| 384 | psci_power_state_t *output_state) |
| 385 | { |
| 386 | return arm_validate_power_state(power_state, output_state); |
| 387 | } |
| 388 | |
| 389 | /******************************************************************************* |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 390 | * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard |
| 391 | * platform layer will take care of registering the handlers with PSCI. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 392 | ******************************************************************************/ |
Soby Mathew | 0b4c5a3 | 2016-10-21 17:51:22 +0100 | [diff] [blame] | 393 | plat_psci_ops_t plat_arm_psci_pm_ops = { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 394 | .cpu_standby = fvp_cpu_standby, |
| 395 | .pwr_domain_on = fvp_pwr_domain_on, |
| 396 | .pwr_domain_off = fvp_pwr_domain_off, |
| 397 | .pwr_domain_suspend = fvp_pwr_domain_suspend, |
| 398 | .pwr_domain_on_finish = fvp_pwr_domain_on_finish, |
| 399 | .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 400 | .system_off = fvp_system_off, |
Soby Mathew | 74e52a7 | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 401 | .system_reset = fvp_system_reset, |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 402 | .validate_power_state = fvp_validate_power_state, |
Jeenu Viswambharan | 59424d8 | 2017-09-19 09:27:18 +0100 | [diff] [blame] | 403 | .validate_ns_entrypoint = arm_validate_psci_entrypoint, |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 404 | .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr, |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 405 | .get_node_hw_state = fvp_node_hw_state, |
Antonio Nino Diaz | 0b6af83 | 2017-11-22 12:00:44 +0000 | [diff] [blame] | 406 | #if !ARM_BL31_IN_DRAM |
| 407 | /* |
| 408 | * The TrustZone Controller is set up during the warmboot sequence after |
| 409 | * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM |
| 410 | * this is not a problem but, if it is in TZC-secured DRAM, it tries to |
| 411 | * reconfigure the same memory it is running on, causing an exception. |
| 412 | */ |
Soby Mathew | 9ca2806 | 2017-10-11 16:08:58 +0100 | [diff] [blame] | 413 | .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state, |
Antonio Nino Diaz | 0b6af83 | 2017-11-22 12:00:44 +0000 | [diff] [blame] | 414 | #endif |
Roberto Vargas | a1c16b6 | 2017-08-03 09:16:43 +0100 | [diff] [blame] | 415 | .mem_protect_chk = arm_psci_mem_protect_chk, |
| 416 | .read_mem_protect = arm_psci_read_mem_protect, |
| 417 | .write_mem_protect = arm_nor_psci_write_mem_protect, |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 418 | }; |
Chandni Cherukuri | e4bf6a0 | 2018-11-14 13:43:59 +0530 | [diff] [blame] | 419 | |
| 420 | const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) |
| 421 | { |
| 422 | return ops; |
| 423 | } |