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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handleyed6ff952014-05-14 17:44:19 +010031#include <platform_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000035ENTRY(bl1_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
37MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010038 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
39 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010040}
41
42SECTIONS
43{
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010044 . = BL1_RO_BASE;
45 ASSERT(. == ALIGN(4096),
46 "BL1_RO_BASE address is not aligned on a page boundary.")
47
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010048#if SEPARATE_CODE_AND_RODATA
49 .text . : {
50 __TEXT_START__ = .;
51 *bl1_entrypoint.o(.text*)
52 *(.text*)
53 *(.vectors)
54 . = NEXT(4096);
55 __TEXT_END__ = .;
56 } >ROM
57
58 .rodata . : {
59 __RODATA_START__ = .;
60 *(.rodata*)
61
62 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
63 . = ALIGN(8);
64 __PARSER_LIB_DESCS_START__ = .;
65 KEEP(*(.img_parser_lib_descs))
66 __PARSER_LIB_DESCS_END__ = .;
67
68 /*
69 * Ensure 8-byte alignment for cpu_ops so that its fields are also
70 * aligned. Also ensure cpu_ops inclusion.
71 */
72 . = ALIGN(8);
73 __CPU_OPS_START__ = .;
74 KEEP(*(cpu_ops))
75 __CPU_OPS_END__ = .;
76
77 /*
78 * No need to pad out the .rodata section to a page boundary. Next is
79 * the .data section, which can mapped in ROM with the same memory
80 * attributes as the .rodata section.
81 */
82 __RODATA_END__ = .;
83 } >ROM
84#else
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010085 ro . : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000086 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000087 *bl1_entrypoint.o(.text*)
88 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000089 *(.rodata*)
Soby Mathewc704cbc2014-08-14 11:33:56 +010090
Juan Castillo8e55d932015-04-02 09:48:16 +010091 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
92 . = ALIGN(8);
93 __PARSER_LIB_DESCS_START__ = .;
94 KEEP(*(.img_parser_lib_descs))
95 __PARSER_LIB_DESCS_END__ = .;
96
Soby Mathewc704cbc2014-08-14 11:33:56 +010097 /*
98 * Ensure 8-byte alignment for cpu_ops so that its fields are also
99 * aligned. Also ensure cpu_ops inclusion.
100 */
101 . = ALIGN(8);
102 __CPU_OPS_START__ = .;
103 KEEP(*(cpu_ops))
104 __CPU_OPS_END__ = .;
105
Achin Guptab739f222014-01-18 16:50:09 +0000106 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000107 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100108 } >ROM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +0100109#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110
Soby Mathewc704cbc2014-08-14 11:33:56 +0100111 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
112 "cpu_ops not defined for this platform.")
113
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000114 /*
115 * The .data section gets copied from ROM to RAM at runtime.
Sandrine Bailleuxf7488062014-05-22 15:21:35 +0100116 * Its LMA must be 16-byte aligned.
117 * Its VMA must be page-aligned as it marks the first read/write page.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000118 */
Sandrine Bailleuxf7488062014-05-22 15:21:35 +0100119 . = BL1_RW_BASE;
120 ASSERT(. == ALIGN(4096),
121 "BL1_RW_BASE address is not aligned on a page boundary.")
122 .data . : ALIGN(16) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123 __DATA_RAM_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000124 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000125 __DATA_RAM_END__ = .;
126 } >RAM AT>ROM
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127
Sandrine Bailleuxf7488062014-05-22 15:21:35 +0100128 stacks . (NOLOAD) : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000129 __STACKS_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100130 *(tzfw_normal_stacks)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000131 __STACKS_END__ = .;
132 } >RAM
133
134 /*
135 * The .bss section gets initialised to 0 at runtime.
136 * Its base address must be 16-byte aligned.
137 */
138 .bss : ALIGN(16) {
139 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000140 *(.bss*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000141 *(COMMON)
142 __BSS_END__ = .;
143 } >RAM
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000145 /*
Achin Guptaa0cd9892014-02-09 13:30:38 +0000146 * The xlat_table section is for full, aligned page tables (4K).
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000147 * Removing them from .bss avoids forcing 4K alignment on
148 * the .bss section and eliminates the unecessary zero init
149 */
150 xlat_table (NOLOAD) : {
151 *(xlat_table)
152 } >RAM
153
Soby Mathew2ae20432015-01-08 18:02:44 +0000154#if USE_COHERENT_MEM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000155 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000156 * The base address of the coherent memory section must be page-aligned (4K)
157 * to guarantee that the coherent data are stored on their own pages and
158 * are not mixed with normal data. This is required to set up the correct
159 * memory attributes for the coherent data page tables.
160 */
161 coherent_ram (NOLOAD) : ALIGN(4096) {
162 __COHERENT_RAM_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100163 *(tzfw_coherent_mem)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000164 __COHERENT_RAM_END_UNALIGNED__ = .;
165 /*
166 * Memory page(s) mapped to this section will be marked
167 * as device memory. No other unexpected data must creep in.
168 * Ensure the rest of the current memory page is unused.
169 */
170 . = NEXT(4096);
171 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000173#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000175 __BL1_RAM_START__ = ADDR(.data);
176 __BL1_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100177
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000178 __DATA_ROM_START__ = LOADADDR(.data);
179 __DATA_SIZE__ = SIZEOF(.data);
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100180
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100181 /*
182 * The .data section is the last PROGBITS section so its end marks the end
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100183 * of BL1's actual content in Trusted ROM.
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100184 */
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100185 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
186 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
187 "BL1's ROM content has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000189 __BSS_SIZE__ = SIZEOF(.bss);
190
Soby Mathew2ae20432015-01-08 18:02:44 +0000191#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000192 __COHERENT_RAM_UNALIGNED_SIZE__ =
193 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000194#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100195
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100196 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197}