Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef CORTEX_A72_H |
| 8 | #define CORTEX_A72_H |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | |
| 10 | #include <lib/utils_def.h> |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 11 | |
| 12 | /* Cortex-A72 midr for revision 0 */ |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 13 | #define CORTEX_A72_MIDR U(0x410FD080) |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 18 | #define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 19 | |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 20 | #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) |
| 21 | #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) |
| 22 | #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) |
| 23 | #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 24 | |
| 25 | /******************************************************************************* |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 26 | * CPU Memory Error Syndrome register specific definitions. |
| 27 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 28 | #define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 29 | |
| 30 | /******************************************************************************* |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 31 | * CPU Auxiliary Control register specific definitions. |
| 32 | ******************************************************************************/ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 33 | #define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 34 | |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 35 | #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 36 | #define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 37 | #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) |
| 38 | #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) |
Eleanor Bonnici | c3b4ca1 | 2017-08-02 18:33:41 +0100 | [diff] [blame] | 39 | #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 40 | |
| 41 | /******************************************************************************* |
Konstantin Porotchkin | 9eb5cf4 | 2018-07-05 11:28:02 +0300 | [diff] [blame] | 42 | * L2 Auxiliary Control register specific definitions. |
| 43 | ******************************************************************************/ |
| 44 | #define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 |
| 45 | |
| 46 | #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) |
| 47 | |
| 48 | /******************************************************************************* |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 49 | * L2 Control register specific definitions. |
| 50 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 51 | #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 52 | |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 53 | #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) |
| 54 | #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 55 | |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 56 | #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) |
| 57 | #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) |
| 58 | #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 59 | |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 60 | /******************************************************************************* |
| 61 | * L2 Memory Error Syndrome register specific definitions. |
| 62 | ******************************************************************************/ |
Eleanor Bonnici | b83e42b | 2017-08-09 10:36:08 +0100 | [diff] [blame] | 63 | #define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 64 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 65 | #endif /* CORTEX_A72_H */ |