commit 41b61be7f896e85ec40f1f4f638410996c8acd13
author Eleanor Bonnici <Eleanor.bonnici@arm.com> Wed Aug 09 16:42:40 2017 +0100
committer Jeenu Viswambharan <jeenu.viswambharan@arm.com> Tue Aug 29 13:52:48 2017 +0100
tree 51c49c24e12a7666499bc13e68198ce4f997c210
parent b83e42b31c400f6fd9476da84c92e6dd56a751e7

CPU: Correct names of implementation-defined aux regs

At present, various CPU register macros that refer to CPUACTLR are named
ACTLR. This patch fixes that.

The previous register names are retained, but guarded by the
ERROR_DEPRECATED macro, so as not to break platforms that continue using
the old names.

Change-Id: Ia872196d81803f8f390b887d149e0fd054df519b
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>

include/lib/cpus/aarch64/cortex_a72.h

diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index a30abe8..aed714c 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -29,11 +29,11 @@
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A72_ACTLR_EL1				S3_1_C15_C2_0
+#define CORTEX_A72_CPUACTLR_EL1					S3_1_C15_C2_0
 
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			(ULL(1) << 49)
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI			(ULL(1) << 44)
+#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
+#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA			(ULL(1) << 49)
+#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI			(ULL(1) << 44)
 
 /*******************************************************************************
  * L2 Control register specific definitions.
@@ -52,4 +52,16 @@
  ******************************************************************************/
 #define CORTEX_A72_L2MERRSR_EL1				S3_1_C15_C2_3
 
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A72_ACTLR				CORTEX_A72_CPUACTLR_EL1
+
+#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
+#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
+#define CORTEX_A72_ACTLR_DCC_AS_DCCI			CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
+#endif /* !ERROR_DEPRECATED */
+
 #endif /* __CORTEX_A72_H__ */