diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index a30abe8..aed714c 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -29,11 +29,11 @@
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A72_ACTLR_EL1				S3_1_C15_C2_0
+#define CORTEX_A72_CPUACTLR_EL1					S3_1_C15_C2_0
 
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			(ULL(1) << 49)
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI			(ULL(1) << 44)
+#define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH	(ULL(1) << 56)
+#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA			(ULL(1) << 49)
+#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI			(ULL(1) << 44)
 
 /*******************************************************************************
  * L2 Control register specific definitions.
@@ -52,4 +52,16 @@
  ******************************************************************************/
 #define CORTEX_A72_L2MERRSR_EL1				S3_1_C15_C2_3
 
+#if !ERROR_DEPRECATED
+/*
+ * These registers were previously wrongly named. Provide previous definitions so
+ * as not to break platforms that continue using them.
+ */
+#define CORTEX_A72_ACTLR				CORTEX_A72_CPUACTLR_EL1
+
+#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH	CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
+#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA			CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
+#define CORTEX_A72_ACTLR_DCC_AS_DCCI			CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
+#endif /* !ERROR_DEPRECATED */
+
 #endif /* __CORTEX_A72_H__ */