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Dan Handley610e7e12018-03-01 18:44:00 +00001Arm CPU Specific Build Macros
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002=============================
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4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
10This document describes the various build options present in the CPU specific
11operations framework to enable errata workarounds and to enable optimizations
12for a specific CPU on a platform.
13
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000014Security Vulnerability Workarounds
15----------------------------------
16
Dan Handley610e7e12018-03-01 18:44:00 +000017TF-A exports a series of build flags which control which security
18vulnerability workarounds should be applied at runtime.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000019
20- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for
Dimitris Papastamos6d1f4992018-03-28 12:06:40 +010021 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
22 of the PEs in the system need the workaround. Setting this flag to 0 provides
23 no performance benefit for non-affected platforms, it just helps to comply
24 with the recommendation in the spec regarding workaround discovery.
25 Defaults to 1.
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000026
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010027- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for
28 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep
29 the default value of 1 even on platforms that are unaffected by
30 CVE-2018-3639, in order to comply with the recommendation in the spec
31 regarding workaround discovery.
32
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010033- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for
34 `CVE-2018-3639`_. This build option should be set to 1 if the target
35 platform contains at least 1 CPU that requires dynamic mitigation.
36 Defaults to 0.
37
Douglas Raillardd7c21b72017-06-28 15:23:03 +010038CPU Errata Workarounds
39----------------------
40
Dan Handley610e7e12018-03-01 18:44:00 +000041TF-A exports a series of build flags which control the errata workarounds that
42are applied to each CPU by the reset handler. The errata details can be found
43in the CPU specific errata documents published by Arm:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010044
45- `Cortex-A53 MPCore Software Developers Errata Notice`_
46- `Cortex-A57 MPCore Software Developers Errata Notice`_
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +010047- `Cortex-A72 MPCore Software Developers Errata Notice`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +010048
49The errata workarounds are implemented for a particular revision or a set of
50processor revisions. This is checked by the reset handler at runtime. Each
51errata workaround is identified by its ``ID`` as specified in the processor's
52errata notice document. The format of the define used to enable/disable the
53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name``
54is for example ``A57`` for the ``Cortex_A57`` CPU.
55
56Refer to the section *CPU errata status reporting* in
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +010057`Firmware Design guide`_ for information on how to write errata workaround
58functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010059
60All workarounds are disabled by default. The platform is responsible for
61enabling these workarounds according to its requirement by defining the
62errata workaround build flags in the platform specific makefile. In case
63these workarounds are enabled for the wrong CPU revision then the errata
64workaround is not applied. In the DEBUG build, this is indicated by
65printing a warning to the crash console.
66
67In the current implementation, a platform which has more than 1 variant
68with different revisions of a processor has no runtime mechanism available
69for it to specify which errata workarounds should be enabled or not.
70
John Tsichritzis4daa1de2018-07-23 09:11:59 +010071The value of the build flags is 0 by default, that is, disabled. A value of 1
72will enable it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010073
Joel Hutton26d16762019-04-10 12:52:52 +010074For Cortex-A9, the following errata build flags are defined :
75
Louis Mayencourte6469d52019-04-18 12:11:25 +010076- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9
Joel Hutton26d16762019-04-10 12:52:52 +010077 CPU. This needs to be enabled for all revisions of the CPU.
78
Ambroise Vincentd4a51eb2019-03-04 16:56:26 +000079For Cortex-A15, the following errata build flags are defined :
80
81- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15
82 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
83
Ambroise Vincent68b38122019-03-05 09:54:21 +000084- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15
85 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
86
Ambroise Vincent8cf9eef2019-02-28 16:23:53 +000087For Cortex-A17, the following errata build flags are defined :
88
89- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17
90 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
91
Ambroise Vincentfa5c9512019-03-04 13:20:56 +000092- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17
93 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
94
Louis Mayencourt8a061272019-04-05 16:25:25 +010095For Cortex-A35, the following errata build flags are defined :
96
97- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35
98 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
99
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100100For Cortex-A53, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100101
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000102- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all
103 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
104
105- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all
106 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
107
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100108- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53
109 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
110
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000111- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all
112 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
113
Douglas Raillardb52353a2017-07-17 14:14:52 +0100114- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and
115 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
116 revision <= r0p4. This workaround can lead the linker to create ``*.stub``
117 sections.
118
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100119- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53
120 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
121 r0p4 and onwards, this errata is enabled by default in hardware.
122
Douglas Raillardb52353a2017-07-17 14:14:52 +0100123- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time
124 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
125 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections
126 which are 4kB aligned.
127
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100128- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
129 CPUs. Though the erratum is present in every revision of the CPU,
130 this workaround is only applied to CPUs from r0p3 onwards, which feature
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100131 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100132 Earlier revisions of the CPU have other errata which require the same
133 workaround in software, so they should be covered anyway.
134
Ambroise Vincent7927fa02019-02-21 16:20:43 +0000135For Cortex-A55, the following errata build flags are defined :
136
137- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
138 CPU. This needs to be enabled only for revision r0p0 of the CPU.
139
Ambroise Vincent6f319602019-02-21 16:25:37 +0000140- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55
141 CPU. This needs to be enabled only for revision r0p0 of the CPU.
142
Ambroise Vincent6a77f052019-02-21 16:27:34 +0000143- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55
144 CPU. This needs to be enabled only for revision r0p0 of the CPU.
145
Ambroise Vincentdd961f72019-02-21 16:29:16 +0000146- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55
147 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
148
Ambroise Vincenta1d64462019-02-21 16:29:50 +0000149- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55
150 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
151
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100152For Cortex-A57, the following errata build flags are defined :
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100153
154- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
155 CPU. This needs to be enabled only for revision r0p0 of the CPU.
156
157- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
158 CPU. This needs to be enabled only for revision r0p0 of the CPU.
159
160- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
161 CPU. This needs to be enabled only for revision r0p0 of the CPU.
162
Ambroise Vincent1b0db762019-02-21 16:35:07 +0000163- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
164 CPU. This needs to be enabled only for revision r0p0 of the CPU.
165
Ambroise Vincentaa2c0292019-02-21 16:35:49 +0000166- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
167 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
168
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
170 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
171
172- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
173 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
174
175- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
176 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
177
178- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
179 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
180
181- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
182 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
183
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100184- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
185 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
186
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100187
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100188For Cortex-A72, the following errata build flags are defined :
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100189
190- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
191 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
192
Louis Mayencourt4405de62019-02-21 16:38:16 +0000193For Cortex-A73, the following errata build flags are defined :
194
Louis Mayencourtd69722c2019-02-27 14:24:16 +0000195- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
196 CPU. This needs to be enabled only for revision r0p0 of the CPU.
197
Louis Mayencourt4405de62019-02-21 16:38:16 +0000198- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
199 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
200
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000201For Cortex-A75, the following errata build flags are defined :
202
203- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
204 CPU. This needs to be enabled only for revision r0p0 of the CPU.
205
Louis Mayencourt8d868702019-02-25 14:57:57 +0000206- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
207 CPU. This needs to be enabled only for revision r0p0 of the CPU.
208
Louis Mayencourt09924472019-02-21 17:35:07 +0000209For Cortex-A76, the following errata build flags are defined :
210
Louis Mayencourt59fa2182019-02-25 15:17:44 +0000211- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76
212 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
213
Louis Mayencourt09924472019-02-21 17:35:07 +0000214- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
215 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
216
Louis Mayencourtadda9d42019-02-25 11:37:38 +0000217- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
218 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
219
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100220DSU Errata Workarounds
221----------------------
222
223Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
224Shared Unit) errata. The DSU errata details can be found in the respective Arm
225documentation:
226
227- `Arm DSU Software Developers Errata Notice`_.
228
229Each erratum is identified by an ``ID``, as defined in the DSU errata notice
230document. Thus, the build flags which enable/disable the errata workarounds
231have the format ``ERRATA_DSU_<ID>``. The implementation and application logic
232of DSU errata workarounds are similar to `CPU errata workarounds`_.
233
234For DSU errata, the following build flags are defined:
235
Louis Mayencourt4498b152019-04-09 16:29:01 +0100236- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the
237 affected DSU configurations. This errata applies only for those DSUs that
238 revision is r0p0 (on r0p1 it is fixed). However, please note that this
239 workaround results in increased DSU power consumption on idle.
240
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100241- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the
242 affected DSU configurations. This errata applies only for those DSUs that
243 contain the ACP interface **and** the DSU revision is older than r2p0 (on
244 r2p0 it is fixed). However, please note that this workaround results in
245 increased DSU power consumption on idle.
246
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100247CPU Specific optimizations
248--------------------------
249
250This section describes some of the optimizations allowed by the CPU micro
251architecture that can be enabled by the platform as desired.
252
253- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
254 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
255 cache. The L1 data cache and the L2 unified cache are inclusive. A flush
256 of the L2 by set/way flushes any dirty lines from the L1 as well. This
257 is a known safe deviation from the Cortex-A57 TRM defined power down
258 sequence. Each Cortex-A57 based platform must make its own decision on
259 whether to use the optimization.
260
261- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal
262 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave
263 in a way most programmers expect, and will most probably result in a
Dan Handley610e7e12018-03-01 18:44:00 +0000264 significant speed degradation to any code that employs them. The Armv8-A
265 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100266 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this
267 flag enforces this behaviour. This needs to be enabled only for revisions
268 <= r0p3 of the CPU and is enabled by default.
269
270- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as
271 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
272 enabled only for revisions <= r1p2 of the CPU and is enabled by default,
273 as recommended in section "4.7 Non-Temporal Loads/Stores" of the
274 `Cortex-A57 Software Optimization Guide`_.
275
276--------------
277
Joel Hutton26d16762019-04-10 12:52:52 +0100278*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100279
John Tsichritzis3eeac412018-09-04 10:56:53 +0100280.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
281.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
Paul Beesley2437ddc2019-02-08 16:43:05 +0000282.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html
283.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100284.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100285.. _Firmware Design guide: firmware-design.rst
286.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100287.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html