blob: 26c7578929461866774fcc16a0c72ab0d3e13194 [file] [log] [blame]
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01001/*
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06002 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef EL3_COMMON_MACROS_S
8#define EL3_COMMON_MACROS_S
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01009
10#include <arch.h>
11#include <asm_macros.S>
Daniel Boulby928747f2021-05-25 18:09:34 +010012#include <assert_macros.S>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010013#include <context.h>
Varun Wadekar5dc9e9c2020-05-16 20:59:30 -070014#include <lib/xlat_tables/xlat_tables_defs.h>
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010015
16 /*
17 * Helper macro to initialise EL3 registers we care about.
18 */
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000019 .macro el3_arch_init_common
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010020 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010021 * SCTLR_EL3 has already been initialised - read current value before
22 * modifying.
23 *
24 * SCTLR_EL3.I: Enable the instruction cache.
25 *
Qixiang Xu3cc39172018-03-05 09:31:11 +080026 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
David Cunadofee86532017-04-13 22:38:29 +010027 * exception is generated if a load or store instruction executed at
28 * EL3 uses the SP as the base address and the SP is not aligned to a
29 * 16-byte boundary.
30 *
31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
32 * load or store one or more registers have an alignment check that the
33 * address being accessed is aligned to the size of the data element(s)
34 * being accessed.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010035 * ---------------------------------------------------------------------
36 */
37 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
38 mrs x0, sctlr_el3
39 orr x0, x0, x1
40 msr sctlr_el3, x0
41 isb
42
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090043#ifdef IMAGE_BL31
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010044 /* ---------------------------------------------------------------------
45 * Initialise the per-cpu cache pointer to the CPU.
46 * This is done early to enable crash reporting to have access to crash
47 * stack. Since crash reporting depends on cpu_data to report the
48 * unhandled exception, not doing so can lead to recursive exceptions
49 * due to a NULL TPIDR_EL3.
50 * ---------------------------------------------------------------------
51 */
52 bl init_cpu_data_ptr
53#endif /* IMAGE_BL31 */
54
55 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010056 * Initialise SCR_EL3, setting all fields rather than relying on hw.
57 * All fields are architecturally UNKNOWN on reset. The following fields
58 * do not change during the TF lifetime. The remaining fields are set to
59 * zero here but are updated ahead of transitioning to a lower EL in the
60 * function cm_init_context_common().
61 *
David Cunadofee86532017-04-13 22:38:29 +010062 * SCR_EL3.SIF: Set to one to disable instruction fetches from
63 * Non-secure memory.
64 *
David Cunadofee86532017-04-13 22:38:29 +010065 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
66 * to EL3 when executing at any EL.
Manish Pandey71af7f12024-01-29 21:17:33 +000067 *
68 * SCR_EL3.EEL2: Set to one if S-EL2 is present and enabled.
69 *
70 * NOTE: Modifying EEL2 bit along with EA bit ensures that we mitigate
71 * against ERRATA_V2_3099206.
Gerald Lejeune632d6df2016-03-22 09:29:23 +010072 * ---------------------------------------------------------------------
73 */
Boyan Karatotev8ae58f02023-04-20 11:00:50 +010074 mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT)
Manish Pandey71af7f12024-01-29 21:17:33 +000075#if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
76 mrs x1, id_aa64pfr0_el1
77 and x1, x1, #(ID_AA64PFR0_SEL2_MASK << ID_AA64PFR0_SEL2_SHIFT)
78 cbz x1, 1f
79 orr x0, x0, #SCR_EEL2_BIT
80#endif
811:
Gerald Lejeune632d6df2016-03-22 09:29:23 +010082 msr scr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +000083
84 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010085 * Initialise MDCR_EL3, setting all fields rather than relying on hw.
86 * Some fields are architecturally UNKNOWN on reset.
87 *
88 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
89 * Debug exceptions, other than Breakpoint Instruction exceptions, are
90 * disabled from all ELs in Secure state.
91 *
92 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
93 * privileged debug from S-EL1.
94 *
95 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
96 * access to the powerdown debug registers do not trap to EL3.
97 *
98 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
99 * debug registers, other than those registers that are controlled by
100 * MDCR_EL3.TDOSA.
David Cunado5f55e282016-10-31 17:37:34 +0000101 */
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000102 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000103 MDCR_SPD32(MDCR_SPD32_DISABLE)) & \
Boyan Karatotev919d3c82023-02-13 16:32:47 +0000104 ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT))
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000105
dp-arm595d0d52017-02-08 11:51:50 +0000106 msr mdcr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +0000107
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100108 /* ---------------------------------------------------------------------
109 * Enable External Aborts and SError Interrupts now that the exception
110 * vectors have been setup.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100111 * ---------------------------------------------------------------------
112 */
113 msr daifclr, #DAIF_ABT_BIT
114
115 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100116 * Initialise CPTR_EL3, setting all fields rather than relying on hw.
117 * All fields are architecturally UNKNOWN on reset.
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100118 * ---------------------------------------------------------------------
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100119 */
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100120 mov_imm x0, CPTR_EL3_RESET_VAL
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100121 msr cptr_el3, x0
Sathees Balya0911df12018-12-06 13:33:24 +0000122
123 /*
124 * If Data Independent Timing (DIT) functionality is implemented,
Daniel Boulby928747f2021-05-25 18:09:34 +0100125 * always enable DIT in EL3.
126 * First assert that the FEAT_DIT build flag matches the feature id
127 * register value for DIT.
Sathees Balya0911df12018-12-06 13:33:24 +0000128 */
Daniel Boulby928747f2021-05-25 18:09:34 +0100129#if ENABLE_FEAT_DIT
Andre Przywara1f55c412023-01-26 16:47:52 +0000130#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1
Sathees Balya0911df12018-12-06 13:33:24 +0000131 mrs x0, id_aa64pfr0_el1
132 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
Andre Przywara1f55c412023-01-26 16:47:52 +0000133#if ENABLE_FEAT_DIT > 1
134 cbz x0, 1f
135#else
Sathees Balya0911df12018-12-06 13:33:24 +0000136 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
Daniel Boulby928747f2021-05-25 18:09:34 +0100137 ASM_ASSERT(eq)
Andre Przywara1f55c412023-01-26 16:47:52 +0000138#endif
139
Daniel Boulby928747f2021-05-25 18:09:34 +0100140#endif /* ENABLE_ASSERTIONS */
Sathees Balya0911df12018-12-06 13:33:24 +0000141 mov x0, #DIT_BIT
142 msr DIT, x0
Andre Przywara1f55c412023-01-26 16:47:52 +00001431:
Daniel Boulby928747f2021-05-25 18:09:34 +0100144#endif
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100145 .endm
146
147/* -----------------------------------------------------------------------------
148 * This is the super set of actions that need to be performed during a cold boot
Juan Castillo7d199412015-12-14 09:35:25 +0000149 * or a warm boot in EL3. This code is shared by BL1 and BL31.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100150 *
151 * This macro will always perform reset handling, architectural initialisations
152 * and stack setup. The rest of the actions are optional because they might not
153 * be needed, depending on the context in which this macro is called. This is
154 * why this macro is parameterised ; each parameter allows to enable/disable
155 * some actions.
156 *
David Cunadofee86532017-04-13 22:38:29 +0100157 * _init_sctlr:
158 * Whether the macro needs to initialise SCTLR_EL3, including configuring
159 * the endianness of data accesses.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100160 *
161 * _warm_boot_mailbox:
162 * Whether the macro needs to detect the type of boot (cold/warm). The
163 * detection is based on the platform entrypoint address : if it is zero
164 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
165 * this macro jumps on the platform entrypoint address.
166 *
167 * _secondary_cold_boot:
168 * Whether the macro needs to identify the CPU that is calling it: primary
169 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
170 * the platform initialisations, while the secondaries will be put in a
171 * platform-specific state in the meantime.
172 *
173 * If the caller knows this macro will only be called by the primary CPU
174 * then this parameter can be defined to 0 to skip this step.
175 *
176 * _init_memory:
177 * Whether the macro needs to initialise the memory.
178 *
179 * _init_c_runtime:
180 * Whether the macro needs to initialise the C runtime environment.
181 *
182 * _exception_vectors:
183 * Address of the exception vectors to program in the VBAR_EL3 register.
Manish Pandeyc8257682019-11-26 11:34:17 +0000184 *
185 * _pie_fixup_size:
186 * Size of memory region to fixup Global Descriptor Table (GDT).
187 *
188 * A non-zero value is expected when firmware needs GDT to be fixed-up.
189 *
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100190 * -----------------------------------------------------------------------------
191 */
192 .macro el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100193 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
Manish Pandeyc8257682019-11-26 11:34:17 +0000194 _init_memory, _init_c_runtime, _exception_vectors, \
195 _pie_fixup_size
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100196
David Cunadofee86532017-04-13 22:38:29 +0100197 .if \_init_sctlr
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100198 /* -------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100199 * This is the initialisation of SCTLR_EL3 and so must ensure
200 * that all fields are explicitly set rather than relying on hw.
201 * Some fields reset to an IMPLEMENTATION DEFINED value and
202 * others are architecturally UNKNOWN on reset.
203 *
204 * SCTLR.EE: Set the CPU endianness before doing anything that
205 * might involve memory reads or writes. Set to zero to select
206 * Little Endian.
207 *
208 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can
209 * force all memory regions that are writeable to be treated as
210 * XN (Execute-never). Set to zero so that this control has no
211 * effect on memory access permissions.
212 *
Qixiang Xu3cc39172018-03-05 09:31:11 +0800213 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
David Cunadofee86532017-04-13 22:38:29 +0100214 *
215 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000216 *
217 * SCTLR.DSSBS: Set to zero to disable speculation store bypass
218 * safe behaviour upon exception entry to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100219 * -------------------------------------------------------------
220 */
David Cunadofee86532017-04-13 22:38:29 +0100221 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000222 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
Manish Pandey514a3012023-10-10 13:53:25 +0100223#if ENABLE_FEAT_RAS
Manish Pandey6b5721f2023-06-26 17:46:14 +0100224 /* If FEAT_RAS is present assume FEAT_IESB is also present */
225 orr x0, x0, #SCTLR_IESB_BIT
226#endif
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100227 msr sctlr_el3, x0
228 isb
David Cunadofee86532017-04-13 22:38:29 +0100229 .endif /* _init_sctlr */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100230
231 .if \_warm_boot_mailbox
232 /* -------------------------------------------------------------
233 * This code will be executed for both warm and cold resets.
234 * Now is the time to distinguish between the two.
235 * Query the platform entrypoint address and if it is not zero
236 * then it means it is a warm boot so jump to this address.
237 * -------------------------------------------------------------
238 */
Soby Mathew3700a922015-07-13 11:21:11 +0100239 bl plat_get_my_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100240 cbz x0, do_cold_boot
241 br x0
242
243 do_cold_boot:
244 .endif /* _warm_boot_mailbox */
245
Manish Pandeyc8257682019-11-26 11:34:17 +0000246 .if \_pie_fixup_size
247#if ENABLE_PIE
248 /*
249 * ------------------------------------------------------------
250 * If PIE is enabled fixup the Global descriptor Table only
251 * once during primary core cold boot path.
252 *
253 * Compile time base address, required for fixup, is calculated
254 * using "pie_fixup" label present within first page.
255 * ------------------------------------------------------------
256 */
257 pie_fixup:
258 ldr x0, =pie_fixup
Jimmy Brissoned202072020-08-04 16:18:52 -0500259 and x0, x0, #~(PAGE_SIZE_MASK)
Manish Pandeyc8257682019-11-26 11:34:17 +0000260 mov_imm x1, \_pie_fixup_size
261 add x1, x1, x0
262 bl fixup_gdt_reloc
263#endif /* ENABLE_PIE */
264 .endif /* _pie_fixup_size */
265
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000266 /* ---------------------------------------------------------------------
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000267 * Set the exception vectors.
268 * ---------------------------------------------------------------------
269 */
270 adr x0, \_exception_vectors
271 msr vbar_el3, x0
272 isb
273
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500274#if !(defined(IMAGE_BL2) && ENABLE_RME)
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000275 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000276 * It is a cold boot.
277 * Perform any processor specific actions upon reset e.g. cache, TLB
278 * invalidations etc.
279 * ---------------------------------------------------------------------
280 */
281 bl reset_handler
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500282#endif
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000283
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000284 el3_arch_init_common
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000285
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100286 .if \_secondary_cold_boot
287 /* -------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000288 * Check if this is a primary or secondary CPU cold boot.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100289 * The primary CPU will set up the platform while the
290 * secondaries are placed in a platform-specific state until the
291 * primary CPU performs the necessary actions to bring them out
292 * of that state and allows entry into the OS.
293 * -------------------------------------------------------------
294 */
Soby Mathew3700a922015-07-13 11:21:11 +0100295 bl plat_is_my_cpu_primary
Soby Matheweb3bbf12015-06-08 12:32:50 +0100296 cbnz w0, do_primary_cold_boot
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100297
298 /* This is a cold boot on a secondary CPU */
299 bl plat_secondary_cold_boot_setup
300 /* plat_secondary_cold_boot_setup() is not supposed to return */
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000301 bl el3_panic
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100302
303 do_primary_cold_boot:
304 .endif /* _secondary_cold_boot */
305
306 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000307 * Initialize memory now. Secondary CPU initialization won't get to this
308 * point.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100309 * ---------------------------------------------------------------------
310 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100311
312 .if \_init_memory
313 bl platform_mem_init
314 .endif /* _init_memory */
315
316 /* ---------------------------------------------------------------------
317 * Init C runtime environment:
318 * - Zero-initialise the NOBITS sections. There are 2 of them:
319 * - the .bss section;
320 * - the coherent memory section (if any).
321 * - Relocate the data section from ROM to RAM, if required.
322 * ---------------------------------------------------------------------
323 */
324 .if \_init_c_runtime
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500325#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600326 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME))
Achin Guptae9c4a642015-09-11 16:03:13 +0100327 /* -------------------------------------------------------------
328 * Invalidate the RW memory used by the BL31 image. This
329 * includes the data and NOBITS sections. This is done to
330 * safeguard against possible corruption of this memory by
331 * dirty cache lines in a system cache as a result of use by
Zelalem Awekeb0d69e82021-10-15 17:25:52 -0500332 * an earlier boot loader stage. If PIE is enabled however,
333 * RO sections including the GOT may be modified during
334 * pie fixup. Therefore, to be on the safe side, invalidate
335 * the entire image region if PIE is enabled.
Achin Guptae9c4a642015-09-11 16:03:13 +0100336 * -------------------------------------------------------------
337 */
Zelalem Awekeb0d69e82021-10-15 17:25:52 -0500338#if ENABLE_PIE
339#if SEPARATE_CODE_AND_RODATA
340 adrp x0, __TEXT_START__
341 add x0, x0, :lo12:__TEXT_START__
342#else
343 adrp x0, __RO_START__
344 add x0, x0, :lo12:__RO_START__
345#endif /* SEPARATE_CODE_AND_RODATA */
346#else
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100347 adrp x0, __RW_START__
348 add x0, x0, :lo12:__RW_START__
Zelalem Awekeb0d69e82021-10-15 17:25:52 -0500349#endif /* ENABLE_PIE */
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100350 adrp x1, __RW_END__
351 add x1, x1, :lo12:__RW_END__
Achin Guptae9c4a642015-09-11 16:03:13 +0100352 sub x1, x1, x0
353 bl inv_dcache_range
Samuel Holland31a14e12018-10-17 21:40:18 -0500354#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION
355 adrp x0, __NOBITS_START__
356 add x0, x0, :lo12:__NOBITS_START__
357 adrp x1, __NOBITS_END__
358 add x1, x1, :lo12:__NOBITS_END__
359 sub x1, x1, x0
360 bl inv_dcache_range
361#endif
Jiafei Pan0824b452022-02-24 10:47:33 +0800362#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION
363 adrp x0, __BL2_NOLOAD_START__
364 add x0, x0, :lo12:__BL2_NOLOAD_START__
365 adrp x1, __BL2_NOLOAD_END__
366 add x1, x1, :lo12:__BL2_NOLOAD_END__
367 sub x1, x1, x0
368 bl inv_dcache_range
369#endif
Roberto Vargase0e99462017-10-30 14:43:43 +0000370#endif
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100371 adrp x0, __BSS_START__
372 add x0, x0, :lo12:__BSS_START__
Achin Guptae9c4a642015-09-11 16:03:13 +0100373
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100374 adrp x1, __BSS_END__
375 add x1, x1, :lo12:__BSS_END__
376 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +0000377 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100378
379#if USE_COHERENT_MEM
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100380 adrp x0, __COHERENT_RAM_START__
381 add x0, x0, :lo12:__COHERENT_RAM_START__
382 adrp x1, __COHERENT_RAM_END_UNALIGNED__
383 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
384 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +0000385 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100386#endif
387
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600388#if defined(IMAGE_BL1) || \
389 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM)
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100390 adrp x0, __DATA_RAM_START__
391 add x0, x0, :lo12:__DATA_RAM_START__
392 adrp x1, __DATA_ROM_START__
393 add x1, x1, :lo12:__DATA_ROM_START__
394 adrp x2, __DATA_RAM_END__
395 add x2, x2, :lo12:__DATA_RAM_END__
396 sub x2, x2, x0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100397 bl memcpy16
398#endif
399 .endif /* _init_c_runtime */
400
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100401 /* ---------------------------------------------------------------------
402 * Use SP_EL0 for the C runtime stack.
403 * ---------------------------------------------------------------------
404 */
405 msr spsel, #0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100406
407 /* ---------------------------------------------------------------------
408 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
409 * the MMU is enabled. There is no risk of reading stale stack memory
410 * after enabling the MMU as only the primary CPU is running at the
411 * moment.
412 * ---------------------------------------------------------------------
413 */
Soby Mathew3700a922015-07-13 11:21:11 +0100414 bl plat_set_my_stack
Douglas Raillard306593d2017-02-24 18:14:15 +0000415
416#if STACK_PROTECTOR_ENABLED
417 .if \_init_c_runtime
418 bl update_stack_protector_canary
419 .endif /* _init_c_runtime */
420#endif
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100421 .endm
422
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100423 .macro apply_at_speculative_wa
424#if ERRATA_SPECULATIVE_AT
425 /*
Manish Pandey66a056e2023-01-11 21:41:07 +0000426 * This function expects x30 has been saved.
427 * Also, save x29 which will be used in the called function.
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100428 */
Manish Pandey66a056e2023-01-11 21:41:07 +0000429 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100430 bl save_and_update_ptw_el1_sys_regs
Manish Pandey66a056e2023-01-11 21:41:07 +0000431 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100432#endif
433 .endm
434
435 .macro restore_ptw_el1_sys_regs
436#if ERRATA_SPECULATIVE_AT
437 /* -----------------------------------------------------------
438 * In case of ERRATA_SPECULATIVE_AT, must follow below order
439 * to ensure that page table walk is not enabled until
440 * restoration of all EL1 system registers. TCR_EL1 register
441 * should be updated at the end which restores previous page
442 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB
443 * ensures that CPU does below steps in order.
444 *
445 * 1. Ensure all other system registers are written before
446 * updating SCTLR_EL1 using ISB.
447 * 2. Restore SCTLR_EL1 register.
448 * 3. Ensure SCTLR_EL1 written successfully using ISB.
449 * 4. Restore TCR_EL1 register.
450 * -----------------------------------------------------------
451 */
452 isb
453 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1]
454 msr sctlr_el1, x28
455 isb
456 msr tcr_el1, x29
457#endif
458 .endm
459
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100460/* -----------------------------------------------------------------
461 * The below macro reads SCR_EL3 from the context structure to
462 * determine the security state of the context upon ERET.
463 * ------------------------------------------------------------------
464 */
465 .macro get_security_state _ret:req, _scr_reg:req
466 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1
467 cmp \_ret, #1
468 beq realm_state
469 bfi \_ret, \_scr_reg, #0, #1
470 b end
471 realm_state:
472 mov \_ret, #2
473 end:
474 .endm
475
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000476#endif /* EL3_COMMON_MACROS_S */