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Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01001/*
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -06002 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef EL3_COMMON_MACROS_S
8#define EL3_COMMON_MACROS_S
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01009
10#include <arch.h>
11#include <asm_macros.S>
Daniel Boulby928747f2021-05-25 18:09:34 +010012#include <assert_macros.S>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010013#include <context.h>
Varun Wadekar5dc9e9c2020-05-16 20:59:30 -070014#include <lib/xlat_tables/xlat_tables_defs.h>
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010015
16 /*
17 * Helper macro to initialise EL3 registers we care about.
18 */
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000019 .macro el3_arch_init_common
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010020 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010021 * SCTLR_EL3 has already been initialised - read current value before
22 * modifying.
23 *
24 * SCTLR_EL3.I: Enable the instruction cache.
25 *
Qixiang Xu3cc39172018-03-05 09:31:11 +080026 * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
David Cunadofee86532017-04-13 22:38:29 +010027 * exception is generated if a load or store instruction executed at
28 * EL3 uses the SP as the base address and the SP is not aligned to a
29 * 16-byte boundary.
30 *
31 * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
32 * load or store one or more registers have an alignment check that the
33 * address being accessed is aligned to the size of the data element(s)
34 * being accessed.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010035 * ---------------------------------------------------------------------
36 */
37 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
38 mrs x0, sctlr_el3
39 orr x0, x0, x1
40 msr sctlr_el3, x0
41 isb
42
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090043#ifdef IMAGE_BL31
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010044 /* ---------------------------------------------------------------------
45 * Initialise the per-cpu cache pointer to the CPU.
46 * This is done early to enable crash reporting to have access to crash
47 * stack. Since crash reporting depends on cpu_data to report the
48 * unhandled exception, not doing so can lead to recursive exceptions
49 * due to a NULL TPIDR_EL3.
50 * ---------------------------------------------------------------------
51 */
52 bl init_cpu_data_ptr
53#endif /* IMAGE_BL31 */
54
55 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010056 * Initialise SCR_EL3, setting all fields rather than relying on hw.
57 * All fields are architecturally UNKNOWN on reset. The following fields
58 * do not change during the TF lifetime. The remaining fields are set to
59 * zero here but are updated ahead of transitioning to a lower EL in the
60 * function cm_init_context_common().
61 *
David Cunadofee86532017-04-13 22:38:29 +010062 * SCR_EL3.SIF: Set to one to disable instruction fetches from
63 * Non-secure memory.
64 *
David Cunadofee86532017-04-13 22:38:29 +010065 * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
66 * to EL3 when executing at any EL.
Gerald Lejeune632d6df2016-03-22 09:29:23 +010067 * ---------------------------------------------------------------------
68 */
Boyan Karatotev8ae58f02023-04-20 11:00:50 +010069 mov_imm x0, (SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT)
Gerald Lejeune632d6df2016-03-22 09:29:23 +010070 msr scr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +000071
72 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +010073 * Initialise MDCR_EL3, setting all fields rather than relying on hw.
74 * Some fields are architecturally UNKNOWN on reset.
75 *
76 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
77 * Debug exceptions, other than Breakpoint Instruction exceptions, are
78 * disabled from all ELs in Secure state.
79 *
80 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
81 * privileged debug from S-EL1.
82 *
83 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
84 * access to the powerdown debug registers do not trap to EL3.
85 *
86 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
87 * debug registers, other than those registers that are controlled by
88 * MDCR_EL3.TDOSA.
David Cunado5f55e282016-10-31 17:37:34 +000089 */
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +000090 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
Boyan Karatotev05504ba2023-02-15 13:21:50 +000091 MDCR_SPD32(MDCR_SPD32_DISABLE)) & \
Boyan Karatotev919d3c82023-02-13 16:32:47 +000092 ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT))
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +000093
dp-arm595d0d52017-02-08 11:51:50 +000094 msr mdcr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +000095
Gerald Lejeune632d6df2016-03-22 09:29:23 +010096 /* ---------------------------------------------------------------------
97 * Enable External Aborts and SError Interrupts now that the exception
98 * vectors have been setup.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010099 * ---------------------------------------------------------------------
100 */
101 msr daifclr, #DAIF_ABT_BIT
102
103 /* ---------------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100104 * Initialise CPTR_EL3, setting all fields rather than relying on hw.
105 * All fields are architecturally UNKNOWN on reset.
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100106 * ---------------------------------------------------------------------
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100107 */
Boyan Karatotev8ae58f02023-04-20 11:00:50 +0100108 mov_imm x0, CPTR_EL3_RESET_VAL
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100109 msr cptr_el3, x0
Sathees Balya0911df12018-12-06 13:33:24 +0000110
111 /*
112 * If Data Independent Timing (DIT) functionality is implemented,
Daniel Boulby928747f2021-05-25 18:09:34 +0100113 * always enable DIT in EL3.
114 * First assert that the FEAT_DIT build flag matches the feature id
115 * register value for DIT.
Sathees Balya0911df12018-12-06 13:33:24 +0000116 */
Daniel Boulby928747f2021-05-25 18:09:34 +0100117#if ENABLE_FEAT_DIT
Andre Przywara1f55c412023-01-26 16:47:52 +0000118#if ENABLE_ASSERTIONS || ENABLE_FEAT_DIT > 1
Sathees Balya0911df12018-12-06 13:33:24 +0000119 mrs x0, id_aa64pfr0_el1
120 ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
Andre Przywara1f55c412023-01-26 16:47:52 +0000121#if ENABLE_FEAT_DIT > 1
122 cbz x0, 1f
123#else
Sathees Balya0911df12018-12-06 13:33:24 +0000124 cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
Daniel Boulby928747f2021-05-25 18:09:34 +0100125 ASM_ASSERT(eq)
Andre Przywara1f55c412023-01-26 16:47:52 +0000126#endif
127
Daniel Boulby928747f2021-05-25 18:09:34 +0100128#endif /* ENABLE_ASSERTIONS */
Sathees Balya0911df12018-12-06 13:33:24 +0000129 mov x0, #DIT_BIT
130 msr DIT, x0
Andre Przywara1f55c412023-01-26 16:47:52 +00001311:
Daniel Boulby928747f2021-05-25 18:09:34 +0100132#endif
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100133 .endm
134
135/* -----------------------------------------------------------------------------
136 * This is the super set of actions that need to be performed during a cold boot
Juan Castillo7d199412015-12-14 09:35:25 +0000137 * or a warm boot in EL3. This code is shared by BL1 and BL31.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100138 *
139 * This macro will always perform reset handling, architectural initialisations
140 * and stack setup. The rest of the actions are optional because they might not
141 * be needed, depending on the context in which this macro is called. This is
142 * why this macro is parameterised ; each parameter allows to enable/disable
143 * some actions.
144 *
David Cunadofee86532017-04-13 22:38:29 +0100145 * _init_sctlr:
146 * Whether the macro needs to initialise SCTLR_EL3, including configuring
147 * the endianness of data accesses.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100148 *
149 * _warm_boot_mailbox:
150 * Whether the macro needs to detect the type of boot (cold/warm). The
151 * detection is based on the platform entrypoint address : if it is zero
152 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
153 * this macro jumps on the platform entrypoint address.
154 *
155 * _secondary_cold_boot:
156 * Whether the macro needs to identify the CPU that is calling it: primary
157 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
158 * the platform initialisations, while the secondaries will be put in a
159 * platform-specific state in the meantime.
160 *
161 * If the caller knows this macro will only be called by the primary CPU
162 * then this parameter can be defined to 0 to skip this step.
163 *
164 * _init_memory:
165 * Whether the macro needs to initialise the memory.
166 *
167 * _init_c_runtime:
168 * Whether the macro needs to initialise the C runtime environment.
169 *
170 * _exception_vectors:
171 * Address of the exception vectors to program in the VBAR_EL3 register.
Manish Pandeyc8257682019-11-26 11:34:17 +0000172 *
173 * _pie_fixup_size:
174 * Size of memory region to fixup Global Descriptor Table (GDT).
175 *
176 * A non-zero value is expected when firmware needs GDT to be fixed-up.
177 *
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100178 * -----------------------------------------------------------------------------
179 */
180 .macro el3_entrypoint_common \
David Cunadofee86532017-04-13 22:38:29 +0100181 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
Manish Pandeyc8257682019-11-26 11:34:17 +0000182 _init_memory, _init_c_runtime, _exception_vectors, \
183 _pie_fixup_size
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100184
David Cunadofee86532017-04-13 22:38:29 +0100185 .if \_init_sctlr
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100186 /* -------------------------------------------------------------
David Cunadofee86532017-04-13 22:38:29 +0100187 * This is the initialisation of SCTLR_EL3 and so must ensure
188 * that all fields are explicitly set rather than relying on hw.
189 * Some fields reset to an IMPLEMENTATION DEFINED value and
190 * others are architecturally UNKNOWN on reset.
191 *
192 * SCTLR.EE: Set the CPU endianness before doing anything that
193 * might involve memory reads or writes. Set to zero to select
194 * Little Endian.
195 *
196 * SCTLR_EL3.WXN: For the EL3 translation regime, this field can
197 * force all memory regions that are writeable to be treated as
198 * XN (Execute-never). Set to zero so that this control has no
199 * effect on memory access permissions.
200 *
Qixiang Xu3cc39172018-03-05 09:31:11 +0800201 * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
David Cunadofee86532017-04-13 22:38:29 +0100202 *
203 * SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000204 *
205 * SCTLR.DSSBS: Set to zero to disable speculation store bypass
206 * safe behaviour upon exception entry to EL3.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100207 * -------------------------------------------------------------
208 */
David Cunadofee86532017-04-13 22:38:29 +0100209 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000210 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100211 msr sctlr_el3, x0
212 isb
David Cunadofee86532017-04-13 22:38:29 +0100213 .endif /* _init_sctlr */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100214
215 .if \_warm_boot_mailbox
216 /* -------------------------------------------------------------
217 * This code will be executed for both warm and cold resets.
218 * Now is the time to distinguish between the two.
219 * Query the platform entrypoint address and if it is not zero
220 * then it means it is a warm boot so jump to this address.
221 * -------------------------------------------------------------
222 */
Soby Mathew3700a922015-07-13 11:21:11 +0100223 bl plat_get_my_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100224 cbz x0, do_cold_boot
225 br x0
226
227 do_cold_boot:
228 .endif /* _warm_boot_mailbox */
229
Manish Pandeyc8257682019-11-26 11:34:17 +0000230 .if \_pie_fixup_size
231#if ENABLE_PIE
232 /*
233 * ------------------------------------------------------------
234 * If PIE is enabled fixup the Global descriptor Table only
235 * once during primary core cold boot path.
236 *
237 * Compile time base address, required for fixup, is calculated
238 * using "pie_fixup" label present within first page.
239 * ------------------------------------------------------------
240 */
241 pie_fixup:
242 ldr x0, =pie_fixup
Jimmy Brissoned202072020-08-04 16:18:52 -0500243 and x0, x0, #~(PAGE_SIZE_MASK)
Manish Pandeyc8257682019-11-26 11:34:17 +0000244 mov_imm x1, \_pie_fixup_size
245 add x1, x1, x0
246 bl fixup_gdt_reloc
247#endif /* ENABLE_PIE */
248 .endif /* _pie_fixup_size */
249
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000250 /* ---------------------------------------------------------------------
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000251 * Set the exception vectors.
252 * ---------------------------------------------------------------------
253 */
254 adr x0, \_exception_vectors
255 msr vbar_el3, x0
256 isb
257
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500258#if !(defined(IMAGE_BL2) && ENABLE_RME)
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000259 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000260 * It is a cold boot.
261 * Perform any processor specific actions upon reset e.g. cache, TLB
262 * invalidations etc.
263 * ---------------------------------------------------------------------
264 */
265 bl reset_handler
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500266#endif
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000267
Dimitris Papastamos446f7f12017-11-30 14:53:53 +0000268 el3_arch_init_common
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000269
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100270 .if \_secondary_cold_boot
271 /* -------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000272 * Check if this is a primary or secondary CPU cold boot.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100273 * The primary CPU will set up the platform while the
274 * secondaries are placed in a platform-specific state until the
275 * primary CPU performs the necessary actions to bring them out
276 * of that state and allows entry into the OS.
277 * -------------------------------------------------------------
278 */
Soby Mathew3700a922015-07-13 11:21:11 +0100279 bl plat_is_my_cpu_primary
Soby Matheweb3bbf12015-06-08 12:32:50 +0100280 cbnz w0, do_primary_cold_boot
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100281
282 /* This is a cold boot on a secondary CPU */
283 bl plat_secondary_cold_boot_setup
284 /* plat_secondary_cold_boot_setup() is not supposed to return */
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000285 bl el3_panic
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100286
287 do_primary_cold_boot:
288 .endif /* _secondary_cold_boot */
289
290 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000291 * Initialize memory now. Secondary CPU initialization won't get to this
292 * point.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100293 * ---------------------------------------------------------------------
294 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100295
296 .if \_init_memory
297 bl platform_mem_init
298 .endif /* _init_memory */
299
300 /* ---------------------------------------------------------------------
301 * Init C runtime environment:
302 * - Zero-initialise the NOBITS sections. There are 2 of them:
303 * - the .bss section;
304 * - the coherent memory section (if any).
305 * - Relocate the data section from ROM to RAM, if required.
306 * ---------------------------------------------------------------------
307 */
308 .if \_init_c_runtime
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500309#if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600310 ((RESET_TO_BL2 && BL2_INV_DCACHE) || ENABLE_RME))
Achin Guptae9c4a642015-09-11 16:03:13 +0100311 /* -------------------------------------------------------------
312 * Invalidate the RW memory used by the BL31 image. This
313 * includes the data and NOBITS sections. This is done to
314 * safeguard against possible corruption of this memory by
315 * dirty cache lines in a system cache as a result of use by
Zelalem Awekeb0d69e82021-10-15 17:25:52 -0500316 * an earlier boot loader stage. If PIE is enabled however,
317 * RO sections including the GOT may be modified during
318 * pie fixup. Therefore, to be on the safe side, invalidate
319 * the entire image region if PIE is enabled.
Achin Guptae9c4a642015-09-11 16:03:13 +0100320 * -------------------------------------------------------------
321 */
Zelalem Awekeb0d69e82021-10-15 17:25:52 -0500322#if ENABLE_PIE
323#if SEPARATE_CODE_AND_RODATA
324 adrp x0, __TEXT_START__
325 add x0, x0, :lo12:__TEXT_START__
326#else
327 adrp x0, __RO_START__
328 add x0, x0, :lo12:__RO_START__
329#endif /* SEPARATE_CODE_AND_RODATA */
330#else
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100331 adrp x0, __RW_START__
332 add x0, x0, :lo12:__RW_START__
Zelalem Awekeb0d69e82021-10-15 17:25:52 -0500333#endif /* ENABLE_PIE */
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100334 adrp x1, __RW_END__
335 add x1, x1, :lo12:__RW_END__
Achin Guptae9c4a642015-09-11 16:03:13 +0100336 sub x1, x1, x0
337 bl inv_dcache_range
Samuel Holland31a14e12018-10-17 21:40:18 -0500338#if defined(IMAGE_BL31) && SEPARATE_NOBITS_REGION
339 adrp x0, __NOBITS_START__
340 add x0, x0, :lo12:__NOBITS_START__
341 adrp x1, __NOBITS_END__
342 add x1, x1, :lo12:__NOBITS_END__
343 sub x1, x1, x0
344 bl inv_dcache_range
345#endif
Jiafei Pan0824b452022-02-24 10:47:33 +0800346#if defined(IMAGE_BL2) && SEPARATE_BL2_NOLOAD_REGION
347 adrp x0, __BL2_NOLOAD_START__
348 add x0, x0, :lo12:__BL2_NOLOAD_START__
349 adrp x1, __BL2_NOLOAD_END__
350 add x1, x1, :lo12:__BL2_NOLOAD_END__
351 sub x1, x1, x0
352 bl inv_dcache_range
353#endif
Roberto Vargase0e99462017-10-30 14:43:43 +0000354#endif
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100355 adrp x0, __BSS_START__
356 add x0, x0, :lo12:__BSS_START__
Achin Guptae9c4a642015-09-11 16:03:13 +0100357
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100358 adrp x1, __BSS_END__
359 add x1, x1, :lo12:__BSS_END__
360 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +0000361 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100362
363#if USE_COHERENT_MEM
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100364 adrp x0, __COHERENT_RAM_START__
365 add x0, x0, :lo12:__COHERENT_RAM_START__
366 adrp x1, __COHERENT_RAM_END_UNALIGNED__
367 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
368 sub x1, x1, x0
Douglas Raillard21362a92016-12-02 13:51:54 +0000369 bl zeromem
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100370#endif
371
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600372#if defined(IMAGE_BL1) || \
373 (defined(IMAGE_BL2) && RESET_TO_BL2 && BL2_IN_XIP_MEM)
Soby Mathewfcaf1bd2018-10-12 16:40:28 +0100374 adrp x0, __DATA_RAM_START__
375 add x0, x0, :lo12:__DATA_RAM_START__
376 adrp x1, __DATA_ROM_START__
377 add x1, x1, :lo12:__DATA_ROM_START__
378 adrp x2, __DATA_RAM_END__
379 add x2, x2, :lo12:__DATA_RAM_END__
380 sub x2, x2, x0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100381 bl memcpy16
382#endif
383 .endif /* _init_c_runtime */
384
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100385 /* ---------------------------------------------------------------------
386 * Use SP_EL0 for the C runtime stack.
387 * ---------------------------------------------------------------------
388 */
389 msr spsel, #0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100390
391 /* ---------------------------------------------------------------------
392 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
393 * the MMU is enabled. There is no risk of reading stale stack memory
394 * after enabling the MMU as only the primary CPU is running at the
395 * moment.
396 * ---------------------------------------------------------------------
397 */
Soby Mathew3700a922015-07-13 11:21:11 +0100398 bl plat_set_my_stack
Douglas Raillard306593d2017-02-24 18:14:15 +0000399
400#if STACK_PROTECTOR_ENABLED
401 .if \_init_c_runtime
402 bl update_stack_protector_canary
403 .endif /* _init_c_runtime */
404#endif
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100405 .endm
406
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100407 .macro apply_at_speculative_wa
408#if ERRATA_SPECULATIVE_AT
409 /*
Manish Pandey66a056e2023-01-11 21:41:07 +0000410 * This function expects x30 has been saved.
411 * Also, save x29 which will be used in the called function.
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100412 */
Manish Pandey66a056e2023-01-11 21:41:07 +0000413 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100414 bl save_and_update_ptw_el1_sys_regs
Manish Pandey66a056e2023-01-11 21:41:07 +0000415 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100416#endif
417 .endm
418
419 .macro restore_ptw_el1_sys_regs
420#if ERRATA_SPECULATIVE_AT
421 /* -----------------------------------------------------------
422 * In case of ERRATA_SPECULATIVE_AT, must follow below order
423 * to ensure that page table walk is not enabled until
424 * restoration of all EL1 system registers. TCR_EL1 register
425 * should be updated at the end which restores previous page
426 * table walk setting of stage1 i.e.(TCR_EL1.EPDx) bits. ISB
427 * ensures that CPU does below steps in order.
428 *
429 * 1. Ensure all other system registers are written before
430 * updating SCTLR_EL1 using ISB.
431 * 2. Restore SCTLR_EL1 register.
432 * 3. Ensure SCTLR_EL1 written successfully using ISB.
433 * 4. Restore TCR_EL1 register.
434 * -----------------------------------------------------------
435 */
436 isb
437 ldp x28, x29, [sp, #CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1]
438 msr sctlr_el1, x28
439 isb
440 msr tcr_el1, x29
441#endif
442 .endm
443
Elizabeth Ho4fc00d22023-07-18 14:10:25 +0100444/* -----------------------------------------------------------------
445 * The below macro reads SCR_EL3 from the context structure to
446 * determine the security state of the context upon ERET.
447 * ------------------------------------------------------------------
448 */
449 .macro get_security_state _ret:req, _scr_reg:req
450 ubfx \_ret, \_scr_reg, #SCR_NSE_SHIFT, #1
451 cmp \_ret, #1
452 beq realm_state
453 bfi \_ret, \_scr_reg, #0, #1
454 b end
455 realm_state:
456 mov \_ret, #2
457 end:
458 .endm
459
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000460#endif /* EL3_COMMON_MACROS_S */