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Dan Handley610e7e12018-03-01 18:44:00 +00001Trusted Firmware-A User Guide
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
4
5.. section-numbering::
6 :suffix: .
7
8.. contents::
9
Dan Handley610e7e12018-03-01 18:44:00 +000010This document describes how to build Trusted Firmware-A (TF-A) and run it with a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010011tested set of other software components using defined configurations on the Juno
Dan Handley610e7e12018-03-01 18:44:00 +000012Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
Douglas Raillardd7c21b72017-06-28 15:23:03 +010013possible to use other software components, configurations and platforms but that
14is outside the scope of this document.
15
16This document assumes that the reader has previous experience running a fully
17bootable Linux software stack on Juno or FVP using the prebuilt binaries and
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010018filesystems provided by `Linaro`_. Further information may be found in the
19`Linaro instructions`_. It also assumes that the user understands the role of
20the different software components required to boot a Linux system:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010021
22- Specific firmware images required by the platform (e.g. SCP firmware on Juno)
23- Normal world bootloader (e.g. UEFI or U-Boot)
24- Device tree
25- Linux kernel image
26- Root filesystem
27
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010028This document also assumes that the user is familiar with the `FVP models`_ and
Douglas Raillardd7c21b72017-06-28 15:23:03 +010029the different command line options available to launch the model.
30
31This document should be used in conjunction with the `Firmware Design`_.
32
33Host machine requirements
34-------------------------
35
36The minimum recommended machine specification for building the software and
37running the FVP models is a dual-core processor running at 2GHz with 12GB of
38RAM. For best performance, use a machine with a quad-core processor running at
392.6GHz with 16GB of RAM.
40
Joel Huttonfe027712018-03-19 11:59:57 +000041The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
Douglas Raillardd7c21b72017-06-28 15:23:03 +010042building the software were installed from that distribution unless otherwise
43specified.
44
45The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
David Cunadob2de0992017-06-29 12:01:33 +010046Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010047
48Tools
49-----
50
Dan Handley610e7e12018-03-01 18:44:00 +000051Install the required packages to build TF-A with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010052
53::
54
Sathees Balya2d0aeb02018-07-10 14:46:51 +010055 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
Douglas Raillardd7c21b72017-06-28 15:23:03 +010056
David Cunado05845bf2017-12-19 16:33:25 +000057TF-A has been tested with Linaro Release 18.04.
David Cunadob2de0992017-06-29 12:01:33 +010058
Douglas Raillardd7c21b72017-06-28 15:23:03 +010059Download and install the AArch32 or AArch64 little-endian GCC cross compiler.
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +010060The `Linaro Release Notes`_ documents which version of the compiler to use for a
61given Linaro Release. Also, these `Linaro instructions`_ provide further
62guidance and a script, which can be used to download Linaro deliverables
63automatically.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010064
Roberto Vargas0489bc02018-04-16 15:43:26 +010065Optionally, TF-A can be built using clang version 4.0 or newer or Arm
66Compiler 6. See instructions below on how to switch the default compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010067
68In addition, the following optional packages and tools may be needed:
69
Sathees Balya017a67e2018-08-17 10:22:01 +010070- ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
71 Tree (FDT) source files (``.dts`` files) provided with this software. The
72 version of dtc must be 1.4.6 or above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010073
Dan Handley610e7e12018-03-01 18:44:00 +000074- For debugging, Arm `Development Studio 5 (DS-5)`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010075
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010076- To create and modify the diagram files included in the documentation, `Dia`_.
77 This tool can be found in most Linux distributions. Inkscape is needed to
Antonio Nino Diaz80914a82018-08-08 16:28:43 +010078 generate the actual \*.png files.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010079
Dan Handley610e7e12018-03-01 18:44:00 +000080Getting the TF-A source code
81----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010082
Dan Handley610e7e12018-03-01 18:44:00 +000083Download the TF-A source code from Github:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010084
85::
86
87 git clone https://github.com/ARM-software/arm-trusted-firmware.git
88
Dan Handley610e7e12018-03-01 18:44:00 +000089Building TF-A
90-------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010091
Dan Handley610e7e12018-03-01 18:44:00 +000092- Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
93 to the Linaro cross compiler.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010094
95 For AArch64:
96
97 ::
98
99 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
100
101 For AArch32:
102
103 ::
104
105 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
106
Roberto Vargas07b1e242018-04-23 08:38:12 +0100107 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
108 ``CC`` needs to point to the clang or armclang binary, which will
109 also select the clang or armclang assembler. Be aware that the
110 GNU linker is used by default. In case of being needed the linker
111 can be overriden using the ``LD`` variable. Clang linker version 6 is
112 known to work with TF-A.
113
114 In both cases ``CROSS_COMPILE`` should be set as described above.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100115
Dan Handley610e7e12018-03-01 18:44:00 +0000116 Arm Compiler 6 will be selected when the base name of the path assigned
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100117 to ``CC`` matches the string 'armclang'.
118
Dan Handley610e7e12018-03-01 18:44:00 +0000119 For AArch64 using Arm Compiler 6:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
121 ::
122
123 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
124 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
125
126 Clang will be selected when the base name of the path assigned to ``CC``
127 contains the string 'clang'. This is to allow both clang and clang-X.Y
128 to work.
129
130 For AArch64 using clang:
131
132 ::
133
134 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
135 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
136
Dan Handley610e7e12018-03-01 18:44:00 +0000137- Change to the root directory of the TF-A source tree and build.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100138
139 For AArch64:
140
141 ::
142
143 make PLAT=<platform> all
144
145 For AArch32:
146
147 ::
148
149 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
150
151 Notes:
152
153 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
154 `Summary of build options`_ for more information on available build
155 options.
156
157 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
158
159 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
160 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
Dan Handley610e7e12018-03-01 18:44:00 +0000161 provided by TF-A to demonstrate how PSCI Library can be integrated with
162 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
163 include other runtime services, for example Trusted OS services. A guide
164 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
165 `here`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100166
167 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
168 image, is not compiled in by default. Refer to the
169 `Building the Test Secure Payload`_ section below.
170
171 - By default this produces a release version of the build. To produce a
172 debug version instead, refer to the "Debugging options" section below.
173
174 - The build process creates products in a ``build`` directory tree, building
175 the objects and binaries for each boot loader stage in separate
176 sub-directories. The following boot loader binary files are created
177 from the corresponding ELF files:
178
179 - ``build/<platform>/<build-type>/bl1.bin``
180 - ``build/<platform>/<build-type>/bl2.bin``
181 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
182 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
183
184 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
185 is either ``debug`` or ``release``. The actual number of images might differ
186 depending on the platform.
187
188- Build products for a specific build variant can be removed using:
189
190 ::
191
192 make DEBUG=<D> PLAT=<platform> clean
193
194 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
195
196 The build tree can be removed completely using:
197
198 ::
199
200 make realclean
201
202Summary of build options
203~~~~~~~~~~~~~~~~~~~~~~~~
204
Dan Handley610e7e12018-03-01 18:44:00 +0000205The TF-A build system supports the following build options. Unless mentioned
206otherwise, these options are expected to be specified at the build command
207line and are not to be modified in any component makefiles. Note that the
208build system doesn't track dependency for build options. Therefore, if any of
209the build options are changed from a previous build, a clean build must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100210performed.
211
212Common build options
213^^^^^^^^^^^^^^^^^^^^
214
Antonio Nino Diaz80914a82018-08-08 16:28:43 +0100215- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
216 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
217 code having a smaller resulting size.
218
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100219- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
220 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
221 directory containing the SP source, relative to the ``bl32/``; the directory
222 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
223
Dan Handley610e7e12018-03-01 18:44:00 +0000224- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
225 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
226 ``aarch64``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100227
Dan Handley610e7e12018-03-01 18:44:00 +0000228- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
229 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
230 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
231 `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100232
Dan Handley610e7e12018-03-01 18:44:00 +0000233- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
234 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
235 *Armv8 Architecture Extensions* in `Firmware Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100236
Dan Handley610e7e12018-03-01 18:44:00 +0000237- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000238 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
239 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
240 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
241 this flag is 0. Note that this option is not used on FVP platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243- ``BL2``: This is an optional build option which specifies the path to BL2
Dan Handley610e7e12018-03-01 18:44:00 +0000244 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
245 built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100246
247- ``BL2U``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000248 BL2U image. In this case, the BL2U in TF-A will not be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100249
John Tsichritzisee10e792018-06-06 09:38:10 +0100250- ``BL2_AT_EL3``: This is an optional build option that enables the use of
Roberto Vargasb1584272017-11-20 13:36:10 +0000251 BL2 at EL3 execution level.
252
John Tsichritzisee10e792018-06-06 09:38:10 +0100253- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000254 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
255 the RW sections in RAM, while leaving the RO sections in place. This option
256 enable this use-case. For now, this option is only supported when BL2_AT_EL3
257 is set to '1'.
258
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100259- ``BL31``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000260 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
261 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100262
263- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
264 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
265 this file name will be used to save the key.
266
267- ``BL32``: This is an optional build option which specifies the path to
Dan Handley610e7e12018-03-01 18:44:00 +0000268 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
269 be built.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100270
John Tsichritzisee10e792018-06-06 09:38:10 +0100271- ``BL32_EXTRA1``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100272 Trusted OS Extra1 image for the ``fip`` target.
273
John Tsichritzisee10e792018-06-06 09:38:10 +0100274- ``BL32_EXTRA2``: This is an optional build option which specifies the path to
Summer Qin80726782017-04-20 16:28:39 +0100275 Trusted OS Extra2 image for the ``fip`` target.
276
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100277- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
278 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
279 this file name will be used to save the key.
280
281- ``BL33``: Path to BL33 image in the host file system. This is mandatory for
Dan Handley610e7e12018-03-01 18:44:00 +0000282 ``fip`` target in case TF-A BL2 is used.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100283
284- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
285 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
286 this file name will be used to save the key.
287
288- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
289 compilation of each build. It must be set to a C string (including quotes
290 where applicable). Defaults to a string that contains the time and date of
291 the compilation.
292
Dan Handley610e7e12018-03-01 18:44:00 +0000293- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF-A
294 build to be uniquely identified. Defaults to the current git commit id.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100295
296- ``CFLAGS``: Extra user options appended on the compiler's command line in
297 addition to the options set by the build system.
298
299- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
300 release several CPUs out of reset. It can take either 0 (several CPUs may be
301 brought up) or 1 (only one CPU will ever be brought up during cold reset).
302 Default is 0. If the platform always brings up a single CPU, there is no
303 need to distinguish between primary and secondary CPUs and the boot path can
304 be optimised. The ``plat_is_my_cpu_primary()`` and
305 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
306 to be implemented in this case.
307
308- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
309 register state when an unexpected exception occurs during execution of
310 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
311 this is only enabled for a debug build of the firmware.
312
313- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
314 certificate generation tool to create new keys in case no valid keys are
315 present or specified. Allowed options are '0' or '1'. Default is '1'.
316
317- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
318 the AArch32 system registers to be included when saving and restoring the
319 CPU context. The option must be set to 0 for AArch64-only platforms (that
320 is on hardware that does not implement AArch32, or at least not at EL1 and
321 higher ELs). Default value is 1.
322
323- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
324 registers to be included when saving and restoring the CPU context. Default
325 is 0.
326
327- ``DEBUG``: Chooses between a debug and release build. It can take either 0
328 (release) or 1 (debug) as values. 0 is the default.
329
John Tsichritzisee10e792018-06-06 09:38:10 +0100330- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
331 Board Boot authentication at runtime. This option is meant to be enabled only
Roberto Vargas025946a2018-09-24 17:20:48 +0100332 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
333 flag has to be enabled. 0 is the default.
Soby Mathew9fe88042018-03-26 12:43:37 +0100334
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100335- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
336 the normal boot flow. It must specify the entry point address of the EL3
337 payload. Please refer to the "Booting an EL3 payload" section for more
338 details.
339
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100340- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100341 This is an optional architectural feature available on v8.4 onwards. Some
342 v8.2 implementations also implement an AMU and this option can be used to
343 enable this feature on those systems as well. Default is 0.
Dimitris Papastamosfcedb692017-10-16 11:40:10 +0100344
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100345- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
346 are compiled out. For debug builds, this option defaults to 1, and calls to
347 ``assert()`` are left in place. For release builds, this option defaults to 0
348 and calls to ``assert()`` function are compiled out. This option can be set
349 independently of ``DEBUG``. It can also be used to hide any auxiliary code
350 that is only required for the assertion and does not fit in the assertion
351 itself.
352
Douglas Raillard77414632018-08-21 12:54:45 +0100353- ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
354 dumps or not. It is supported in both AArch64 and AArch32. However, in
355 AArch32 the format of the frame records are not defined in the AAPCS and they
356 are defined by the implementation. This implementation of backtrace only
357 supports the format used by GCC when T32 interworking is disabled. For this
358 reason enabling this option in AArch32 will force the compiler to only
359 generate A32 code. This option is enabled by default only in AArch64 debug
360 builds, but this behaviour can be overriden in each platform's Makefile or in
361 the build command line.
362
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100363- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
364 feature. MPAM is an optional Armv8.4 extension that enables various memory
365 system components and resources to define partitions; software running at
366 various ELs can assign themselves to desired partition to control their
367 performance aspects.
368
369 When this option is set to ``1``, EL3 allows lower ELs to access their own
370 MPAM registers without trapping into EL3. This option doesn't make use of
371 partitioning in EL3, however. Platform initialisation code should configure
372 and use partitions in EL3 as required. This option defaults to ``0``.
373
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
375 Measurement Framework(PMF). Default is 0.
376
377- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
378 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
379 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
380 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
381 software.
382
383- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000384 instrumentation which injects timestamp collection points into TF-A to
385 allow runtime performance to be measured. Currently, only PSCI is
386 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
387 as well. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100388
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100389- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
Dimitris Papastamos9da09cd2017-10-13 15:07:45 +0100390 extensions. This is an optional architectural feature for AArch64.
391 The default is 1 but is automatically disabled when the target architecture
392 is AArch32.
Jeenu Viswambharand73dcf32017-07-19 13:52:12 +0100393
Sandrine Bailleux604f0a42018-09-20 12:44:39 +0200394- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
395 Refer to the `Secure Partition Manager Design guide`_ for more details about
396 this feature. Default is 0.
397
David Cunadoce88eee2017-10-20 11:30:57 +0100398- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
399 (SVE) for the Non-secure world only. SVE is an optional architectural feature
400 for AArch64. Note that when SVE is enabled for the Non-secure world, access
401 to SIMD and floating-point functionality from the Secure world is disabled.
402 This is to avoid corruption of the Non-secure world data in the Z-registers
403 which are aliased by the SIMD and FP registers. The build option is not
404 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
405 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
406 1. The default is 1 but is automatically disabled when the target
407 architecture is AArch32.
408
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100409- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
410 checks in GCC. Allowed values are "all", "strong" and "0" (default).
411 "strong" is the recommended stack protection level if this feature is
412 desired. 0 disables the stack protection. For all values other than 0, the
413 ``plat_get_stack_protector_canary()`` platform hook needs to be implemented.
414 The value is passed as the last component of the option
415 ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
416
417- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
418 deprecated platform APIs, helper functions or drivers within Trusted
419 Firmware as error. It can take the value 1 (flag the use of deprecated
420 APIs as error) or 0. The default is 0.
421
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100422- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
423 targeted at EL3. When set ``0`` (default), no exceptions are expected or
424 handled at EL3, and a panic will result. This is supported only for AArch64
425 builds.
426
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000427- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 externsions introduced support for fault
428 injection from lower ELs, and this build option enables lower ELs to use
429 Error Records accessed via System Registers to inject faults. This is
430 applicable only to AArch64 builds.
431
432 This feature is intended for testing purposes only, and is advisable to keep
433 disabled for production images.
434
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100435- ``FIP_NAME``: This is an optional build option which specifies the FIP
436 filename for the ``fip`` target. Default is ``fip.bin``.
437
438- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
439 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
440
441- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
442 tool to create certificates as per the Chain of Trust described in
443 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
444 include the certificates in the FIP and FWU\_FIP. Default value is '0'.
445
446 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
447 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
448 the corresponding certificates, and to include those certificates in the
449 FIP and FWU\_FIP.
450
451 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
452 images will not include support for Trusted Board Boot. The FIP will still
453 include the corresponding certificates. This FIP can be used to verify the
454 Chain of Trust on the host machine through other mechanisms.
455
456 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
457 images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
458 will not include the corresponding certificates, causing a boot failure.
459
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100460- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
461 inherent support for specific EL3 type interrupts. Setting this build option
462 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
463 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
464 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
465 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
466 the Secure Payload interrupts needs to be synchronously handed over to Secure
467 EL1 for handling. The default value of this option is ``0``, which means the
468 Group 0 interrupts are assumed to be handled by Secure EL1.
469
470 .. __: `platform-interrupt-controller-API.rst`
471 .. __: `interrupt-framework-design.rst`
472
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700473- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
474 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
475 ``0`` (default), these exceptions will be trapped in the current exception
476 level (or in EL1 if the current exception level is EL0).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100477
Dan Handley610e7e12018-03-01 18:44:00 +0000478- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100479 software operations are required for CPUs to enter and exit coherency.
480 However, there exists newer systems where CPUs' entry to and exit from
481 coherency is managed in hardware. Such systems require software to only
482 initiate the operations, and the rest is managed in hardware, minimizing
Dan Handley610e7e12018-03-01 18:44:00 +0000483 active software management. In such systems, this boolean option enables
484 TF-A to carry out build and run-time optimizations during boot and power
485 management operations. This option defaults to 0 and if it is enabled,
486 then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100487
Jeenu Viswambharane834ee12018-04-27 15:17:03 +0100488 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
489 translation library (xlat tables v2) must be used; version 1 of translation
490 library is not supported.
491
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100492- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
493 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
494 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
495 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
496 images.
497
Soby Mathew13b16052017-08-31 11:49:32 +0100498- ``KEY_ALG``: This build flag enables the user to select the algorithm to be
499 used for generating the PKCS keys and subsequent signing of the certificate.
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800500 It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is
Soby Mathew2fd70f62017-08-31 11:50:29 +0100501 the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is
502 retained only for compatibility. The default value of this flag is ``rsa``
503 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
Soby Mathew13b16052017-08-31 11:49:32 +0100504
Qixiang Xu1a1f2912017-11-09 13:56:29 +0800505- ``HASH_ALG``: This build flag enables the user to select the secure hash
506 algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``.
507 The default value of this flag is ``sha256``.
508
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100509- ``LDFLAGS``: Extra user options appended to the linkers' command line in
510 addition to the one set by the build system.
511
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100512- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
513 output compiled into the build. This should be one of the following:
514
515 ::
516
517 0 (LOG_LEVEL_NONE)
Daniel Boulby86c6b072018-06-14 10:07:40 +0100518 10 (LOG_LEVEL_ERROR)
519 20 (LOG_LEVEL_NOTICE)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100520 30 (LOG_LEVEL_WARNING)
521 40 (LOG_LEVEL_INFO)
522 50 (LOG_LEVEL_VERBOSE)
523
John Tsichritzis35006c42018-10-05 12:02:29 +0100524 All log output up to and including the selected log level is compiled into
525 the build. The default value is 40 in debug builds and 20 in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100526
527- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
528 specifies the file that contains the Non-Trusted World private key in PEM
529 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
530
531- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
532 optional. It is only needed if the platform makefile specifies that it
533 is required in order to build the ``fwu_fip`` target.
534
535- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
536 contents upon world switch. It can take either 0 (don't save and restore) or
537 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
538 wants the timer registers to be saved and restored.
539
540- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
541 the underlying hardware is not a full PL011 UART but a minimally compliant
542 generic UART, which is a subset of the PL011. The driver will not access
543 any register that is not part of the SBSA generic UART specification.
544 Default value is 0 (a full PL011 compliant UART is present).
545
Dan Handley610e7e12018-03-01 18:44:00 +0000546- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
547 must be subdirectory of any depth under ``plat/``, and must contain a
548 platform makefile named ``platform.mk``. For example, to build TF-A for the
549 Arm Juno board, select PLAT=juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100550
551- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
552 instead of the normal boot flow. When defined, it must specify the entry
553 point address for the preloaded BL33 image. This option is incompatible with
554 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
555 over ``PRELOADED_BL33_BASE``.
556
557- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
558 vector address can be programmed or is fixed on the platform. It can take
559 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
560 programmable reset address, it is expected that a CPU will start executing
561 code directly at the right address, both on a cold and warm reset. In this
562 case, there is no need to identify the entrypoint on boot and the boot path
563 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
564 does not need to be implemented in this case.
565
566- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
567 possible for the PSCI power-state parameter viz original and extended
568 State-ID formats. This flag if set to 1, configures the generic PSCI layer
569 to use the extended format. The default value of this flag is 0, which
570 means by default the original power-state format is used by the PSCI
571 implementation. This flag should be specified by the platform makefile
572 and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
Dan Handley610e7e12018-03-01 18:44:00 +0000573 smc function id. When this option is enabled on Arm platforms, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100574 option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
575
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100576- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
577 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
578 or later CPUs.
579
580 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
581 set to ``1``.
582
583 This option is disabled by default.
584
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100585- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
586 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
587 entrypoint) or 1 (CPU reset to BL31 entrypoint).
588 The default value is 0.
589
Dan Handley610e7e12018-03-01 18:44:00 +0000590- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided
591 in TF-A. This flag configures SP\_MIN entrypoint as the CPU reset vector
592 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
593 entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default value is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100594
595- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
596 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
597 file name will be used to save the key.
598
599- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
600 certificate generation tool to save the keys used to establish the Chain of
601 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
602
603- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
604 If a SCP\_BL2 image is present then this option must be passed for the ``fip``
605 target.
606
607- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
608 file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
609 this file name will be used to save the key.
610
611- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
612 optional. It is only needed if the platform makefile specifies that it
613 is required in order to build the ``fwu_fip`` target.
614
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +0100615- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
616 Delegated Exception Interface to BL31 image. This defaults to ``0``.
617
618 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
619 set to ``1``.
620
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100621- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
622 isolated on separate memory pages. This is a trade-off between security and
623 memory usage. See "Isolating code and read-only data on separate memory
624 pages" section in `Firmware Design`_. This flag is disabled by default and
625 affects all BL images.
626
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100627- ``SMCCC_MAJOR_VERSION``: Numeric value that indicates the major version of
628 the SMC Calling Convention that the Trusted Firmware supports. The only two
629 allowed values are 1 and 2, and it defaults to 1. The minor version is
630 determined using this value.
631
Dan Handley610e7e12018-03-01 18:44:00 +0000632- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
633 This build option is only valid if ``ARCH=aarch64``. The value should be
634 the path to the directory containing the SPD source, relative to
635 ``services/spd/``; the directory is expected to contain a makefile called
636 ``<spd-value>.mk``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100637
638- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
639 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
640 execution in BL1 just before handing over to BL31. At this point, all
641 firmware images have been loaded in memory, and the MMU and caches are
642 turned off. Refer to the "Debugging options" section for more details.
643
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100644- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200645 secure interrupts (caught through the FIQ line). Platforms can enable
646 this directive if they need to handle such interruption. When enabled,
647 the FIQ are handled in monitor mode and non secure world is not allowed
648 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
649 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
650
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100651- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
652 Boot feature. When set to '1', BL1 and BL2 images include support to load
653 and verify the certificates and images in a FIP, and BL1 includes support
654 for the Firmware Update. The default value is '0'. Generation and inclusion
655 of certificates in the FIP and FWU\_FIP depends upon the value of the
656 ``GENERATE_COT`` option.
657
658 Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
659 already exist in disk, they will be overwritten without further notice.
660
661- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
662 specifies the file that contains the Trusted World private key in PEM
663 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
664
665- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
666 synchronous, (see "Initializing a BL32 Image" section in
667 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
668 synchronous method) or 1 (BL32 is initialized using asynchronous method).
669 Default is 0.
670
671- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
672 routing model which routes non-secure interrupts asynchronously from TSP
673 to EL3 causing immediate preemption of TSP. The EL3 is responsible
674 for saving and restoring the TSP context in this routing model. The
675 default routing model (when the value is 0) is to route non-secure
676 interrupts to TSP allowing it to save its context and hand over
677 synchronously to EL3 via an SMC.
678
Jeenu Viswambharan2f40f322018-01-11 14:30:22 +0000679 Note: when ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
680 must also be set to ``1``.
681
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100682- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
683 memory region in the BL memory map or not (see "Use of Coherent memory in
Dan Handley610e7e12018-03-01 18:44:00 +0000684 TF-A" section in `Firmware Design`_). It can take the value 1
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100685 (Coherent memory region is included) or 0 (Coherent memory region is
686 excluded). Default is 1.
687
688- ``V``: Verbose build. If assigned anything other than 0, the build commands
689 are printed. Default is 0.
690
Dan Handley610e7e12018-03-01 18:44:00 +0000691- ``VERSION_STRING``: String used in the log output for each TF-A image.
692 Defaults to a string formed by concatenating the version number, build type
693 and build string.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100694
695- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
696 the CPU after warm boot. This is applicable for platforms which do not
697 require interconnect programming to enable cache coherency (eg: single
698 cluster platforms). If this option is enabled, then warm boot path
699 enables D-caches immediately after enabling MMU. This option defaults to 0.
700
Dan Handley610e7e12018-03-01 18:44:00 +0000701Arm development platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100702^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
703
704- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
705 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
706 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
707 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
708 flag.
709
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100710- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
711 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
712 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
713 match the frame used by the Non-Secure image (normally the Linux kernel).
714 Default is true (access to the frame is allowed).
715
716- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
Dan Handley610e7e12018-03-01 18:44:00 +0000717 By default, Arm platforms use a watchdog to trigger a system reset in case
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100718 an error is encountered during the boot process (for example, when an image
719 could not be loaded or authenticated). The watchdog is enabled in the early
720 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
721 Trusted Watchdog may be disabled at build time for testing or development
722 purposes.
723
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100724- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
725 have specific values at boot. This boolean option allows the Trusted Firmware
726 to have a Linux kernel image as BL33 by preparing the registers to these
727 values before jumping to BL33. This option defaults to 0 (disabled). For now,
728 it only supports AArch64 kernels. ``RESET_TO_BL31`` must be 1 when using it.
729 If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set to the
730 location of a device tree blob (DTB) already loaded in memory. The Linux
731 Image address must be specified using the ``PRELOADED_BL33_BASE`` option.
732
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100733- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
734 for the construction of composite state-ID in the power-state parameter.
735 The existing PSCI clients currently do not support this encoding of
736 State-ID yet. Hence this flag is used to configure whether to use the
737 recommended State-ID encoding or not. The default value of this flag is 0,
738 in which case the platform is configured to expect NULL in the State-ID
739 field of power-state parameter.
740
741- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
742 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
Dan Handley610e7e12018-03-01 18:44:00 +0000743 for Arm platforms. Depending on the selected option, the proper private key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100744 must be specified using the ``ROT_KEY`` option when building the Trusted
745 Firmware. This private key will be used by the certificate generation tool
746 to sign the BL2 and Trusted Key certificates. Available options for
747 ``ARM_ROTPK_LOCATION`` are:
748
749 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
750 registers. The private key corresponding to this ROTPK hash is not
751 currently available.
752 - ``devel_rsa`` : return a development public key hash embedded in the BL1
753 and BL2 binaries. This hash has been obtained from the RSA public key
754 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
755 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
756 creating the certificates.
Qixiang Xu1c2aef12017-08-24 15:12:20 +0800757 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
758 and BL2 binaries. This hash has been obtained from the ECDSA public key
759 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
760 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
761 when creating the certificates.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100762
763- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
764
Qixiang Xuc7b12c52017-10-13 09:04:12 +0800765 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100766 - ``tdram`` : Trusted DRAM (if available)
John Tsichritzisee10e792018-06-06 09:38:10 +0100767 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
768 configured by the TrustZone controller)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100769
Dan Handley610e7e12018-03-01 18:44:00 +0000770- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
771 of the translation tables library instead of version 2. It is set to 0 by
772 default, which selects version 2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100773
Dan Handley610e7e12018-03-01 18:44:00 +0000774- ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
775 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
776 platforms. If this option is specified, then the path to the CryptoCell
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100777 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
778
Dan Handley610e7e12018-03-01 18:44:00 +0000779For a better understanding of these options, the Arm development platform memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100780map is explained in the `Firmware Design`_.
781
Dan Handley610e7e12018-03-01 18:44:00 +0000782Arm CSS platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100783^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
784
785- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
786 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
787 compatible change to the MTL protocol, used for AP/SCP communication.
Dan Handley610e7e12018-03-01 18:44:00 +0000788 TF-A no longer supports earlier SCP versions. If this option is set to 1
789 then TF-A will detect if an earlier version is in use. Default is 1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100790
791- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
792 SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
793 during boot. Default is 1.
794
Soby Mathew1ced6b82017-06-12 12:37:10 +0100795- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
796 instead of SCPI/BOM driver for communicating with the SCP during power
797 management operations and for SCP RAM Firmware transfer. If this option
798 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100799
Dan Handley610e7e12018-03-01 18:44:00 +0000800Arm FVP platform specific build options
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100801^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
802
803- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
Dan Handley610e7e12018-03-01 18:44:00 +0000804 build the topology tree within TF-A. By default TF-A is configured for dual
805 cluster topology and this option can be used to override the default value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100806
807- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
808 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
809 explained in the options below:
810
811 - ``FVP_CCI`` : The CCI driver is selected. This is the default
812 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
813 - ``FVP_CCN`` : The CCN driver is selected. This is the default
814 if ``FVP_CLUSTER_COUNT`` > 2.
815
Jeenu Viswambharan75421132018-01-31 14:52:08 +0000816- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
817 a single cluster. This option defaults to 4.
818
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +0000819- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
820 in the system. This option defaults to 1. Note that the build option
821 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
822
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100823- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
824
825 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
826 - ``FVP_GICV2`` : The GICv2 only driver is selected
827 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100828
829- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
830 for functions that wait for an arbitrary time length (udelay and mdelay).
831 The default value is 0.
832
Soby Mathewb1bf0442018-02-16 14:52:52 +0000833- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
834 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
835 details on HW_CONFIG. By default, this is initialized to a sensible DTS
836 file in ``fdts/`` folder depending on other build options. But some cases,
837 like shifted affinity format for MPIDR, cannot be detected at build time
838 and this option is needed to specify the appropriate DTS file.
839
840- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
841 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
842 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
843 HW_CONFIG blob instead of the DTS file. This option is useful to override
844 the default HW_CONFIG selected by the build system.
845
Summer Qin13b95c22018-03-02 15:51:14 +0800846ARM JUNO platform specific build options
847^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
848
849- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
850 Media Protection (TZ-MP1). Default value of this flag is 0.
851
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100852Debugging options
853~~~~~~~~~~~~~~~~~
854
855To compile a debug version and make the build more verbose use
856
857::
858
859 make PLAT=<platform> DEBUG=1 V=1 all
860
861AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
862example DS-5) might not support this and may need an older version of DWARF
863symbols to be emitted by GCC. This can be achieved by using the
864``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
865version to 2 is recommended for DS-5 versions older than 5.16.
866
867When debugging logic problems it might also be useful to disable all compiler
868optimizations by using ``-O0``.
869
870NOTE: Using ``-O0`` could cause output images to be larger and base addresses
Dan Handley610e7e12018-03-01 18:44:00 +0000871might need to be recalculated (see the **Memory layout on Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100872platforms** section in the `Firmware Design`_).
873
874Extra debug options can be passed to the build system by setting ``CFLAGS`` or
875``LDFLAGS``:
876
877.. code:: makefile
878
879 CFLAGS='-O0 -gdwarf-2' \
880 make PLAT=<platform> DEBUG=1 V=1 all
881
882Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
883ignored as the linker is called directly.
884
885It is also possible to introduce an infinite loop to help in debugging the
Dan Handley610e7e12018-03-01 18:44:00 +0000886post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
887``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100888section. In this case, the developer may take control of the target using a
889debugger when indicated by the console output. When using DS-5, the following
890commands can be used:
891
892::
893
894 # Stop target execution
895 interrupt
896
897 #
898 # Prepare your debugging environment, e.g. set breakpoints
899 #
900
901 # Jump over the debug loop
902 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
903
904 # Resume execution
905 continue
906
907Building the Test Secure Payload
908~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
909
910The TSP is coupled with a companion runtime service in the BL31 firmware,
911called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
912must be recompiled as well. For more information on SPs and SPDs, see the
913`Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
914
Dan Handley610e7e12018-03-01 18:44:00 +0000915First clean the TF-A build directory to get rid of any previous BL31 binary.
916Then to build the TSP image use:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100917
918::
919
920 make PLAT=<platform> SPD=tspd all
921
922An additional boot loader binary file is created in the ``build`` directory:
923
924::
925
926 build/<platform>/<build-type>/bl32.bin
927
928Checking source code style
929~~~~~~~~~~~~~~~~~~~~~~~~~~
930
931When making changes to the source for submission to the project, the source
932must be in compliance with the Linux style guide, and to assist with this check
933the project Makefile contains two targets, which both utilise the
934``checkpatch.pl`` script that ships with the Linux source tree.
935
Joel Huttonfe027712018-03-19 11:59:57 +0000936To check the entire source tree, you must first download copies of
937``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
938in the `Linux master tree`_ scripts directory, then set the ``CHECKPATCH``
939environment variable to point to ``checkpatch.pl`` (with the other 2 files in
John Tsichritzisee10e792018-06-06 09:38:10 +0100940the same directory) and build the target checkcodebase:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100941
942::
943
944 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
945
946To just check the style on the files that differ between your local branch and
947the remote master, use:
948
949::
950
951 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
952
953If you wish to check your patch against something other than the remote master,
954set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
955is set to ``origin/master``.
956
957Building and using the FIP tool
958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
959
Dan Handley610e7e12018-03-01 18:44:00 +0000960Firmware Image Package (FIP) is a packaging format used by TF-A to package
961firmware images in a single binary. The number and type of images that should
962be packed in a FIP is platform specific and may include TF-A images and other
963firmware images required by the platform. For example, most platforms require
964a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
965U-Boot).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100966
Dan Handley610e7e12018-03-01 18:44:00 +0000967The TF-A build system provides the make target ``fip`` to create a FIP file
968for the specified platform using the FIP creation tool included in the TF-A
969project. Examples below show how to build a FIP file for FVP, packaging TF-A
970and BL33 images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100971
972For AArch64:
973
974::
975
976 make PLAT=fvp BL33=<path/to/bl33.bin> fip
977
978For AArch32:
979
980::
981
982 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip
983
984Note that AArch32 support for Normal world boot loader (BL33), like U-boot or
985UEFI, on FVP is not available upstream. Hence custom solutions are required to
986allow Linux boot on FVP. These instructions assume such a custom boot loader
987(BL33) is available.
988
989The resulting FIP may be found in:
990
991::
992
993 build/fvp/<build-type>/fip.bin
994
995For advanced operations on FIP files, it is also possible to independently build
996the tool and create or modify FIPs using this tool. To do this, follow these
997steps:
998
999It is recommended to remove old artifacts before building the tool:
1000
1001::
1002
1003 make -C tools/fiptool clean
1004
1005Build the tool:
1006
1007::
1008
1009 make [DEBUG=1] [V=1] fiptool
1010
1011The tool binary can be located in:
1012
1013::
1014
1015 ./tools/fiptool/fiptool
1016
1017Invoking the tool with ``--help`` will print a help message with all available
1018options.
1019
1020Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1021
1022::
1023
1024 ./tools/fiptool/fiptool create \
1025 --tb-fw build/<platform>/<build-type>/bl2.bin \
1026 --soc-fw build/<platform>/<build-type>/bl31.bin \
1027 fip.bin
1028
1029Example 2: view the contents of an existing Firmware package:
1030
1031::
1032
1033 ./tools/fiptool/fiptool info <path-to>/fip.bin
1034
1035Example 3: update the entries of an existing Firmware package:
1036
1037::
1038
1039 # Change the BL2 from Debug to Release version
1040 ./tools/fiptool/fiptool update \
1041 --tb-fw build/<platform>/release/bl2.bin \
1042 build/<platform>/debug/fip.bin
1043
1044Example 4: unpack all entries from an existing Firmware package:
1045
1046::
1047
1048 # Images will be unpacked to the working directory
1049 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1050
1051Example 5: remove an entry from an existing Firmware package:
1052
1053::
1054
1055 ./tools/fiptool/fiptool remove \
1056 --tb-fw build/<platform>/debug/fip.bin
1057
1058Note that if the destination FIP file exists, the create, update and
1059remove operations will automatically overwrite it.
1060
1061The unpack operation will fail if the images already exist at the
1062destination. In that case, use -f or --force to continue.
1063
1064More information about FIP can be found in the `Firmware Design`_ document.
1065
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001066Building FIP images with support for Trusted Board Boot
1067~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1068
1069Trusted Board Boot primarily consists of the following two features:
1070
1071- Image Authentication, described in `Trusted Board Boot`_, and
1072- Firmware Update, described in `Firmware Update`_
1073
1074The following steps should be followed to build FIP and (optionally) FWU\_FIP
1075images with support for these features:
1076
1077#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1078 modules by checking out a recent version of the `mbed TLS Repository`_. It
Dan Handley610e7e12018-03-01 18:44:00 +00001079 is important to use a version that is compatible with TF-A and fixes any
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001080 known security vulnerabilities. See `mbed TLS Security Center`_ for more
Dan Handley610e7e12018-03-01 18:44:00 +00001081 information. The latest version of TF-A is tested with tag
David Cunado05845bf2017-12-19 16:33:25 +00001082 ``mbedtls-2.12.0``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001083
1084 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1085 source files the modules depend upon.
1086 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1087 options required to build the mbed TLS sources.
1088
1089 Note that the mbed TLS library is licensed under the Apache version 2.0
Dan Handley610e7e12018-03-01 18:44:00 +00001090 license. Using mbed TLS source code will affect the licensing of TF-A
1091 binaries that are built using this library.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001092
1093#. To build the FIP image, ensure the following command line variables are set
Dan Handley610e7e12018-03-01 18:44:00 +00001094 while invoking ``make`` to build TF-A:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001095
1096 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1097 - ``TRUSTED_BOARD_BOOT=1``
1098 - ``GENERATE_COT=1``
1099
Dan Handley610e7e12018-03-01 18:44:00 +00001100 In the case of Arm platforms, the location of the ROTPK hash must also be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001101 specified at build time. Two locations are currently supported (see
1102 ``ARM_ROTPK_LOCATION`` build option):
1103
1104 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1105 root-key storage registers present in the platform. On Juno, this
1106 registers are read-only. On FVP Base and Cortex models, the registers
1107 are read-only, but the value can be specified using the command line
1108 option ``bp.trusted_key_storage.public_key`` when launching the model.
1109 On both Juno and FVP models, the default value corresponds to an
1110 ECDSA-SECP256R1 public key hash, whose private part is not currently
1111 available.
1112
1113 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001114 in the Arm platform port. The private/public RSA key pair may be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001115 found in ``plat/arm/board/common/rotpk``.
1116
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001117 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
Dan Handley610e7e12018-03-01 18:44:00 +00001118 in the Arm platform port. The private/public ECDSA key pair may be
Qixiang Xu1c2aef12017-08-24 15:12:20 +08001119 found in ``plat/arm/board/common/rotpk``.
1120
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001121 Example of command line using RSA development keys:
1122
1123 ::
1124
1125 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1126 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1127 ARM_ROTPK_LOCATION=devel_rsa \
1128 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1129 BL33=<path-to>/<bl33_image> \
1130 all fip
1131
1132 The result of this build will be the bl1.bin and the fip.bin binaries. This
1133 FIP will include the certificates corresponding to the Chain of Trust
1134 described in the TBBR-client document. These certificates can also be found
1135 in the output build directory.
1136
1137#. The optional FWU\_FIP contains any additional images to be loaded from
1138 Non-Volatile storage during the `Firmware Update`_ process. To build the
1139 FWU\_FIP, any FWU images required by the platform must be specified on the
Dan Handley610e7e12018-03-01 18:44:00 +00001140 command line. On Arm development platforms like Juno, these are:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001141
1142 - NS\_BL2U. The AP non-secure Firmware Updater image.
1143 - SCP\_BL2U. The SCP Firmware Update Configuration image.
1144
1145 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1146 targets using RSA development:
1147
1148 ::
1149
1150 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1151 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1152 ARM_ROTPK_LOCATION=devel_rsa \
1153 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1154 BL33=<path-to>/<bl33_image> \
1155 SCP_BL2=<path-to>/<scp_bl2_image> \
1156 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1157 NS_BL2U=<path-to>/<ns_bl2u_image> \
1158 all fip fwu_fip
1159
1160 Note: The BL2U image will be built by default and added to the FWU\_FIP.
1161 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1162 to the command line above.
1163
1164 Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
1165 NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
1166
1167 The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
1168 Both the FIP and FWU\_FIP will include the certificates corresponding to the
1169 Chain of Trust described in the TBBR-client document. These certificates
1170 can also be found in the output build directory.
1171
1172Building the Certificate Generation Tool
1173~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1174
Dan Handley610e7e12018-03-01 18:44:00 +00001175The ``cert_create`` tool is built as part of the TF-A build process when the
1176``fip`` make target is specified and TBB is enabled (as described in the
1177previous section), but it can also be built separately with the following
1178command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001179
1180::
1181
1182 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1183
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001184For platforms that require their own IDs in certificate files, the generic
1185'cert\_create' tool can be built with the following command:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001186
1187::
1188
Antonio Nino Diazd8d734c2018-09-25 09:41:08 +01001189 make USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001190
1191``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1192verbose. The following command should be used to obtain help about the tool:
1193
1194::
1195
1196 ./tools/cert_create/cert_create -h
1197
1198Building a FIP for Juno and FVP
1199-------------------------------
1200
1201This section provides Juno and FVP specific instructions to build Trusted
1202Firmware, obtain the additional required firmware, and pack it all together in
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001203a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001204
David Cunadob2de0992017-06-29 12:01:33 +01001205Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
1206onwards. Before that release, pre-built binaries are only available for AArch64.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001207
Joel Huttonfe027712018-03-19 11:59:57 +00001208Note: Follow the full instructions for one platform before switching to a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001209different one. Mixing instructions for different platforms may result in
1210corrupted binaries.
1211
Joel Huttonfe027712018-03-19 11:59:57 +00001212Note: The uboot image downloaded by the Linaro workspace script does not always
1213match the uboot image packaged as BL33 in the corresponding fip file. It is
1214recommended to use the version that is packaged in the fip file using the
1215instructions below.
1216
Soby Mathewecd94ad2018-05-09 13:59:29 +01001217Note: For the FVP, the kernel FDT is packaged in FIP during build and loaded
1218by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1219section for more info on selecting the right FDT to use.
1220
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001221#. Clean the working directory
1222
1223 ::
1224
1225 make realclean
1226
1227#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
1228
1229 Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
1230 package included in the Linaro release:
1231
1232 ::
1233
1234 # Build the fiptool
1235 make [DEBUG=1] [V=1] fiptool
1236
1237 # Unpack firmware images from Linaro FIP
1238 ./tools/fiptool/fiptool unpack \
1239 <path/to/linaro/release>/fip.bin
1240
1241 The unpack operation will result in a set of binary images extracted to the
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001242 current working directory. The SCP\_BL2 image corresponds to
1243 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001244
Joel Huttonfe027712018-03-19 11:59:57 +00001245 Note: The fiptool will complain if the images to be unpacked already
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001246 exist in the current directory. If that is the case, either delete those
1247 files or use the ``--force`` option to overwrite.
1248
Joel Huttonfe027712018-03-19 11:59:57 +00001249 Note: For AArch32, the instructions below assume that nt-fw.bin is a custom
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001250 Normal world boot loader that supports AArch32.
1251
Dan Handley610e7e12018-03-01 18:44:00 +00001252#. Build TF-A images and create a new FIP for FVP
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001253
1254 ::
1255
1256 # AArch64
1257 make PLAT=fvp BL33=nt-fw.bin all fip
1258
1259 # AArch32
1260 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1261
Dan Handley610e7e12018-03-01 18:44:00 +00001262#. Build TF-A images and create a new FIP for Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001263
1264 For AArch64:
1265
1266 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1267 as a build parameter.
1268
1269 ::
1270
1271 make PLAT=juno all fip \
1272 BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \
1273 SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin
1274
1275 For AArch32:
1276
1277 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1278 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1279 separately for AArch32.
1280
1281 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1282 to the AArch32 Linaro cross compiler.
1283
1284 ::
1285
1286 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1287
1288 - Build BL32 in AArch32.
1289
1290 ::
1291
1292 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1293 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1294
1295 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1296 must point to the AArch64 Linaro cross compiler.
1297
1298 ::
1299
1300 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1301
1302 - The following parameters should be used to build BL1 and BL2 in AArch64
1303 and point to the BL32 file.
1304
1305 ::
1306
Soby Mathew97b1bff2018-09-27 16:46:41 +01001307 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001308 BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
Soby Mathewbf169232017-11-14 14:10:10 +00001309 SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001310 BL32=<path-to-bl32>/bl32.bin all fip
1311
1312The resulting BL1 and FIP images may be found in:
1313
1314::
1315
1316 # Juno
1317 ./build/juno/release/bl1.bin
1318 ./build/juno/release/fip.bin
1319
1320 # FVP
1321 ./build/fvp/release/bl1.bin
1322 ./build/fvp/release/fip.bin
1323
Roberto Vargas096f3a02017-10-17 10:19:00 +01001324
1325Booting Firmware Update images
1326-------------------------------------
1327
1328When Firmware Update (FWU) is enabled there are at least 2 new images
1329that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1330FWU FIP.
1331
1332Juno
1333~~~~
1334
1335The new images must be programmed in flash memory by adding
1336an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1337on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1338Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1339programming" for more information. User should ensure these do not
1340overlap with any other entries in the file.
1341
1342::
1343
1344 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1345 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1346 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1347 NOR10LOAD: 00000000 ;Image Load Address
1348 NOR10ENTRY: 00000000 ;Image Entry Point
1349
1350 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1351 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1352 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1353 NOR11LOAD: 00000000 ;Image Load Address
1354
1355The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1356In the same way, the address ns_bl2u_base_address is the value of
1357NS_BL2U_BASE - 0x8000000.
1358
1359FVP
1360~~~
1361
1362The additional fip images must be loaded with:
1363
1364::
1365
1366 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1367 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1368
1369The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1370In the same way, the address ns_bl2u_base_address is the value of
1371NS_BL2U_BASE.
1372
1373
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001374EL3 payloads alternative boot flow
1375----------------------------------
1376
1377On a pre-production system, the ability to execute arbitrary, bare-metal code at
1378the highest exception level is required. It allows full, direct access to the
1379hardware, for example to run silicon soak tests.
1380
1381Although it is possible to implement some baremetal secure firmware from
1382scratch, this is a complex task on some platforms, depending on the level of
1383configuration required to put the system in the expected state.
1384
1385Rather than booting a baremetal application, a possible compromise is to boot
Dan Handley610e7e12018-03-01 18:44:00 +00001386``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1387boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1388other BL images and passing control to BL31. It reduces the complexity of
1389developing EL3 baremetal code by:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001390
1391- putting the system into a known architectural state;
1392- taking care of platform secure world initialization;
1393- loading the SCP\_BL2 image if required by the platform.
1394
Dan Handley610e7e12018-03-01 18:44:00 +00001395When booting an EL3 payload on Arm standard platforms, the configuration of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001396TrustZone controller is simplified such that only region 0 is enabled and is
1397configured to permit secure access only. This gives full access to the whole
1398DRAM to the EL3 payload.
1399
1400The system is left in the same state as when entering BL31 in the default boot
1401flow. In particular:
1402
1403- Running in EL3;
1404- Current state is AArch64;
1405- Little-endian data access;
1406- All exceptions disabled;
1407- MMU disabled;
1408- Caches disabled.
1409
1410Booting an EL3 payload
1411~~~~~~~~~~~~~~~~~~~~~~
1412
1413The EL3 payload image is a standalone image and is not part of the FIP. It is
Dan Handley610e7e12018-03-01 18:44:00 +00001414not loaded by TF-A. Therefore, there are 2 possible scenarios:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001415
1416- The EL3 payload may reside in non-volatile memory (NVM) and execute in
1417 place. In this case, booting it is just a matter of specifying the right
Dan Handley610e7e12018-03-01 18:44:00 +00001418 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001419
1420- The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1421 run-time.
1422
1423To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1424used. The infinite loop that it introduces in BL1 stops execution at the right
1425moment for a debugger to take control of the target and load the payload (for
1426example, over JTAG).
1427
1428It is expected that this loading method will work in most cases, as a debugger
1429connection is usually available in a pre-production system. The user is free to
1430use any other platform-specific mechanism to load the EL3 payload, though.
1431
1432Booting an EL3 payload on FVP
1433^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1434
1435The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1436the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1437is undefined on the FVP platform and the FVP platform code doesn't clear it.
1438Therefore, one must modify the way the model is normally invoked in order to
1439clear the mailbox at start-up.
1440
1441One way to do that is to create an 8-byte file containing all zero bytes using
1442the following command:
1443
1444::
1445
1446 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1447
1448and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1449using the following model parameters:
1450
1451::
1452
1453 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1454 --data=mailbox.dat@0x04000000 [Foundation FVP]
1455
1456To provide the model with the EL3 payload image, the following methods may be
1457used:
1458
1459#. If the EL3 payload is able to execute in place, it may be programmed into
1460 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1461 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1462 used for the FIP):
1463
1464 ::
1465
1466 -C bp.flashloader1.fname="/path/to/el3-payload"
1467
1468 On Foundation FVP, there is no flash loader component and the EL3 payload
1469 may be programmed anywhere in flash using method 3 below.
1470
1471#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1472 command may be used to load the EL3 payload ELF image over JTAG:
1473
1474 ::
1475
1476 load /path/to/el3-payload.elf
1477
1478#. The EL3 payload may be pre-loaded in volatile memory using the following
1479 model parameters:
1480
1481 ::
1482
1483 --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs]
1484 --data="/path/to/el3-payload"@address [Foundation FVP]
1485
1486 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
Dan Handley610e7e12018-03-01 18:44:00 +00001487 used when building TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001488
1489Booting an EL3 payload on Juno
1490^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1491
1492If the EL3 payload is able to execute in place, it may be programmed in flash
1493memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1494on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1495Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1496programming" for more information.
1497
1498Alternatively, the same DS-5 command mentioned in the FVP section above can
1499be used to load the EL3 payload's ELF file over JTAG on Juno.
1500
1501Preloaded BL33 alternative boot flow
1502------------------------------------
1503
1504Some platforms have the ability to preload BL33 into memory instead of relying
Dan Handley610e7e12018-03-01 18:44:00 +00001505on TF-A to load it. This may simplify packaging of the normal world code and
1506improve performance in a development environment. When secure world cold boot
1507is complete, TF-A simply jumps to a BL33 base address provided at build time.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001508
1509For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
Dan Handley610e7e12018-03-01 18:44:00 +00001510used when compiling TF-A. For example, the following command will create a FIP
1511without a BL33 and prepare to jump to a BL33 image loaded at address
15120x80000000:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001513
1514::
1515
1516 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1517
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001518Boot of a preloaded kernel image on Base FVP
1519~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001520
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001521The following example uses a simplified boot flow by directly jumping from the
1522TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1523useful if both the kernel and the device tree blob (DTB) are already present in
1524memory (like in FVP).
1525
1526For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1527address ``0x82000000``, the firmware can be built like this:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001528
1529::
1530
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001531 CROSS_COMPILE=aarch64-linux-gnu- \
1532 make PLAT=fvp DEBUG=1 \
1533 RESET_TO_BL31=1 \
1534 ARM_LINUX_KERNEL_AS_BL33=1 \
1535 PRELOADED_BL33_BASE=0x80080000 \
1536 ARM_PRELOADED_DTB_BASE=0x82000000 \
1537 all fip
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001538
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001539Now, it is needed to modify the DTB so that the kernel knows the address of the
1540ramdisk. The following script generates a patched DTB from the provided one,
1541assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1542script assumes that the user is using a ramdisk image prepared for U-Boot, like
1543the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1544offset in ``INITRD_START`` has to be removed.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001545
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001546.. code:: bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001547
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001548 #!/bin/bash
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001549
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001550 # Path to the input DTB
1551 KERNEL_DTB=<path-to>/<fdt>
1552 # Path to the output DTB
1553 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1554 # Base address of the ramdisk
1555 INITRD_BASE=0x84000000
1556 # Path to the ramdisk
1557 INITRD=<path-to>/<ramdisk.img>
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001558
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001559 # Skip uboot header (64 bytes)
1560 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1561 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1562 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1563
1564 CHOSEN_NODE=$(echo \
1565 "/ { \
1566 chosen { \
1567 linux,initrd-start = <${INITRD_START}>; \
1568 linux,initrd-end = <${INITRD_END}>; \
1569 }; \
1570 };")
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001571
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001572 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1573 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001574
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001575And the FVP binary can be run with the following command:
1576
1577::
1578
1579 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1580 -C pctl.startup=0.0.0.0 \
1581 -C bp.secure_memory=1 \
1582 -C cluster0.NUM_CORES=4 \
1583 -C cluster1.NUM_CORES=4 \
1584 -C cache_state_modelled=1 \
1585 -C cluster0.cpu0.RVBAR=0x04020000 \
1586 -C cluster0.cpu1.RVBAR=0x04020000 \
1587 -C cluster0.cpu2.RVBAR=0x04020000 \
1588 -C cluster0.cpu3.RVBAR=0x04020000 \
1589 -C cluster1.cpu0.RVBAR=0x04020000 \
1590 -C cluster1.cpu1.RVBAR=0x04020000 \
1591 -C cluster1.cpu2.RVBAR=0x04020000 \
1592 -C cluster1.cpu3.RVBAR=0x04020000 \
1593 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1594 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1595 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1596 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1597
1598Boot of a preloaded kernel image on Juno
1599~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001600
Antonio Nino Diazb1881552018-05-14 09:12:34 +01001601The Trusted Firmware must be compiled in a similar way as for FVP explained
1602above. The process to load binaries to memory is the one explained in
1603`Booting an EL3 payload on Juno`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001604
1605Running the software on FVP
1606---------------------------
1607
David Cunado7c032642018-03-12 18:47:05 +00001608The latest version of the AArch64 build of TF-A has been tested on the following
1609Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1610(64-bit host machine only).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001611
David Cunado05845bf2017-12-19 16:33:25 +00001612NOTE: Unless otherwise stated, the model version is Version 11.4 Build 37.
David Cunado124415e2017-06-27 17:31:12 +01001613
David Cunado05845bf2017-12-19 16:33:25 +00001614- ``FVP_Base_Aresx4``
1615- ``FVP_Base_AEMv8A-AEMv8A``
1616- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
1617- ``FVP_Base_AEMv8A-AEMv8A``
1618- ``FVP_Base_RevC-2xAEMv8A``
1619- ``FVP_Base_Cortex-A32x4``
David Cunado124415e2017-06-27 17:31:12 +01001620- ``FVP_Base_Cortex-A35x4``
1621- ``FVP_Base_Cortex-A53x4``
David Cunado05845bf2017-12-19 16:33:25 +00001622- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1623- ``FVP_Base_Cortex-A55x4``
David Cunado124415e2017-06-27 17:31:12 +01001624- ``FVP_Base_Cortex-A57x4-A53x4``
1625- ``FVP_Base_Cortex-A57x4``
1626- ``FVP_Base_Cortex-A72x4-A53x4``
1627- ``FVP_Base_Cortex-A72x4``
1628- ``FVP_Base_Cortex-A73x4-A53x4``
1629- ``FVP_Base_Cortex-A73x4``
David Cunado05845bf2017-12-19 16:33:25 +00001630- ``FVP_Base_Cortex-A75x4``
1631- ``FVP_Base_Cortex-A76x4``
1632- ``FVP_CSS_SGI-575`` (Version 11.3 build 40)
1633- ``Foundation_Platform``
David Cunado7c032642018-03-12 18:47:05 +00001634
1635The latest version of the AArch32 build of TF-A has been tested on the following
1636Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1637(64-bit host machine only).
1638
1639- ``FVP_Base_AEMv8A-AEMv8A``
David Cunado124415e2017-06-27 17:31:12 +01001640- ``FVP_Base_Cortex-A32x4``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001641
David Cunado7c032642018-03-12 18:47:05 +00001642NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1643is not compatible with legacy GIC configurations. Therefore this FVP does not
1644support these legacy GIC configurations.
1645
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001646NOTE: The build numbers quoted above are those reported by launching the FVP
1647with the ``--version`` parameter.
1648
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001649NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
1650file systems that can be downloaded separately. To run an FVP with a virtio
1651file system image an additional FVP configuration option
1652``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1653used.
1654
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001655NOTE: The software will not work on Version 1.0 of the Foundation FVP.
1656The commands below would report an ``unhandled argument`` error in this case.
1657
1658NOTE: FVPs can be launched with ``--cadi-server`` option such that a
Dan Handley610e7e12018-03-01 18:44:00 +00001659CADI-compliant debugger (for example, Arm DS-5) can connect to and control its
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001660execution.
1661
Eleanor Bonnicie124dc42017-10-04 15:03:33 +01001662NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
David Cunado97309462017-07-31 12:24:51 +01001663the internal synchronisation timings changed compared to older versions of the
1664models. The models can be launched with ``-Q 100`` option if they are required
1665to match the run time characteristics of the older versions.
1666
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001667The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
Dan Handley610e7e12018-03-01 18:44:00 +00001668downloaded for free from `Arm's website`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001669
David Cunado124415e2017-06-27 17:31:12 +01001670The Cortex-A models listed above are also available to download from
Dan Handley610e7e12018-03-01 18:44:00 +00001671`Arm's website`_.
David Cunado124415e2017-06-27 17:31:12 +01001672
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001673Please refer to the FVP documentation for a detailed description of the model
Dan Handley610e7e12018-03-01 18:44:00 +00001674parameter options. A brief description of the important ones that affect TF-A
1675and normal world software behavior is provided below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001676
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001677Obtaining the Flattened Device Trees
1678~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1679
1680Depending on the FVP configuration and Linux configuration used, different
Soby Mathewecd94ad2018-05-09 13:59:29 +01001681FDT files are required. FDT source files for the Foundation and Base FVPs can
1682be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1683a subset of the Base FVP components. For example, the Foundation FVP lacks
1684CLCD and MMC support, and has only one CPU cluster.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001685
1686Note: It is not recommended to use the FDTs built along the kernel because not
1687all FDTs are available from there.
1688
Soby Mathewecd94ad2018-05-09 13:59:29 +01001689The dynamic configuration capability is enabled in the firmware for FVPs.
1690This means that the firmware can authenticate and load the FDT if present in
1691FIP. A default FDT is packaged into FIP during the build based on
1692the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1693or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1694`Arm FVP platform specific build options`_ section for detail on the options).
1695
1696- ``fvp-base-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001697
David Cunado7c032642018-03-12 18:47:05 +00001698 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1699 affinities and with Base memory map configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001700
Soby Mathewecd94ad2018-05-09 13:59:29 +01001701- ``fvp-base-gicv2-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001702
David Cunado7c032642018-03-12 18:47:05 +00001703 For use with models such as the Cortex-A32 Base FVPs without shifted
1704 affinities and running Linux in AArch32 state with Base memory map
1705 configuration.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001706
Soby Mathewecd94ad2018-05-09 13:59:29 +01001707- ``fvp-base-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001708
David Cunado7c032642018-03-12 18:47:05 +00001709 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1710 affinities and with Base memory map configuration and Linux GICv3 support.
1711
Soby Mathewecd94ad2018-05-09 13:59:29 +01001712- ``fvp-base-gicv3-psci-1t.dts``
David Cunado7c032642018-03-12 18:47:05 +00001713
1714 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1715 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1716
Soby Mathewecd94ad2018-05-09 13:59:29 +01001717- ``fvp-base-gicv3-psci-dynamiq.dts``
David Cunado7c032642018-03-12 18:47:05 +00001718
1719 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1720 single cluster, single threaded CPUs, Base memory map configuration and Linux
1721 GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001722
Soby Mathewecd94ad2018-05-09 13:59:29 +01001723- ``fvp-base-gicv3-psci-aarch32.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001724
David Cunado7c032642018-03-12 18:47:05 +00001725 For use with models such as the Cortex-A32 Base FVPs without shifted
1726 affinities and running Linux in AArch32 state with Base memory map
1727 configuration and Linux GICv3 support.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001728
Soby Mathewecd94ad2018-05-09 13:59:29 +01001729- ``fvp-foundation-gicv2-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001730
1731 For use with Foundation FVP with Base memory map configuration.
1732
Soby Mathewecd94ad2018-05-09 13:59:29 +01001733- ``fvp-foundation-gicv3-psci.dts``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001734
1735 (Default) For use with Foundation FVP with Base memory map configuration
1736 and Linux GICv3 support.
1737
1738Running on the Foundation FVP with reset to BL1 entrypoint
1739~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1740
1741The following ``Foundation_Platform`` parameters should be used to boot Linux with
Dan Handley610e7e12018-03-01 18:44:00 +000017424 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001743
1744::
1745
1746 <path-to>/Foundation_Platform \
1747 --cores=4 \
Antonio Nino Diazb44eda52018-02-23 11:01:31 +00001748 --arm-v8.0 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001749 --secure-memory \
1750 --visualization \
1751 --gicv3 \
1752 --data="<path-to>/<bl1-binary>"@0x0 \
1753 --data="<path-to>/<FIP-binary>"@0x08000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001754 --data="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001755 --data="<path-to>/<ramdisk-binary>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001756
1757Notes:
1758
1759- BL1 is loaded at the start of the Trusted ROM.
1760- The Firmware Image Package is loaded at the start of NOR FLASH0.
Soby Mathewecd94ad2018-05-09 13:59:29 +01001761- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1762 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001763- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1764 and enable the GICv3 device in the model. Note that without this option,
1765 the Foundation FVP defaults to legacy (Versatile Express) memory map which
Dan Handley610e7e12018-03-01 18:44:00 +00001766 is not supported by TF-A.
1767- In order for TF-A to run correctly on the Foundation FVP, the architecture
1768 versions must match. The Foundation FVP defaults to the highest v8.x
1769 version it supports but the default build for TF-A is for v8.0. To avoid
1770 issues either start the Foundation FVP to use v8.0 architecture using the
1771 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1772 ``ARM_ARCH_MINOR``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001773
1774Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1775~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1776
David Cunado7c032642018-03-12 18:47:05 +00001777The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001778with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001779
1780::
1781
David Cunado7c032642018-03-12 18:47:05 +00001782 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001783 -C pctl.startup=0.0.0.0 \
1784 -C bp.secure_memory=1 \
1785 -C bp.tzc_400.diagnostics=1 \
1786 -C cluster0.NUM_CORES=4 \
1787 -C cluster1.NUM_CORES=4 \
1788 -C cache_state_modelled=1 \
1789 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1790 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001791 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001792 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001793
1794Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1795~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1796
1797The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001798with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001799
1800::
1801
1802 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1803 -C pctl.startup=0.0.0.0 \
1804 -C bp.secure_memory=1 \
1805 -C bp.tzc_400.diagnostics=1 \
1806 -C cluster0.NUM_CORES=4 \
1807 -C cluster1.NUM_CORES=4 \
1808 -C cache_state_modelled=1 \
1809 -C cluster0.cpu0.CONFIG64=0 \
1810 -C cluster0.cpu1.CONFIG64=0 \
1811 -C cluster0.cpu2.CONFIG64=0 \
1812 -C cluster0.cpu3.CONFIG64=0 \
1813 -C cluster1.cpu0.CONFIG64=0 \
1814 -C cluster1.cpu1.CONFIG64=0 \
1815 -C cluster1.cpu2.CONFIG64=0 \
1816 -C cluster1.cpu3.CONFIG64=0 \
1817 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1818 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001819 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001820 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001821
1822Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1823~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1824
1825The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001826boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001827
1828::
1829
1830 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1831 -C pctl.startup=0.0.0.0 \
1832 -C bp.secure_memory=1 \
1833 -C bp.tzc_400.diagnostics=1 \
1834 -C cache_state_modelled=1 \
1835 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1836 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001837 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001838 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001839
1840Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1841~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1842
1843The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001844boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001845
1846::
1847
1848 <path-to>/FVP_Base_Cortex-A32x4 \
1849 -C pctl.startup=0.0.0.0 \
1850 -C bp.secure_memory=1 \
1851 -C bp.tzc_400.diagnostics=1 \
1852 -C cache_state_modelled=1 \
1853 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1854 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001855 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001856 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001857
1858Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1859~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1860
David Cunado7c032642018-03-12 18:47:05 +00001861The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001862with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001863
1864::
1865
David Cunado7c032642018-03-12 18:47:05 +00001866 <path-to>/FVP_Base_RevC-2xAEMv8A \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001867 -C pctl.startup=0.0.0.0 \
1868 -C bp.secure_memory=1 \
1869 -C bp.tzc_400.diagnostics=1 \
1870 -C cluster0.NUM_CORES=4 \
1871 -C cluster1.NUM_CORES=4 \
1872 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001873 -C cluster0.cpu0.RVBAR=0x04020000 \
1874 -C cluster0.cpu1.RVBAR=0x04020000 \
1875 -C cluster0.cpu2.RVBAR=0x04020000 \
1876 -C cluster0.cpu3.RVBAR=0x04020000 \
1877 -C cluster1.cpu0.RVBAR=0x04020000 \
1878 -C cluster1.cpu1.RVBAR=0x04020000 \
1879 -C cluster1.cpu2.RVBAR=0x04020000 \
1880 -C cluster1.cpu3.RVBAR=0x04020000 \
1881 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001882 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
1883 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001884 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001885 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001886 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001887
1888Notes:
1889
1890- Since a FIP is not loaded when using BL31 as reset entrypoint, the
1891 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
1892 parameter is needed to load the individual bootloader images in memory.
1893 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
Soby Mathewecd94ad2018-05-09 13:59:29 +01001894 Payload. For the same reason, the FDT needs to be compiled from the DT source
1895 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
1896 parameter.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001897
1898- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
1899 X and Y are the cluster and CPU numbers respectively, is used to set the
1900 reset vector for each core.
1901
1902- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
1903 changing the value of
1904 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
1905 ``BL32_BASE``.
1906
1907Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1908~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1909
1910The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
Dan Handley610e7e12018-03-01 18:44:00 +00001911with 8 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001912
1913::
1914
1915 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1916 -C pctl.startup=0.0.0.0 \
1917 -C bp.secure_memory=1 \
1918 -C bp.tzc_400.diagnostics=1 \
1919 -C cluster0.NUM_CORES=4 \
1920 -C cluster1.NUM_CORES=4 \
1921 -C cache_state_modelled=1 \
1922 -C cluster0.cpu0.CONFIG64=0 \
1923 -C cluster0.cpu1.CONFIG64=0 \
1924 -C cluster0.cpu2.CONFIG64=0 \
1925 -C cluster0.cpu3.CONFIG64=0 \
1926 -C cluster1.cpu0.CONFIG64=0 \
1927 -C cluster1.cpu1.CONFIG64=0 \
1928 -C cluster1.cpu2.CONFIG64=0 \
1929 -C cluster1.cpu3.CONFIG64=0 \
1930 -C cluster0.cpu0.RVBAR=0x04001000 \
1931 -C cluster0.cpu1.RVBAR=0x04001000 \
1932 -C cluster0.cpu2.RVBAR=0x04001000 \
1933 -C cluster0.cpu3.RVBAR=0x04001000 \
1934 -C cluster1.cpu0.RVBAR=0x04001000 \
1935 -C cluster1.cpu1.RVBAR=0x04001000 \
1936 -C cluster1.cpu2.RVBAR=0x04001000 \
1937 -C cluster1.cpu3.RVBAR=0x04001000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001938 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001939 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001940 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001941 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001942 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001943
1944Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
1945It should match the address programmed into the RVBAR register as well.
1946
1947Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
1948~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1949
1950The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001951boot Linux with 8 CPUs using the AArch64 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001952
1953::
1954
1955 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1956 -C pctl.startup=0.0.0.0 \
1957 -C bp.secure_memory=1 \
1958 -C bp.tzc_400.diagnostics=1 \
1959 -C cache_state_modelled=1 \
Qixiang Xua5f72812017-08-31 11:45:32 +08001960 -C cluster0.cpu0.RVBARADDR=0x04020000 \
1961 -C cluster0.cpu1.RVBARADDR=0x04020000 \
1962 -C cluster0.cpu2.RVBARADDR=0x04020000 \
1963 -C cluster0.cpu3.RVBARADDR=0x04020000 \
1964 -C cluster1.cpu0.RVBARADDR=0x04020000 \
1965 -C cluster1.cpu1.RVBARADDR=0x04020000 \
1966 -C cluster1.cpu2.RVBARADDR=0x04020000 \
1967 -C cluster1.cpu3.RVBARADDR=0x04020000 \
1968 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001969 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001970 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001971 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001972 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001973 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001974
1975Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
1976~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1977
1978The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
Dan Handley610e7e12018-03-01 18:44:00 +00001979boot Linux with 4 CPUs using the AArch32 build of TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001980
1981::
1982
1983 <path-to>/FVP_Base_Cortex-A32x4 \
1984 -C pctl.startup=0.0.0.0 \
1985 -C bp.secure_memory=1 \
1986 -C bp.tzc_400.diagnostics=1 \
1987 -C cache_state_modelled=1 \
1988 -C cluster0.cpu0.RVBARADDR=0x04001000 \
1989 -C cluster0.cpu1.RVBARADDR=0x04001000 \
1990 -C cluster0.cpu2.RVBARADDR=0x04001000 \
1991 -C cluster0.cpu3.RVBARADDR=0x04001000 \
Soby Mathewaf14b462018-06-01 16:53:38 +01001992 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001993 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001994 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001995 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01001996 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001997
1998Running the software on Juno
1999----------------------------
2000
Dan Handley610e7e12018-03-01 18:44:00 +00002001This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002002
2003To execute the software stack on Juno, the version of the Juno board recovery
2004image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2005earlier version installed or are unsure which version is installed, please
2006re-install the recovery image by following the
2007`Instructions for using Linaro's deliverables on Juno`_.
2008
Dan Handley610e7e12018-03-01 18:44:00 +00002009Preparing TF-A images
2010~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002011
Dan Handley610e7e12018-03-01 18:44:00 +00002012After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2013``SOFTWARE/`` directory of the Juno SD card.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002014
2015Other Juno software information
2016~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2017
Dan Handley610e7e12018-03-01 18:44:00 +00002018Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002019software information. Please also refer to the `Juno Getting Started Guide`_ to
Dan Handley610e7e12018-03-01 18:44:00 +00002020get more detailed information about the Juno Arm development platform and how to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002021configure it.
2022
2023Testing SYSTEM SUSPEND on Juno
2024~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2025
2026The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2027to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2028on Juno, at the linux shell prompt, issue the following command:
2029
2030::
2031
2032 echo +10 > /sys/class/rtc/rtc0/wakealarm
2033 echo -n mem > /sys/power/state
2034
2035The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2036wakeup interrupt from RTC.
2037
2038--------------
2039
Dan Handley610e7e12018-03-01 18:44:00 +00002040*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002041
David Cunadob2de0992017-06-29 12:01:33 +01002042.. _Linaro: `Linaro Release Notes`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002043.. _Linaro Release: `Linaro Release Notes`_
David Cunado82509be2017-12-19 16:33:25 +00002044.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes
David Cunado82509be2017-12-19 16:33:25 +00002045.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables
2046.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
Dan Handley610e7e12018-03-01 18:44:00 +00002047.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002048.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
Sandrine Bailleux771535b2018-09-20 10:27:13 +02002049.. _Linux master tree: https://github.com/torvalds/linux/tree/master/
Antonio Nino Diazb5d68092017-05-23 11:49:22 +01002050.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002051.. _here: psci-lib-integration-guide.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002052.. _Trusted Board Boot: trusted-board-boot.rst
Soby Mathewecd94ad2018-05-09 13:59:29 +01002053.. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002054.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002055.. _Firmware Update: firmware-update.rst
2056.. _Firmware Design: firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002057.. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2058.. _mbed TLS Security Center: https://tls.mbed.org/security
Dan Handley610e7e12018-03-01 18:44:00 +00002059.. _Arm's website: `FVP models`_
Eleanor Bonnicic61b22e2017-07-07 14:33:24 +01002060.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002061.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
David Cunadob2de0992017-06-29 12:01:33 +01002062.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Sandrine Bailleux604f0a42018-09-20 12:44:39 +02002063.. _Secure Partition Manager Design guide: secure-partition-manager-design.rst