Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 31 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 32 | #include <assert.h> |
| 33 | #include <bl_common.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | #include <console.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 35 | #include <mmio.h> |
| 36 | #include <platform.h> |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 37 | #include <platform_def.h> |
| 38 | #include "fvp_def.h" |
| 39 | #include "fvp_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
| 41 | /******************************************************************************* |
| 42 | * Declarations of linker defined symbols which will help us find the layout |
| 43 | * of trusted SRAM |
| 44 | ******************************************************************************/ |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 45 | extern unsigned long __COHERENT_RAM_START__; |
| 46 | extern unsigned long __COHERENT_RAM_END__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 47 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 48 | extern unsigned long __BL1_RAM_START__; |
| 49 | extern unsigned long __BL1_RAM_END__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 50 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 51 | /* |
| 52 | * The next 2 constants identify the extents of the coherent memory region. |
| 53 | * These addresses are used by the MMU setup code and therefore they must be |
| 54 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 55 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to |
| 56 | * page-aligned addresses. |
| 57 | */ |
| 58 | #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 59 | #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 60 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 61 | #define BL1_RAM_BASE (unsigned long)(&__BL1_RAM_START__) |
| 62 | #define BL1_RAM_LIMIT (unsigned long)(&__BL1_RAM_END__) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 63 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 64 | |
| 65 | /* Data structure which holds the extents of the trusted SRAM for BL1*/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 66 | static meminfo_t bl1_tzram_layout; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 67 | |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 68 | meminfo_t *bl1_plat_sec_mem_layout(void) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 69 | { |
Sandrine Bailleux | ee12f6f | 2013-11-28 14:55:58 +0000 | [diff] [blame] | 70 | return &bl1_tzram_layout; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | /******************************************************************************* |
| 74 | * Perform any BL1 specific platform actions. |
| 75 | ******************************************************************************/ |
| 76 | void bl1_early_platform_setup(void) |
| 77 | { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 78 | const unsigned long bl1_ram_base = BL1_RAM_BASE; |
| 79 | const unsigned long bl1_ram_limit = BL1_RAM_LIMIT; |
| 80 | const unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 81 | |
Vikram Kanigiri | 3684abf | 2014-03-27 14:33:15 +0000 | [diff] [blame] | 82 | /* Initialize the console to provide early debug support */ |
| 83 | console_init(PL011_UART0_BASE); |
| 84 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 85 | /* |
| 86 | * Calculate how much ram is BL1 using & how much remains free. |
| 87 | * This also includes a rudimentary mechanism to detect whether |
| 88 | * the BL1 data is loaded at the top or bottom of memory. |
| 89 | * TODO: add support for discontigous chunks of free ram if |
| 90 | * needed. Might need dynamic memory allocation support |
| 91 | * et al. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 92 | */ |
| 93 | bl1_tzram_layout.total_base = TZRAM_BASE; |
| 94 | bl1_tzram_layout.total_size = TZRAM_SIZE; |
| 95 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 96 | if (bl1_ram_limit == tzram_limit) { |
| 97 | /* BL1 has been loaded at the top of memory. */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 98 | bl1_tzram_layout.free_base = TZRAM_BASE; |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 99 | bl1_tzram_layout.free_size = bl1_ram_base - TZRAM_BASE; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 100 | } else { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 101 | /* BL1 has been loaded at the bottom of memory. */ |
| 102 | bl1_tzram_layout.free_base = bl1_ram_limit; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 103 | bl1_tzram_layout.free_size = |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 104 | tzram_limit - bl1_ram_limit; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 105 | } |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 106 | |
| 107 | /* Initialize the platform config for future decision making */ |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 108 | fvp_config_setup(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | /******************************************************************************* |
| 112 | * Function which will evaluate how much of the trusted ram has been gobbled |
| 113 | * up by BL1 and return the base and size of whats available for loading BL2. |
| 114 | * Its called after coherency and the MMU have been turned on. |
| 115 | ******************************************************************************/ |
| 116 | void bl1_platform_setup(void) |
| 117 | { |
James Morrissey | 9d72b4e | 2014-02-10 17:04:32 +0000 | [diff] [blame] | 118 | /* Initialise the IO layer and register platform IO devices */ |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 119 | fvp_io_setup(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 120 | } |
| 121 | |
James Morrissey | 9d72b4e | 2014-02-10 17:04:32 +0000 | [diff] [blame] | 122 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 123 | /******************************************************************************* |
| 124 | * Perform the very early platform specific architecture setup here. At the |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 125 | * moment this only does basic initialization. Later architectural setup |
| 126 | * (bl1_arch_setup()) does not do anything platform specific. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 127 | ******************************************************************************/ |
| 128 | void bl1_plat_arch_setup(void) |
| 129 | { |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 130 | fvp_cci_setup(); |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 131 | |
Dan Handley | ea45157 | 2014-05-15 14:53:30 +0100 | [diff] [blame] | 132 | fvp_configure_mmu_el3(bl1_tzram_layout.total_base, |
| 133 | bl1_tzram_layout.total_size, |
| 134 | TZROM_BASE, |
| 135 | TZROM_BASE + TZROM_SIZE, |
| 136 | BL1_COHERENT_RAM_BASE, |
| 137 | BL1_COHERENT_RAM_LIMIT); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 138 | } |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 139 | |
| 140 | |
| 141 | /******************************************************************************* |
| 142 | * Before calling this function BL2 is loaded in memory and its entrypoint |
| 143 | * is set by load_image. This is a placeholder for the platform to change |
| 144 | * the entrypoint of BL2 and set SPSR and security state. |
| 145 | * On FVP we are only setting the security state, entrypoint |
| 146 | ******************************************************************************/ |
| 147 | void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, |
| 148 | entry_point_info_t *bl2_ep) |
| 149 | { |
| 150 | SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); |
| 151 | bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 152 | } |