blob: 5b3d4c26f710f780ef54e3bd189f3bd377300951 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Daniel Boulby60786e72021-10-22 11:37:34 +01002 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00007#ifndef ARCH_HELPERS_H
8#define ARCH_HELPERS_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000010#include <cdefs.h>
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000011#include <stdbool.h>
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010012#include <stdint.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010013#include <string.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010014
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <arch.h>
16
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010017/**********************************************************************
18 * Macros which create inline functions to read or write CPU system
19 * registers
20 *********************************************************************/
21
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000022#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090023static inline u_register_t read_ ## _name(void) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000024{ \
Masahiro Yamada6292d772018-02-02 21:19:17 +090025 u_register_t v; \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000026 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
27 return v; \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010028}
29
Andre Przywara23b57bb2022-11-14 10:39:48 +000030#define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \
31static inline u_register_t read_ ## _name(void) \
32{ \
33 u_register_t v; \
34 __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \
35 return v; \
36}
37
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000038#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090039static inline void write_ ## _name(u_register_t v) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000040{ \
41 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010042}
43
Roberto Vargasc51cdb72017-09-18 09:53:25 +010044#define SYSREG_WRITE_CONST(reg_name, v) \
45 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010046
47/* Define read function for system register */
48#define DEFINE_SYSREG_READ_FUNC(_name) \
49 _DEFINE_SYSREG_READ_FUNC(_name, _name)
50
51/* Define read & write function for system register */
52#define DEFINE_SYSREG_RW_FUNCS(_name) \
53 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
54 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
55
56/* Define read & write function for renamed system register */
57#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
58 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
60
Achin Gupta92712a52015-09-03 14:18:02 +010061/* Define read function for renamed system register */
62#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
63 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
64
65/* Define write function for renamed system register */
66#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
67 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
68
Andre Przywara23b57bb2022-11-14 10:39:48 +000069/* Define read function for ID register (w/o volatile qualifier) */
70#define DEFINE_IDREG_READ_FUNC(_name) \
71 _DEFINE_SYSREG_READ_FUNC_NV(_name, _name)
72
73/* Define read function for renamed ID register (w/o volatile qualifier) */
74#define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \
75 _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name)
76
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010077/**********************************************************************
78 * Macros to create inline functions for system instructions
79 *********************************************************************/
80
81/* Define function for simple system instruction */
82#define DEFINE_SYSOP_FUNC(_op) \
Juan Castillo2d552402014-06-13 17:05:10 +010083static inline void _op(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010084{ \
85 __asm__ (#_op); \
86}
87
Alexei Fedorovb8f26e92020-02-06 17:11:03 +000088/* Define function for system instruction with register parameter */
89#define DEFINE_SYSOP_PARAM_FUNC(_op) \
90static inline void _op(uint64_t v) \
91{ \
92 __asm__ (#_op " %0" : : "r" (v)); \
93}
94
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010095/* Define function for system instruction with type specifier */
96#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
Juan Castillo2d552402014-06-13 17:05:10 +010097static inline void _op ## _type(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010098{ \
Andre Przywara5c29cba2020-10-16 18:19:03 +010099 __asm__ (#_op " " #_type : : : "memory"); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100100}
101
102/* Define function for system instruction with register parameter */
103#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
104static inline void _op ## _type(uint64_t v) \
105{ \
106 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
107}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100108
109/*******************************************************************************
110 * TLB maintenance accessor prototypes
111 ******************************************************************************/
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000112
Soby Mathew16d006b2019-05-03 13:17:56 +0100113#if ERRATA_A57_813419 || ERRATA_A76_1286807
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000114/*
115 * Define function for TLBI instruction with type specifier that implements
Soby Mathew16d006b2019-05-03 13:17:56 +0100116 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
117 * Cortex-A76.
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000118 */
Soby Mathew16d006b2019-05-03 13:17:56 +0100119#define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000120static inline void tlbi ## _type(void) \
121{ \
122 __asm__("tlbi " #_type "\n" \
123 "dsb ish\n" \
124 "tlbi " #_type); \
125}
126
127/*
128 * Define function for TLBI instruction with register parameter that implements
Soby Mathew16d006b2019-05-03 13:17:56 +0100129 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
130 * Cortex-A76.
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000131 */
Soby Mathew16d006b2019-05-03 13:17:56 +0100132#define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000133static inline void tlbi ## _type(uint64_t v) \
134{ \
135 __asm__("tlbi " #_type ", %0\n" \
136 "dsb ish\n" \
137 "tlbi " #_type ", %0" : : "r" (v)); \
138}
139#endif /* ERRATA_A57_813419 */
140
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000141#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
142/*
143 * Define function for DC instruction with register parameter that enables
144 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
145 */
146#define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \
147static inline void dc ## _name(uint64_t v) \
148{ \
149 __asm__("dc " #_type ", %0" : : "r" (v)); \
150}
151#endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
152
Soby Mathew16d006b2019-05-03 13:17:56 +0100153#if ERRATA_A57_813419
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100154DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
155DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
156DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
157DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
Soby Mathew16d006b2019-05-03 13:17:56 +0100158DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
159DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
160DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
161#elif ERRATA_A76_1286807
162DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1)
163DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is)
164DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2)
165DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is)
166DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
167DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
168DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000169#else
Soby Mathew16d006b2019-05-03 13:17:56 +0100170DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
171DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
172DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
173DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100174DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
175DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
176DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
Soby Mathew16d006b2019-05-03 13:17:56 +0100177#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178
Soby Mathew16d006b2019-05-03 13:17:56 +0100179#if ERRATA_A57_813419
Antonio Nino Diazac998032017-02-27 17:23:54 +0000180DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
181DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
182DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
183DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
Soby Mathew16d006b2019-05-03 13:17:56 +0100184DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
185DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
186#elif ERRATA_A76_1286807
187DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is)
188DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is)
189DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is)
190DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is)
191DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
192DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000193#else
Soby Mathew16d006b2019-05-03 13:17:56 +0100194DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
195DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
196DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
197DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000198DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
199DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000200#endif
Antonio Nino Diazac998032017-02-27 17:23:54 +0000201
Achin Gupta4f6ad662013-10-25 09:08:21 +0100202/*******************************************************************************
203 * Cache maintenance accessor prototypes
204 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100205DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
206DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000207#if ERRATA_A53_827319
208DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
209#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100210DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000211#endif
212#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
213DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
214#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100215DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000216#endif
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100217DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
218DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000219#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
220DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
221#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100222DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000223#endif
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100224DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
225
Varun Wadekar97625e32015-03-13 14:59:03 +0530226/*******************************************************************************
227 * Address translation accessor prototypes
228 ******************************************************************************/
229DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
230DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
231DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
232DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
Douglas Raillard77414632018-08-21 12:54:45 +0100233DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100234DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
Douglas Raillard77414632018-08-21 12:54:45 +0100235DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
Varun Wadekar97625e32015-03-13 14:59:03 +0530236
Alexei Fedorovb8f26e92020-02-06 17:11:03 +0000237/*******************************************************************************
238 * Strip Pointer Authentication Code
239 ******************************************************************************/
240DEFINE_SYSOP_PARAM_FUNC(xpaci)
241
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000242void flush_dcache_range(uintptr_t addr, size_t size);
Robert Wakim48e6b572021-10-21 15:39:56 +0100243void flush_dcache_to_popa_range(uintptr_t addr, size_t size);
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000244void clean_dcache_range(uintptr_t addr, size_t size);
245void inv_dcache_range(uintptr_t addr, size_t size);
Masahiro Yamada019b4f82020-04-02 15:35:19 +0900246bool is_dcache_enabled(void);
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000247
248void dcsw_op_louis(u_register_t op_type);
249void dcsw_op_all(u_register_t op_type);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100250
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100251void disable_mmu_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100252void disable_mmu_el3(void);
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600253void disable_mpu_el2(void);
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100254void disable_mmu_icache_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100255void disable_mmu_icache_el3(void);
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600256void disable_mpu_icache_el2(void);
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100257
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258/*******************************************************************************
259 * Misc. accessor prototypes
260 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100261
Roberto Vargasc51cdb72017-09-18 09:53:25 +0100262#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
263#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000265DEFINE_SYSREG_RW_FUNCS(par_el1)
Andre Przywara23b57bb2022-11-14 10:39:48 +0000266DEFINE_IDREG_READ_FUNC(id_pfr1_el1)
267DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1)
268DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1)
269DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1)
270DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1)
271DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1)
272DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1)
273DEFINE_IDREG_READ_FUNC(id_afr0_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100274DEFINE_SYSREG_READ_FUNC(CurrentEl)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000275DEFINE_SYSREG_READ_FUNC(ctr_el0)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100276DEFINE_SYSREG_RW_FUNCS(daif)
277DEFINE_SYSREG_RW_FUNCS(spsr_el1)
278DEFINE_SYSREG_RW_FUNCS(spsr_el2)
279DEFINE_SYSREG_RW_FUNCS(spsr_el3)
280DEFINE_SYSREG_RW_FUNCS(elr_el1)
281DEFINE_SYSREG_RW_FUNCS(elr_el2)
282DEFINE_SYSREG_RW_FUNCS(elr_el3)
Venkatesh Yadav Abbarapuf80014d2020-11-27 02:58:24 -0700283DEFINE_SYSREG_RW_FUNCS(mdccsr_el0)
284DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0)
285DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0)
Manish Pandeycabcad52022-06-23 10:43:31 +0100286DEFINE_SYSREG_RW_FUNCS(sp_el1)
287DEFINE_SYSREG_RW_FUNCS(sp_el2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100288
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100289DEFINE_SYSOP_FUNC(wfi)
290DEFINE_SYSOP_FUNC(wfe)
291DEFINE_SYSOP_FUNC(sev)
292DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
Soby Mathewed995662014-12-30 16:11:42 +0000293DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Juan Castillo2e86cb12016-01-13 15:01:09 +0000294DEFINE_SYSOP_TYPE_FUNC(dmb, st)
295DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Soby Mathewed995662014-12-30 16:11:42 +0000296DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Robert Wakim48e6b572021-10-21 15:39:56 +0100297DEFINE_SYSOP_TYPE_FUNC(dsb, osh)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100298DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000299DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Robert Wakim48e6b572021-10-21 15:39:56 +0100300DEFINE_SYSOP_TYPE_FUNC(dsb, oshst)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000301DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
302DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
303DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
304DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
305DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
306DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
307DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100308DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000309DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100310DEFINE_SYSOP_FUNC(isb)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100311
Antonio Nino Diazb4e3e4b2018-11-23 15:04:01 +0000312static inline void enable_irq(void)
313{
314 /*
315 * The compiler memory barrier will prevent the compiler from
316 * scheduling non-volatile memory access after the write to the
317 * register.
318 *
319 * This could happen if some initialization code issues non-volatile
320 * accesses to an area used by an interrupt handler, in the assumption
321 * that it is safe as the interrupts are disabled at the time it does
322 * that (according to program order). However, non-volatile accesses
323 * are not necessarily in program order relatively with volatile inline
324 * assembly statements (and volatile accesses).
325 */
326 COMPILER_BARRIER();
327 write_daifclr(DAIF_IRQ_BIT);
328 isb();
329}
330
331static inline void enable_fiq(void)
332{
333 COMPILER_BARRIER();
334 write_daifclr(DAIF_FIQ_BIT);
335 isb();
336}
337
338static inline void enable_serror(void)
339{
340 COMPILER_BARRIER();
341 write_daifclr(DAIF_ABT_BIT);
342 isb();
343}
344
345static inline void enable_debug_exceptions(void)
346{
347 COMPILER_BARRIER();
348 write_daifclr(DAIF_DBG_BIT);
349 isb();
350}
351
352static inline void disable_irq(void)
353{
354 COMPILER_BARRIER();
355 write_daifset(DAIF_IRQ_BIT);
356 isb();
357}
358
359static inline void disable_fiq(void)
360{
361 COMPILER_BARRIER();
362 write_daifset(DAIF_FIQ_BIT);
363 isb();
364}
365
366static inline void disable_serror(void)
367{
368 COMPILER_BARRIER();
369 write_daifset(DAIF_ABT_BIT);
370 isb();
371}
372
373static inline void disable_debug_exceptions(void)
374{
375 COMPILER_BARRIER();
376 write_daifset(DAIF_DBG_BIT);
377 isb();
378}
379
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100380void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
381 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100382
383/*******************************************************************************
384 * System register accessor prototypes
385 ******************************************************************************/
Andre Przywara23b57bb2022-11-14 10:39:48 +0000386DEFINE_IDREG_READ_FUNC(midr_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100387DEFINE_SYSREG_READ_FUNC(mpidr_el1)
Andre Przywara23b57bb2022-11-14 10:39:48 +0000388DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1)
389DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100390
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100391DEFINE_SYSREG_RW_FUNCS(scr_el3)
392DEFINE_SYSREG_RW_FUNCS(hcr_el2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100393
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100394DEFINE_SYSREG_RW_FUNCS(vbar_el1)
395DEFINE_SYSREG_RW_FUNCS(vbar_el2)
396DEFINE_SYSREG_RW_FUNCS(vbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100397
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100398DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
399DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
400DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100402DEFINE_SYSREG_RW_FUNCS(actlr_el1)
403DEFINE_SYSREG_RW_FUNCS(actlr_el2)
404DEFINE_SYSREG_RW_FUNCS(actlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100405
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100406DEFINE_SYSREG_RW_FUNCS(esr_el1)
407DEFINE_SYSREG_RW_FUNCS(esr_el2)
408DEFINE_SYSREG_RW_FUNCS(esr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100409
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100410DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
411DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
412DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100413
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100414DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
415DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
416DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100417
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100418DEFINE_SYSREG_RW_FUNCS(far_el1)
419DEFINE_SYSREG_RW_FUNCS(far_el2)
420DEFINE_SYSREG_RW_FUNCS(far_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100421
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100422DEFINE_SYSREG_RW_FUNCS(mair_el1)
423DEFINE_SYSREG_RW_FUNCS(mair_el2)
424DEFINE_SYSREG_RW_FUNCS(mair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100425
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100426DEFINE_SYSREG_RW_FUNCS(amair_el1)
427DEFINE_SYSREG_RW_FUNCS(amair_el2)
428DEFINE_SYSREG_RW_FUNCS(amair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100429
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100430DEFINE_SYSREG_READ_FUNC(rvbar_el1)
431DEFINE_SYSREG_READ_FUNC(rvbar_el2)
432DEFINE_SYSREG_READ_FUNC(rvbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100433
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100434DEFINE_SYSREG_RW_FUNCS(rmr_el1)
435DEFINE_SYSREG_RW_FUNCS(rmr_el2)
436DEFINE_SYSREG_RW_FUNCS(rmr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100437
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100438DEFINE_SYSREG_RW_FUNCS(tcr_el1)
439DEFINE_SYSREG_RW_FUNCS(tcr_el2)
440DEFINE_SYSREG_RW_FUNCS(tcr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100441
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100442DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
443DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
444DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100445
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100446DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100447
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000448DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
449
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100450DEFINE_SYSREG_RW_FUNCS(cptr_el2)
451DEFINE_SYSREG_RW_FUNCS(cptr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100452
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100453DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
454DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000455DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
456DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
457DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100458DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
459DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
460DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000461DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
462DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
463DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100464DEFINE_SYSREG_READ_FUNC(cntpct_el0)
465DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100466
Manish Pandey5693afe2021-10-06 17:28:09 +0100467DEFINE_SYSREG_RW_FUNCS(vtcr_el2)
468
Antonio Nino Diazdc4ed3d2018-11-23 13:54:00 +0000469#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
470 CNTP_CTL_ENABLE_MASK)
471#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
472 CNTP_CTL_IMASK_MASK)
473#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
474 CNTP_CTL_ISTATUS_MASK)
475
476#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
477#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
478
479#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
480#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
481
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100482DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100483
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100484DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
485
Andrew Thoelke4e126072014-06-04 21:10:52 +0100486DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
487DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
488
Soby Mathew26fb90e2015-01-06 21:36:55 +0000489DEFINE_SYSREG_READ_FUNC(isr_el1)
490
David Cunado5f55e282016-10-31 17:37:34 +0000491DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100492DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
David Cunadoc14b08e2016-11-25 00:21:59 +0000493DEFINE_SYSREG_RW_FUNCS(hstr_el2)
David Cunado4168f2f2017-10-02 17:41:39 +0100494DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
David Cunado5f55e282016-10-31 17:37:34 +0000495
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000496/* GICv3 System Registers */
497
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100498DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
499DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
500DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
501DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100502DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100503DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000504DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100505DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
506DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
507DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
508DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
509DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
510DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
511DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100512DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000513DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
Florian Lugoud4e25032021-09-08 12:40:24 +0200514DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100515
Alexei Fedorov7e6306b2020-07-14 08:17:56 +0100516DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)
517DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0)
johpow01fa59c6f2020-10-02 13:41:11 -0500518DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0)
519DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100520DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
521DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
522DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
523DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
524
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100525DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100526
David Cunadoce88eee2017-10-20 11:30:57 +0100527DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
528DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
529
Andre Przywara23b57bb2022-11-14 10:39:48 +0000530DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
johpow019baade32021-07-08 14:14:00 -0500531DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3)
532
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000533DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
534DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
535
536DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
537DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
538DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
539DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
540DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
541DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
542
Andre Przywara902c9022022-11-17 17:30:43 +0000543DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
544
Andre Przywara98908b32022-11-17 16:42:09 +0000545/* Armv8.1 VHE Registers */
546DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
547DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2)
548
Andre Przywara84b86532022-11-17 16:42:09 +0000549/* Armv8.2 ID Registers */
Andre Przywara23b57bb2022-11-14 10:39:48 +0000550DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000551
Andre Przywara870627e2023-01-27 12:25:49 +0000552/* Armv8.2 RAS Registers */
553DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2)
554DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2)
555
Andre Przywara84b86532022-11-17 16:42:09 +0000556/* Armv8.2 MPAM Registers */
557DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
558DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
559DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
560DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
561DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm0_el2, MPAMVPM0_EL2)
562DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm1_el2, MPAMVPM1_EL2)
563DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm2_el2, MPAMVPM2_EL2)
564DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm3_el2, MPAMVPM3_EL2)
565DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm4_el2, MPAMVPM4_EL2)
566DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm5_el2, MPAMVPM5_EL2)
567DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm6_el2, MPAMVPM6_EL2)
568DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm7_el2, MPAMVPM7_EL2)
569DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpmv_el2, MPAMVPMV_EL2)
570
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000571/* Armv8.3 Pointer Authentication Registers */
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000572DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
573DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000574
Daniel Boulby60786e72021-10-22 11:37:34 +0100575/* Armv8.4 Data Independent Timing Register */
576DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
577
Andre Przywara06ea44e2022-11-17 17:30:43 +0000578/* Armv8.4 FEAT_TRF Register */
579DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000580DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
Andre Przywara06ea44e2022-11-17 17:30:43 +0000581
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100582/* Armv8.5 MTE Registers */
583DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
584DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
585DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
586DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
587
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000588/* Armv8.5 FEAT_RNG Registers */
Andre Przywarabdc76f12022-11-21 17:07:25 +0000589DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
590DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS)
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000591
Andre Przywara5d6d2ab2022-11-10 14:40:37 +0000592/* Armv8.6 FEAT_FGT Registers */
593DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2)
594DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2)
595DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2)
596DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2)
597DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2)
598DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2)
599
Andre Przywarac3464182022-11-17 17:30:43 +0000600/* ARMv8.6 FEAT_ECV Register */
601DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2)
602
johpow01f91e59f2021-08-04 19:38:18 -0500603/* FEAT_HCX Register */
604DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
605
Mark Brownc37eee72023-03-14 20:13:03 +0000606/* Armv8.9 system registers */
607DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1)
608
609/* FEAT_TCR2 Register */
610DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2)
611
Mark Brown293a6612023-03-14 20:48:43 +0000612/* FEAT_SxPIE Registers */
613DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2)
614DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2)
615DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2)
616
617/* FEAT_SxPOE Registers */
618DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2)
619
Mark Brown326f2952023-03-14 21:33:04 +0000620/* FEAT_GCS Registers */
621DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
622DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
623
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500624/* DynamIQ Shared Unit power management */
625DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
626
Chris Kay03be39d2021-05-05 13:38:30 +0100627/* CPU Power/Performance Management registers */
628DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3)
629DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3)
630
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500631/* Armv9.2 RME Registers */
632DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3)
633DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3)
634
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100635#define IS_IN_EL(x) \
636 (GET_EL(read_CurrentEl()) == MODE_EL##x)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100637
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100638#define IS_IN_EL1() IS_IN_EL(1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000639#define IS_IN_EL2() IS_IN_EL(2)
Douglas Raillard77414632018-08-21 12:54:45 +0100640#define IS_IN_EL3() IS_IN_EL(3)
641
642static inline unsigned int get_current_el(void)
643{
644 return GET_EL(read_CurrentEl());
645}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100646
Masahiro Yamada8a6e9612020-03-26 13:18:48 +0900647static inline unsigned int get_current_el_maybe_constant(void)
648{
649#if defined(IMAGE_AT_EL1)
650 return 1;
651#elif defined(IMAGE_AT_EL2)
652 return 2; /* no use-case in TF-A */
653#elif defined(IMAGE_AT_EL3)
654 return 3;
655#else
656 /*
657 * If we do not know which exception level this is being built for
658 * (e.g. built for library), fall back to run-time detection.
659 */
660 return get_current_el();
661#endif
662}
663
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000664/*
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000665 * Check if an EL is implemented from AA64PFR0 register fields.
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000666 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000667static inline uint64_t el_implemented(unsigned int el)
668{
669 if (el > 3U) {
670 return EL_IMPL_NONE;
671 } else {
672 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
673
674 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
675 }
676}
677
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500678/*
679 * TLBIPAALLOS instruction
680 * (TLB Inivalidate GPT Information by PA,
681 * All Entries, Outer Shareable)
682 */
683static inline void tlbipaallos(void)
684{
685 __asm__("SYS #6,c8,c1,#4");
686}
687
688/*
Robert Wakim48e6b572021-10-21 15:39:56 +0100689 * Invalidate TLBs of GPT entries by Physical address, last level.
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500690 *
691 * @pa: the starting address for the range
692 * of invalidation
693 * @size: size of the range of invalidation
694 */
Robert Wakim48e6b572021-10-21 15:39:56 +0100695void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500696
697
698/* Previously defined accessor functions with incomplete register names */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100699
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100700#define read_current_el() read_CurrentEl()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100701
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100702#define dsb() dsbsy()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100703
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100704#define read_midr() read_midr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100705
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100706#define read_mpidr() read_mpidr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100707
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100708#define read_scr() read_scr_el3()
709#define write_scr(_v) write_scr_el3(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100710
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100711#define read_hcr() read_hcr_el2()
712#define write_hcr(_v) write_hcr_el2(_v)
Sandrine Bailleux25232af2014-05-09 11:23:11 +0100713
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100714#define read_cpacr() read_cpacr_el1()
715#define write_cpacr(_v) write_cpacr_el1(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100716
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500717#define read_clusterpwrdn() read_clusterpwrdn_el1()
718#define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
719
Manish V Badarkhebde5c952020-07-14 14:43:12 +0100720#if ERRATA_SPECULATIVE_AT
721/*
722 * Assuming SCTLR.M bit is already enabled
723 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits
724 * 2. Execute AT instruction for lower EL1/0
725 * 3. Disable page table walk by setting TCR_EL1.EPDx bits
726 */
727#define AT(_at_inst, _va) \
728{ \
729 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \
730 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \
731 isb(); \
732 _at_inst(_va); \
733 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \
734 isb(); \
735}
736#else
Elyes Haouas183638f2023-02-13 10:05:41 +0100737#define AT(_at_inst, _va) _at_inst(_va)
Manish V Badarkhebde5c952020-07-14 14:43:12 +0100738#endif
739
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000740#endif /* ARCH_HELPERS_H */