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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Antonio Nino Diaz719bf852017-02-23 17:22:58 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6#include <arch.h>
7#include <arch_helpers.h>
Antonio Nino Diazf09d0032017-04-11 14:04:56 +01008#include <arm_xlat_tables.h>
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +01009#include <assert.h>
Yatharth Kochar3c0087a2016-04-14 14:49:37 +010010#include <debug.h>
Dan Handley9df48042015-03-19 18:58:55 +000011#include <mmio.h>
12#include <plat_arm.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +010013#include <platform_def.h>
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000014#include <secure_partition.h>
Dan Handley9df48042015-03-19 18:58:55 +000015
Vikram Kanigiri07035432015-11-12 18:52:34 +000016extern const mmap_region_t plat_arm_mmap[];
Dan Handley9df48042015-03-19 18:58:55 +000017
Dan Handley9df48042015-03-19 18:58:55 +000018/* Weak definitions may be overridden in specific ARM standard platform */
19#pragma weak plat_get_ns_image_entrypoint
Vikram Kanigiri07035432015-11-12 18:52:34 +000020#pragma weak plat_arm_get_mmap
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010021
22/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
23 * conflicts with the definition in plat/common. */
24#if ERROR_DEPRECATED
25#pragma weak plat_get_syscnt_freq2
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +010026#endif
Dan Handley9df48042015-03-19 18:58:55 +000027
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010028/*
29 * Set up the page tables for the generic and platform-specific memory regions.
30 * The extents of the generic memory regions are specified by the function
31 * arguments and consist of:
32 * - Trusted SRAM seen by the BL image;
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010033 * - Code section;
34 * - Read-only data section;
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010035 * - Coherent memory region, if applicable.
36 */
Soby Mathewa0fedc42016-06-16 14:52:04 +010037void arm_setup_page_tables(uintptr_t total_base,
38 size_t total_size,
39 uintptr_t code_start,
40 uintptr_t code_limit,
41 uintptr_t rodata_start,
42 uintptr_t rodata_limit
Dan Handley9df48042015-03-19 18:58:55 +000043#if USE_COHERENT_MEM
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010044 ,
Soby Mathewa0fedc42016-06-16 14:52:04 +010045 uintptr_t coh_start,
46 uintptr_t coh_limit
Dan Handley9df48042015-03-19 18:58:55 +000047#endif
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010048 )
49{
50 /*
51 * Map the Trusted SRAM with appropriate memory attributes.
52 * Subsequent mappings will adjust the attributes for specific regions.
53 */
Sandrine Bailleux12997c52016-06-20 13:57:10 +010054 VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n",
55 (void *) total_base, (void *) (total_base + total_size));
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010056 mmap_add_region(total_base, total_base,
57 total_size,
58 MT_MEMORY | MT_RW | MT_SECURE);
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010059
60 /* Re-map the code section */
Sandrine Bailleux12997c52016-06-20 13:57:10 +010061 VERBOSE("Code region: %p - %p\n",
62 (void *) code_start, (void *) code_limit);
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010063 mmap_add_region(code_start, code_start,
64 code_limit - code_start,
65 MT_CODE | MT_SECURE);
66
67 /* Re-map the read-only data section */
Sandrine Bailleux12997c52016-06-20 13:57:10 +010068 VERBOSE("Read-only data region: %p - %p\n",
69 (void *) rodata_start, (void *) rodata_limit);
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010070 mmap_add_region(rodata_start, rodata_start,
71 rodata_limit - rodata_start,
72 MT_RO_DATA | MT_SECURE);
73
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010074#if USE_COHERENT_MEM
75 /* Re-map the coherent memory region */
Sandrine Bailleux12997c52016-06-20 13:57:10 +010076 VERBOSE("Coherent region: %p - %p\n",
77 (void *) coh_start, (void *) coh_limit);
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010078 mmap_add_region(coh_start, coh_start,
79 coh_limit - coh_start,
80 MT_DEVICE | MT_RW | MT_SECURE);
81#endif
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +010082
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000083#if ENABLE_SPM && defined(IMAGE_BL31)
84 /* The address of the following region is calculated by the linker. */
85 mmap_add_region(SP_IMAGE_XLAT_TABLES_START,
86 SP_IMAGE_XLAT_TABLES_START,
87 SP_IMAGE_XLAT_TABLES_SIZE,
88 MT_MEMORY | MT_RW | MT_SECURE);
89#endif
90
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010091 /* Now (re-)map the platform-specific memory regions */
92 mmap_add(plat_arm_get_mmap());
Dan Handley9df48042015-03-19 18:58:55 +000093
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010094 /* Create the page tables to reflect the above mappings */
95 init_xlat_tables();
96}
Dan Handley9df48042015-03-19 18:58:55 +000097
Soby Mathew21f93612016-03-23 10:11:10 +000098uintptr_t plat_get_ns_image_entrypoint(void)
Dan Handley9df48042015-03-19 18:58:55 +000099{
Soby Mathew4876ae32016-05-09 17:20:10 +0100100#ifdef PRELOADED_BL33_BASE
101 return PRELOADED_BL33_BASE;
102#else
Dan Handley9df48042015-03-19 18:58:55 +0000103 return PLAT_ARM_NS_IMAGE_OFFSET;
Soby Mathew4876ae32016-05-09 17:20:10 +0100104#endif
Dan Handley9df48042015-03-19 18:58:55 +0000105}
106
107/*******************************************************************************
108 * Gets SPSR for BL32 entry
109 ******************************************************************************/
110uint32_t arm_get_spsr_for_bl32_entry(void)
111{
112 /*
113 * The Secure Payload Dispatcher service is responsible for
Juan Castillo7d199412015-12-14 09:35:25 +0000114 * setting the SPSR prior to entry into the BL32 image.
Dan Handley9df48042015-03-19 18:58:55 +0000115 */
116 return 0;
117}
118
119/*******************************************************************************
120 * Gets SPSR for BL33 entry
121 ******************************************************************************/
Soby Mathew0d268dc2016-07-11 14:13:56 +0100122#ifndef AARCH32
Dan Handley9df48042015-03-19 18:58:55 +0000123uint32_t arm_get_spsr_for_bl33_entry(void)
124{
Dan Handley9df48042015-03-19 18:58:55 +0000125 unsigned int mode;
126 uint32_t spsr;
127
128 /* Figure out what mode we enter the non-secure world in */
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000129 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1;
Dan Handley9df48042015-03-19 18:58:55 +0000130
131 /*
132 * TODO: Consider the possibility of specifying the SPSR in
133 * the FIP ToC and allowing the platform to have a say as
134 * well.
135 */
136 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
137 return spsr;
138}
Soby Mathew0d268dc2016-07-11 14:13:56 +0100139#else
140/*******************************************************************************
141 * Gets SPSR for BL33 entry
142 ******************************************************************************/
143uint32_t arm_get_spsr_for_bl33_entry(void)
144{
145 unsigned int hyp_status, mode, spsr;
146
147 hyp_status = GET_VIRT_EXT(read_id_pfr1());
148
149 mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
150
151 /*
152 * TODO: Consider the possibility of specifying the SPSR in
153 * the FIP ToC and allowing the platform to have a say as
154 * well.
155 */
156 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
157 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
158 return spsr;
159}
160#endif /* AARCH32 */
Dan Handley9df48042015-03-19 18:58:55 +0000161
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100162/*******************************************************************************
163 * Configures access to the system counter timer module.
164 ******************************************************************************/
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800165#ifdef ARM_SYS_TIMCTL_BASE
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100166void arm_configure_sys_timer(void)
167{
168 unsigned int reg_val;
169
Juan Castilloaadf19a2015-11-06 16:02:32 +0000170#if ARM_CONFIG_CNTACR
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100171 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
172 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
173 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
174 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val);
Juan Castilloaadf19a2015-11-06 16:02:32 +0000175#endif /* ARM_CONFIG_CNTACR */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100176
177 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID));
178 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val);
179}
Soren Brinkmann3d80b712016-03-06 20:23:39 -0800180#endif /* ARM_SYS_TIMCTL_BASE */
Vikram Kanigiri07035432015-11-12 18:52:34 +0000181
182/*******************************************************************************
183 * Returns ARM platform specific memory map regions.
184 ******************************************************************************/
185const mmap_region_t *plat_arm_get_mmap(void)
186{
187 return plat_arm_mmap;
188}
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100189
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100190#ifdef ARM_SYS_CNTCTL_BASE
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100191
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100192unsigned int plat_get_syscnt_freq2(void)
193{
Sandrine Bailleuxa8ef6652016-06-03 15:00:46 +0100194 unsigned int counter_base_frequency;
Yatharth Kochar3c0087a2016-04-14 14:49:37 +0100195
196 /* Read the frequency from Frequency modes table */
197 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
198
199 /* The first entry of the frequency modes table must not be 0 */
200 if (counter_base_frequency == 0)
201 panic();
202
203 return counter_base_frequency;
204}
Antonio Nino Diaze82e29c2016-05-19 10:00:28 +0100205
Yatharth Kochar0b49fb72016-04-26 10:36:29 +0100206#endif /* ARM_SYS_CNTCTL_BASE */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100207
208#if SDEI_SUPPORT
209/*
210 * Translate SDEI entry point to PA, and perform standard ARM entry point
211 * validation on it.
212 */
213int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode)
214{
215 uint64_t par, pa;
216 uint32_t scr_el3;
217
218 /* Doing Non-secure address translation requires SCR_EL3.NS set */
219 scr_el3 = read_scr_el3();
220 write_scr_el3(scr_el3 | SCR_NS_BIT);
221 isb();
222
223 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1));
224 if (client_mode == MODE_EL2) {
225 /*
226 * Translate entry point to Physical Address using the EL2
227 * translation regime.
228 */
229 ats1e2r(ep);
230 } else {
231 /*
232 * Translate entry point to Physical Address using the EL1&0
233 * translation regime, including stage 2.
234 */
235 ats12e1r(ep);
236 }
237 isb();
238 par = read_par_el1();
239
240 /* Restore original SCRL_EL3 */
241 write_scr_el3(scr_el3);
242 isb();
243
244 /* If the translation resulted in fault, return failure */
245 if ((par & PAR_F_MASK) != 0)
246 return -1;
247
248 /* Extract Physical Address from PAR */
249 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT));
250
251 /* Perform NS entry point validation on the physical address */
252 return arm_validate_ns_entrypoint(pa);
253}
254#endif