Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1 | Trusted Firmware-A User Guide |
| 2 | ============================= |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3 | |
| 4 | |
| 5 | .. section-numbering:: |
| 6 | :suffix: . |
| 7 | |
| 8 | .. contents:: |
| 9 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 10 | This document describes how to build Trusted Firmware-A (TF-A) and run it with a |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 11 | tested set of other software components using defined configurations on the Juno |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 12 | Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 13 | possible to use other software components, configurations and platforms but that |
| 14 | is outside the scope of this document. |
| 15 | |
| 16 | This document assumes that the reader has previous experience running a fully |
| 17 | bootable Linux software stack on Juno or FVP using the prebuilt binaries and |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 18 | filesystems provided by `Linaro`_. Further information may be found in the |
| 19 | `Linaro instructions`_. It also assumes that the user understands the role of |
| 20 | the different software components required to boot a Linux system: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 21 | |
| 22 | - Specific firmware images required by the platform (e.g. SCP firmware on Juno) |
| 23 | - Normal world bootloader (e.g. UEFI or U-Boot) |
| 24 | - Device tree |
| 25 | - Linux kernel image |
| 26 | - Root filesystem |
| 27 | |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 28 | This document also assumes that the user is familiar with the `FVP models`_ and |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 29 | the different command line options available to launch the model. |
| 30 | |
| 31 | This document should be used in conjunction with the `Firmware Design`_. |
| 32 | |
| 33 | Host machine requirements |
| 34 | ------------------------- |
| 35 | |
| 36 | The minimum recommended machine specification for building the software and |
| 37 | running the FVP models is a dual-core processor running at 2GHz with 12GB of |
| 38 | RAM. For best performance, use a machine with a quad-core processor running at |
| 39 | 2.6GHz with 16GB of RAM. |
| 40 | |
Joel Hutton | fe02771 | 2018-03-19 11:59:57 +0000 | [diff] [blame] | 41 | The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 42 | building the software were installed from that distribution unless otherwise |
| 43 | specified. |
| 44 | |
| 45 | The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE, |
David Cunado | b2de099 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 46 | Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 47 | |
| 48 | Tools |
| 49 | ----- |
| 50 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 51 | Install the required packages to build TF-A with the following command: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 52 | |
| 53 | :: |
| 54 | |
Sathees Balya | 2d0aeb0 | 2018-07-10 14:46:51 +0100 | [diff] [blame] | 55 | sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 56 | |
David Cunado | 05845bf | 2017-12-19 16:33:25 +0000 | [diff] [blame] | 57 | TF-A has been tested with Linaro Release 18.04. |
David Cunado | b2de099 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 58 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 59 | Download and install the AArch32 or AArch64 little-endian GCC cross compiler. |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 60 | The `Linaro Release Notes`_ documents which version of the compiler to use for a |
| 61 | given Linaro Release. Also, these `Linaro instructions`_ provide further |
| 62 | guidance and a script, which can be used to download Linaro deliverables |
| 63 | automatically. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 64 | |
Roberto Vargas | 0489bc0 | 2018-04-16 15:43:26 +0100 | [diff] [blame] | 65 | Optionally, TF-A can be built using clang version 4.0 or newer or Arm |
| 66 | Compiler 6. See instructions below on how to switch the default compiler. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 67 | |
| 68 | In addition, the following optional packages and tools may be needed: |
| 69 | |
Sathees Balya | 017a67e | 2018-08-17 10:22:01 +0100 | [diff] [blame] | 70 | - ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device |
| 71 | Tree (FDT) source files (``.dts`` files) provided with this software. The |
| 72 | version of dtc must be 1.4.6 or above. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 73 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 74 | - For debugging, Arm `Development Studio 5 (DS-5)`_. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 75 | |
Antonio Nino Diaz | b5d6809 | 2017-05-23 11:49:22 +0100 | [diff] [blame] | 76 | - To create and modify the diagram files included in the documentation, `Dia`_. |
| 77 | This tool can be found in most Linux distributions. Inkscape is needed to |
Antonio Nino Diaz | 80914a8 | 2018-08-08 16:28:43 +0100 | [diff] [blame] | 78 | generate the actual \*.png files. |
Antonio Nino Diaz | b5d6809 | 2017-05-23 11:49:22 +0100 | [diff] [blame] | 79 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 80 | Getting the TF-A source code |
| 81 | ---------------------------- |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 82 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 83 | Download the TF-A source code from Github: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 84 | |
| 85 | :: |
| 86 | |
| 87 | git clone https://github.com/ARM-software/arm-trusted-firmware.git |
| 88 | |
Paul Beesley | 8b4bdeb | 2019-01-21 12:06:24 +0000 | [diff] [blame] | 89 | Checking source code style |
| 90 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 91 | |
| 92 | Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the |
| 93 | source, for submission to the project, the source must be in compliance with |
| 94 | this style guide. |
| 95 | |
| 96 | Additional, project-specific guidelines are defined in the `Trusted Firmware-A |
| 97 | Coding Guidelines`_ document. |
| 98 | |
| 99 | To assist with coding style compliance, the project Makefile contains two |
| 100 | targets which both utilise the `checkpatch.pl` script that ships with the Linux |
| 101 | source tree. The project also defines certain *checkpatch* options in the |
| 102 | ``.checkpatch.conf`` file in the top-level directory. |
| 103 | |
| 104 | **Note:** Checkpatch errors will gate upstream merging of pull requests. |
| 105 | Checkpatch warnings will not gate merging but should be reviewed and fixed if |
| 106 | possible. |
| 107 | |
| 108 | To check the entire source tree, you must first download copies of |
| 109 | ``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available |
| 110 | in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH`` |
| 111 | environment variable to point to ``checkpatch.pl`` (with the other 2 files in |
| 112 | the same directory) and build the `checkcodebase` target: |
| 113 | |
| 114 | :: |
| 115 | |
| 116 | make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase |
| 117 | |
| 118 | To just check the style on the files that differ between your local branch and |
| 119 | the remote master, use: |
| 120 | |
| 121 | :: |
| 122 | |
| 123 | make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch |
| 124 | |
| 125 | If you wish to check your patch against something other than the remote master, |
| 126 | set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT`` |
| 127 | is set to ``origin/master``. |
| 128 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 129 | Building TF-A |
| 130 | ------------- |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 131 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 132 | - Before building TF-A, the environment variable ``CROSS_COMPILE`` must point |
| 133 | to the Linaro cross compiler. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 134 | |
| 135 | For AArch64: |
| 136 | |
| 137 | :: |
| 138 | |
| 139 | export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- |
| 140 | |
| 141 | For AArch32: |
| 142 | |
| 143 | :: |
| 144 | |
| 145 | export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf- |
| 146 | |
Roberto Vargas | 07b1e24 | 2018-04-23 08:38:12 +0100 | [diff] [blame] | 147 | It is possible to build TF-A using Clang or Arm Compiler 6. To do so |
| 148 | ``CC`` needs to point to the clang or armclang binary, which will |
| 149 | also select the clang or armclang assembler. Be aware that the |
| 150 | GNU linker is used by default. In case of being needed the linker |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 151 | can be overridden using the ``LD`` variable. Clang linker version 6 is |
Roberto Vargas | 07b1e24 | 2018-04-23 08:38:12 +0100 | [diff] [blame] | 152 | known to work with TF-A. |
| 153 | |
| 154 | In both cases ``CROSS_COMPILE`` should be set as described above. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 155 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 156 | Arm Compiler 6 will be selected when the base name of the path assigned |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 157 | to ``CC`` matches the string 'armclang'. |
| 158 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 159 | For AArch64 using Arm Compiler 6: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 160 | |
| 161 | :: |
| 162 | |
| 163 | export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- |
| 164 | make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all |
| 165 | |
| 166 | Clang will be selected when the base name of the path assigned to ``CC`` |
| 167 | contains the string 'clang'. This is to allow both clang and clang-X.Y |
| 168 | to work. |
| 169 | |
| 170 | For AArch64 using clang: |
| 171 | |
| 172 | :: |
| 173 | |
| 174 | export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- |
| 175 | make CC=<path-to-clang>/bin/clang PLAT=<platform> all |
| 176 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 177 | - Change to the root directory of the TF-A source tree and build. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 178 | |
| 179 | For AArch64: |
| 180 | |
| 181 | :: |
| 182 | |
| 183 | make PLAT=<platform> all |
| 184 | |
| 185 | For AArch32: |
| 186 | |
| 187 | :: |
| 188 | |
| 189 | make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all |
| 190 | |
| 191 | Notes: |
| 192 | |
| 193 | - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the |
| 194 | `Summary of build options`_ for more information on available build |
| 195 | options. |
| 196 | |
| 197 | - (AArch32 only) Currently only ``PLAT=fvp`` is supported. |
| 198 | |
| 199 | - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it |
| 200 | corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 201 | provided by TF-A to demonstrate how PSCI Library can be integrated with |
| 202 | an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may |
| 203 | include other runtime services, for example Trusted OS services. A guide |
| 204 | to integrate PSCI library with AArch32 EL3 Runtime Software can be found |
| 205 | `here`_. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 206 | |
| 207 | - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32 |
| 208 | image, is not compiled in by default. Refer to the |
| 209 | `Building the Test Secure Payload`_ section below. |
| 210 | |
| 211 | - By default this produces a release version of the build. To produce a |
| 212 | debug version instead, refer to the "Debugging options" section below. |
| 213 | |
| 214 | - The build process creates products in a ``build`` directory tree, building |
| 215 | the objects and binaries for each boot loader stage in separate |
| 216 | sub-directories. The following boot loader binary files are created |
| 217 | from the corresponding ELF files: |
| 218 | |
| 219 | - ``build/<platform>/<build-type>/bl1.bin`` |
| 220 | - ``build/<platform>/<build-type>/bl2.bin`` |
| 221 | - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only) |
| 222 | - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32) |
| 223 | |
| 224 | where ``<platform>`` is the name of the chosen platform and ``<build-type>`` |
| 225 | is either ``debug`` or ``release``. The actual number of images might differ |
| 226 | depending on the platform. |
| 227 | |
| 228 | - Build products for a specific build variant can be removed using: |
| 229 | |
| 230 | :: |
| 231 | |
| 232 | make DEBUG=<D> PLAT=<platform> clean |
| 233 | |
| 234 | ... where ``<D>`` is ``0`` or ``1``, as specified when building. |
| 235 | |
| 236 | The build tree can be removed completely using: |
| 237 | |
| 238 | :: |
| 239 | |
| 240 | make realclean |
| 241 | |
| 242 | Summary of build options |
| 243 | ~~~~~~~~~~~~~~~~~~~~~~~~ |
| 244 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 245 | The TF-A build system supports the following build options. Unless mentioned |
| 246 | otherwise, these options are expected to be specified at the build command |
| 247 | line and are not to be modified in any component makefiles. Note that the |
| 248 | build system doesn't track dependency for build options. Therefore, if any of |
| 249 | the build options are changed from a previous build, a clean build must be |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 250 | performed. |
| 251 | |
| 252 | Common build options |
| 253 | ^^^^^^^^^^^^^^^^^^^^ |
| 254 | |
Antonio Nino Diaz | 80914a8 | 2018-08-08 16:28:43 +0100 | [diff] [blame] | 255 | - ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the |
| 256 | compiler should use. Valid values are T32 and A32. It defaults to T32 due to |
| 257 | code having a smaller resulting size. |
| 258 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 259 | - ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as |
| 260 | as the BL32 image when ``ARCH=aarch32``. The value should be the path to the |
| 261 | directory containing the SP source, relative to the ``bl32/``; the directory |
| 262 | is expected to contain a makefile called ``<aarch32_sp-value>.mk``. |
| 263 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 264 | - ``ARCH`` : Choose the target build architecture for TF-A. It can take either |
| 265 | ``aarch64`` or ``aarch32`` as values. By default, it is defined to |
| 266 | ``aarch64``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 267 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 268 | - ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when |
| 269 | compiling TF-A. Its value must be numeric, and defaults to 8 . See also, |
| 270 | *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in |
| 271 | `Firmware Design`_. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 272 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 273 | - ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when |
| 274 | compiling TF-A. Its value must be a numeric, and defaults to 0. See also, |
| 275 | *Armv8 Architecture Extensions* in `Firmware Design`_. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 276 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 277 | - ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 278 | cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag |
| 279 | is set, the functions which deal with MPIDR assume that the ``MT`` bit in |
| 280 | MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of |
| 281 | this flag is 0. Note that this option is not used on FVP platforms. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 282 | |
| 283 | - ``BL2``: This is an optional build option which specifies the path to BL2 |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 284 | image for the ``fip`` target. In this case, the BL2 in the TF-A will not be |
| 285 | built. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 286 | |
| 287 | - ``BL2U``: This is an optional build option which specifies the path to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 288 | BL2U image. In this case, the BL2U in TF-A will not be built. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 289 | |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 290 | - ``BL2_AT_EL3``: This is an optional build option that enables the use of |
Roberto Vargas | b158427 | 2017-11-20 13:36:10 +0000 | [diff] [blame] | 291 | BL2 at EL3 execution level. |
| 292 | |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 293 | - ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place |
Jiafei Pan | 43a7bf4 | 2018-03-21 07:20:09 +0000 | [diff] [blame] | 294 | (XIP) memory, like BL1. In these use-cases, it is necessary to initialize |
| 295 | the RW sections in RAM, while leaving the RO sections in place. This option |
| 296 | enable this use-case. For now, this option is only supported when BL2_AT_EL3 |
| 297 | is set to '1'. |
| 298 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 299 | - ``BL31``: This is an optional build option which specifies the path to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 300 | BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not |
| 301 | be built. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 302 | |
| 303 | - ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 304 | file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, |
| 305 | this file name will be used to save the key. |
| 306 | |
| 307 | - ``BL32``: This is an optional build option which specifies the path to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 308 | BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not |
| 309 | be built. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 310 | |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 311 | - ``BL32_EXTRA1``: This is an optional build option which specifies the path to |
Summer Qin | 8072678 | 2017-04-20 16:28:39 +0100 | [diff] [blame] | 312 | Trusted OS Extra1 image for the ``fip`` target. |
| 313 | |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 314 | - ``BL32_EXTRA2``: This is an optional build option which specifies the path to |
Summer Qin | 8072678 | 2017-04-20 16:28:39 +0100 | [diff] [blame] | 315 | Trusted OS Extra2 image for the ``fip`` target. |
| 316 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 317 | - ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 318 | file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, |
| 319 | this file name will be used to save the key. |
| 320 | |
| 321 | - ``BL33``: Path to BL33 image in the host file system. This is mandatory for |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 322 | ``fip`` target in case TF-A BL2 is used. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 323 | |
| 324 | - ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 325 | file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, |
| 326 | this file name will be used to save the key. |
| 327 | |
| 328 | - ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the |
| 329 | compilation of each build. It must be set to a C string (including quotes |
| 330 | where applicable). Defaults to a string that contains the time and date of |
| 331 | the compilation. |
| 332 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 333 | - ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF-A |
| 334 | build to be uniquely identified. Defaults to the current git commit id. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 335 | |
| 336 | - ``CFLAGS``: Extra user options appended on the compiler's command line in |
| 337 | addition to the options set by the build system. |
| 338 | |
| 339 | - ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may |
| 340 | release several CPUs out of reset. It can take either 0 (several CPUs may be |
| 341 | brought up) or 1 (only one CPU will ever be brought up during cold reset). |
| 342 | Default is 0. If the platform always brings up a single CPU, there is no |
| 343 | need to distinguish between primary and secondary CPUs and the boot path can |
| 344 | be optimised. The ``plat_is_my_cpu_primary()`` and |
| 345 | ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need |
| 346 | to be implemented in this case. |
| 347 | |
| 348 | - ``CRASH_REPORTING``: A non-zero value enables a console dump of processor |
| 349 | register state when an unexpected exception occurs during execution of |
| 350 | BL31. This option defaults to the value of ``DEBUG`` - i.e. by default |
| 351 | this is only enabled for a debug build of the firmware. |
| 352 | |
| 353 | - ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the |
| 354 | certificate generation tool to create new keys in case no valid keys are |
| 355 | present or specified. Allowed options are '0' or '1'. Default is '1'. |
| 356 | |
| 357 | - ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause |
| 358 | the AArch32 system registers to be included when saving and restoring the |
| 359 | CPU context. The option must be set to 0 for AArch64-only platforms (that |
| 360 | is on hardware that does not implement AArch32, or at least not at EL1 and |
| 361 | higher ELs). Default value is 1. |
| 362 | |
| 363 | - ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP |
| 364 | registers to be included when saving and restoring the CPU context. Default |
| 365 | is 0. |
| 366 | |
| 367 | - ``DEBUG``: Chooses between a debug and release build. It can take either 0 |
| 368 | (release) or 1 (debug) as values. 0 is the default. |
| 369 | |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 370 | - ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted |
| 371 | Board Boot authentication at runtime. This option is meant to be enabled only |
Roberto Vargas | 025946a | 2018-09-24 17:20:48 +0100 | [diff] [blame] | 372 | for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this |
| 373 | flag has to be enabled. 0 is the default. |
Soby Mathew | 9fe8804 | 2018-03-26 12:43:37 +0100 | [diff] [blame] | 374 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 375 | - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of |
| 376 | the normal boot flow. It must specify the entry point address of the EL3 |
| 377 | payload. Please refer to the "Booting an EL3 payload" section for more |
| 378 | details. |
| 379 | |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 380 | - ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. |
Dimitris Papastamos | e08005a | 2017-10-12 13:02:29 +0100 | [diff] [blame] | 381 | This is an optional architectural feature available on v8.4 onwards. Some |
| 382 | v8.2 implementations also implement an AMU and this option can be used to |
| 383 | enable this feature on those systems as well. Default is 0. |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 384 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 385 | - ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` |
| 386 | are compiled out. For debug builds, this option defaults to 1, and calls to |
| 387 | ``assert()`` are left in place. For release builds, this option defaults to 0 |
| 388 | and calls to ``assert()`` function are compiled out. This option can be set |
| 389 | independently of ``DEBUG``. It can also be used to hide any auxiliary code |
| 390 | that is only required for the assertion and does not fit in the assertion |
| 391 | itself. |
| 392 | |
Douglas Raillard | 7741463 | 2018-08-21 12:54:45 +0100 | [diff] [blame] | 393 | - ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace |
| 394 | dumps or not. It is supported in both AArch64 and AArch32. However, in |
| 395 | AArch32 the format of the frame records are not defined in the AAPCS and they |
| 396 | are defined by the implementation. This implementation of backtrace only |
| 397 | supports the format used by GCC when T32 interworking is disabled. For this |
| 398 | reason enabling this option in AArch32 will force the compiler to only |
| 399 | generate A32 code. This option is enabled by default only in AArch64 debug |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 400 | builds, but this behaviour can be overridden in each platform's Makefile or |
| 401 | in the build command line. |
Douglas Raillard | 7741463 | 2018-08-21 12:54:45 +0100 | [diff] [blame] | 402 | |
Jeenu Viswambharan | 2da918c | 2018-07-31 16:13:33 +0100 | [diff] [blame] | 403 | - ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM |
| 404 | feature. MPAM is an optional Armv8.4 extension that enables various memory |
| 405 | system components and resources to define partitions; software running at |
| 406 | various ELs can assign themselves to desired partition to control their |
| 407 | performance aspects. |
| 408 | |
| 409 | When this option is set to ``1``, EL3 allows lower ELs to access their own |
| 410 | MPAM registers without trapping into EL3. This option doesn't make use of |
| 411 | partitioning in EL3, however. Platform initialisation code should configure |
| 412 | and use partitions in EL3 as required. This option defaults to ``0``. |
| 413 | |
Soby Mathew | 078f1a4 | 2018-08-28 11:13:55 +0100 | [diff] [blame] | 414 | - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) |
| 415 | support within generic code in TF-A. This option is currently only supported |
| 416 | in BL31. Default is 0. |
| 417 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 418 | - ``ENABLE_PMF``: Boolean option to enable support for optional Performance |
| 419 | Measurement Framework(PMF). Default is 0. |
| 420 | |
| 421 | - ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI |
| 422 | functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. |
| 423 | In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must |
| 424 | be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in |
| 425 | software. |
| 426 | |
| 427 | - ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 428 | instrumentation which injects timestamp collection points into TF-A to |
| 429 | allow runtime performance to be measured. Currently, only PSCI is |
| 430 | instrumented. Enabling this option enables the ``ENABLE_PMF`` build option |
| 431 | as well. Default is 0. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 432 | |
Jeenu Viswambharan | d73dcf3 | 2017-07-19 13:52:12 +0100 | [diff] [blame] | 433 | - ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling |
Dimitris Papastamos | 9da09cd | 2017-10-13 15:07:45 +0100 | [diff] [blame] | 434 | extensions. This is an optional architectural feature for AArch64. |
| 435 | The default is 1 but is automatically disabled when the target architecture |
| 436 | is AArch32. |
Jeenu Viswambharan | d73dcf3 | 2017-07-19 13:52:12 +0100 | [diff] [blame] | 437 | |
Sandrine Bailleux | 604f0a4 | 2018-09-20 12:44:39 +0200 | [diff] [blame] | 438 | - ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM). |
| 439 | Refer to the `Secure Partition Manager Design guide`_ for more details about |
| 440 | this feature. Default is 0. |
| 441 | |
David Cunado | ce88eee | 2017-10-20 11:30:57 +0100 | [diff] [blame] | 442 | - ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension |
| 443 | (SVE) for the Non-secure world only. SVE is an optional architectural feature |
| 444 | for AArch64. Note that when SVE is enabled for the Non-secure world, access |
| 445 | to SIMD and floating-point functionality from the Secure world is disabled. |
| 446 | This is to avoid corruption of the Non-secure world data in the Z-registers |
| 447 | which are aliased by the SIMD and FP registers. The build option is not |
| 448 | compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an |
| 449 | assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to |
| 450 | 1. The default is 1 but is automatically disabled when the target |
| 451 | architecture is AArch32. |
| 452 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 453 | - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection |
| 454 | checks in GCC. Allowed values are "all", "strong" and "0" (default). |
| 455 | "strong" is the recommended stack protection level if this feature is |
| 456 | desired. 0 disables the stack protection. For all values other than 0, the |
| 457 | ``plat_get_stack_protector_canary()`` platform hook needs to be implemented. |
| 458 | The value is passed as the last component of the option |
| 459 | ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. |
| 460 | |
| 461 | - ``ERROR_DEPRECATED``: This option decides whether to treat the usage of |
| 462 | deprecated platform APIs, helper functions or drivers within Trusted |
| 463 | Firmware as error. It can take the value 1 (flag the use of deprecated |
| 464 | APIs as error) or 0. The default is 0. |
| 465 | |
Jeenu Viswambharan | 10a6727 | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 466 | - ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions |
| 467 | targeted at EL3. When set ``0`` (default), no exceptions are expected or |
| 468 | handled at EL3, and a panic will result. This is supported only for AArch64 |
| 469 | builds. |
| 470 | |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 471 | - ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault |
Jeenu Viswambharan | f00da74 | 2017-12-08 12:13:51 +0000 | [diff] [blame] | 472 | injection from lower ELs, and this build option enables lower ELs to use |
| 473 | Error Records accessed via System Registers to inject faults. This is |
| 474 | applicable only to AArch64 builds. |
| 475 | |
| 476 | This feature is intended for testing purposes only, and is advisable to keep |
| 477 | disabled for production images. |
| 478 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 479 | - ``FIP_NAME``: This is an optional build option which specifies the FIP |
| 480 | filename for the ``fip`` target. Default is ``fip.bin``. |
| 481 | |
| 482 | - ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU |
| 483 | FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. |
| 484 | |
| 485 | - ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` |
| 486 | tool to create certificates as per the Chain of Trust described in |
| 487 | `Trusted Board Boot`_. The build system then calls ``fiptool`` to |
| 488 | include the certificates in the FIP and FWU\_FIP. Default value is '0'. |
| 489 | |
| 490 | Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support |
| 491 | for the Trusted Board Boot feature in the BL1 and BL2 images, to generate |
| 492 | the corresponding certificates, and to include those certificates in the |
| 493 | FIP and FWU\_FIP. |
| 494 | |
| 495 | Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 |
| 496 | images will not include support for Trusted Board Boot. The FIP will still |
| 497 | include the corresponding certificates. This FIP can be used to verify the |
| 498 | Chain of Trust on the host machine through other mechanisms. |
| 499 | |
| 500 | Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 |
| 501 | images will include support for Trusted Board Boot, but the FIP and FWU\_FIP |
| 502 | will not include the corresponding certificates, causing a boot failure. |
| 503 | |
Jeenu Viswambharan | c06f05c | 2017-09-22 08:32:09 +0100 | [diff] [blame] | 504 | - ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have |
| 505 | inherent support for specific EL3 type interrupts. Setting this build option |
| 506 | to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both |
| 507 | by `platform abstraction layer`__ and `Interrupt Management Framework`__. |
| 508 | This allows GICv2 platforms to enable features requiring EL3 interrupt type. |
| 509 | This also means that all GICv2 Group 0 interrupts are delivered to EL3, and |
| 510 | the Secure Payload interrupts needs to be synchronously handed over to Secure |
| 511 | EL1 for handling. The default value of this option is ``0``, which means the |
| 512 | Group 0 interrupts are assumed to be handled by Secure EL1. |
| 513 | |
| 514 | .. __: `platform-interrupt-controller-API.rst` |
| 515 | .. __: `interrupt-framework-design.rst` |
| 516 | |
Julius Werner | c51a2ec | 2018-08-28 14:45:43 -0700 | [diff] [blame] | 517 | - ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError |
| 518 | Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to |
| 519 | ``0`` (default), these exceptions will be trapped in the current exception |
| 520 | level (or in EL1 if the current exception level is EL0). |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 521 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 522 | - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 523 | software operations are required for CPUs to enter and exit coherency. |
| 524 | However, there exists newer systems where CPUs' entry to and exit from |
| 525 | coherency is managed in hardware. Such systems require software to only |
| 526 | initiate the operations, and the rest is managed in hardware, minimizing |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 527 | active software management. In such systems, this boolean option enables |
| 528 | TF-A to carry out build and run-time optimizations during boot and power |
| 529 | management operations. This option defaults to 0 and if it is enabled, |
| 530 | then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 531 | |
Jeenu Viswambharan | e834ee1 | 2018-04-27 15:17:03 +0100 | [diff] [blame] | 532 | Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of |
| 533 | translation library (xlat tables v2) must be used; version 1 of translation |
| 534 | library is not supported. |
| 535 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 536 | - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 |
| 537 | runtime software in AArch32 mode, which is required to run AArch32 on Juno. |
| 538 | By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in |
| 539 | AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable |
| 540 | images. |
| 541 | |
Soby Mathew | 13b1605 | 2017-08-31 11:49:32 +0100 | [diff] [blame] | 542 | - ``KEY_ALG``: This build flag enables the user to select the algorithm to be |
| 543 | used for generating the PKCS keys and subsequent signing of the certificate. |
Qixiang Xu | 1a1f291 | 2017-11-09 13:56:29 +0800 | [diff] [blame] | 544 | It accepts 3 values viz. ``rsa``, ``rsa_1_5``, ``ecdsa``. The ``rsa_1_5`` is |
Soby Mathew | 2fd70f6 | 2017-08-31 11:50:29 +0100 | [diff] [blame] | 545 | the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is |
| 546 | retained only for compatibility. The default value of this flag is ``rsa`` |
| 547 | which is the TBBR compliant PKCS#1 RSA 2.1 scheme. |
Soby Mathew | 13b1605 | 2017-08-31 11:49:32 +0100 | [diff] [blame] | 548 | |
Qixiang Xu | 1a1f291 | 2017-11-09 13:56:29 +0800 | [diff] [blame] | 549 | - ``HASH_ALG``: This build flag enables the user to select the secure hash |
| 550 | algorithm. It accepts 3 values viz. ``sha256``, ``sha384``, ``sha512``. |
| 551 | The default value of this flag is ``sha256``. |
| 552 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 553 | - ``LDFLAGS``: Extra user options appended to the linkers' command line in |
| 554 | addition to the one set by the build system. |
| 555 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 556 | - ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log |
| 557 | output compiled into the build. This should be one of the following: |
| 558 | |
| 559 | :: |
| 560 | |
| 561 | 0 (LOG_LEVEL_NONE) |
Daniel Boulby | 86c6b07 | 2018-06-14 10:07:40 +0100 | [diff] [blame] | 562 | 10 (LOG_LEVEL_ERROR) |
| 563 | 20 (LOG_LEVEL_NOTICE) |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 564 | 30 (LOG_LEVEL_WARNING) |
| 565 | 40 (LOG_LEVEL_INFO) |
| 566 | 50 (LOG_LEVEL_VERBOSE) |
| 567 | |
John Tsichritzis | 35006c4 | 2018-10-05 12:02:29 +0100 | [diff] [blame] | 568 | All log output up to and including the selected log level is compiled into |
| 569 | the build. The default value is 40 in debug builds and 20 in release builds. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 570 | |
| 571 | - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It |
| 572 | specifies the file that contains the Non-Trusted World private key in PEM |
| 573 | format. If ``SAVE_KEYS=1``, this file name will be used to save the key. |
| 574 | |
| 575 | - ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is |
| 576 | optional. It is only needed if the platform makefile specifies that it |
| 577 | is required in order to build the ``fwu_fip`` target. |
| 578 | |
| 579 | - ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register |
| 580 | contents upon world switch. It can take either 0 (don't save and restore) or |
| 581 | 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it |
| 582 | wants the timer registers to be saved and restored. |
| 583 | |
| 584 | - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that |
| 585 | the underlying hardware is not a full PL011 UART but a minimally compliant |
| 586 | generic UART, which is a subset of the PL011. The driver will not access |
| 587 | any register that is not part of the SBSA generic UART specification. |
| 588 | Default value is 0 (a full PL011 compliant UART is present). |
| 589 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 590 | - ``PLAT``: Choose a platform to build TF-A for. The chosen platform name |
| 591 | must be subdirectory of any depth under ``plat/``, and must contain a |
| 592 | platform makefile named ``platform.mk``. For example, to build TF-A for the |
| 593 | Arm Juno board, select PLAT=juno. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 594 | |
| 595 | - ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image |
| 596 | instead of the normal boot flow. When defined, it must specify the entry |
| 597 | point address for the preloaded BL33 image. This option is incompatible with |
| 598 | ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority |
| 599 | over ``PRELOADED_BL33_BASE``. |
| 600 | |
| 601 | - ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset |
| 602 | vector address can be programmed or is fixed on the platform. It can take |
| 603 | either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a |
| 604 | programmable reset address, it is expected that a CPU will start executing |
| 605 | code directly at the right address, both on a cold and warm reset. In this |
| 606 | case, there is no need to identify the entrypoint on boot and the boot path |
| 607 | can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface |
| 608 | does not need to be implemented in this case. |
| 609 | |
| 610 | - ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats |
| 611 | possible for the PSCI power-state parameter viz original and extended |
| 612 | State-ID formats. This flag if set to 1, configures the generic PSCI layer |
| 613 | to use the extended format. The default value of this flag is 0, which |
| 614 | means by default the original power-state format is used by the PSCI |
| 615 | implementation. This flag should be specified by the platform makefile |
| 616 | and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 617 | smc function id. When this option is enabled on Arm platforms, the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 618 | option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well. |
| 619 | |
Jeenu Viswambharan | 9a7ce2f | 2018-04-04 16:07:11 +0100 | [diff] [blame] | 620 | - ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features |
| 621 | are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 |
| 622 | or later CPUs. |
| 623 | |
| 624 | When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be |
| 625 | set to ``1``. |
| 626 | |
| 627 | This option is disabled by default. |
| 628 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 629 | - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead |
| 630 | of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 |
| 631 | entrypoint) or 1 (CPU reset to BL31 entrypoint). |
| 632 | The default value is 0. |
| 633 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 634 | - ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided |
| 635 | in TF-A. This flag configures SP\_MIN entrypoint as the CPU reset vector |
| 636 | instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 |
| 637 | entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default value is 0. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 638 | |
| 639 | - ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 640 | file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this |
| 641 | file name will be used to save the key. |
| 642 | |
| 643 | - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the |
| 644 | certificate generation tool to save the keys used to establish the Chain of |
| 645 | Trust. Allowed options are '0' or '1'. Default is '0' (do not save). |
| 646 | |
| 647 | - ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional. |
| 648 | If a SCP\_BL2 image is present then this option must be passed for the ``fip`` |
| 649 | target. |
| 650 | |
| 651 | - ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the |
| 652 | file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``, |
| 653 | this file name will be used to save the key. |
| 654 | |
| 655 | - ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is |
| 656 | optional. It is only needed if the platform makefile specifies that it |
| 657 | is required in order to build the ``fwu_fip`` target. |
| 658 | |
Jeenu Viswambharan | 04e3a7f | 2017-10-16 08:43:14 +0100 | [diff] [blame] | 659 | - ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software |
| 660 | Delegated Exception Interface to BL31 image. This defaults to ``0``. |
| 661 | |
| 662 | When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be |
| 663 | set to ``1``. |
| 664 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 665 | - ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be |
| 666 | isolated on separate memory pages. This is a trade-off between security and |
| 667 | memory usage. See "Isolating code and read-only data on separate memory |
| 668 | pages" section in `Firmware Design`_. This flag is disabled by default and |
| 669 | affects all BL images. |
| 670 | |
Antonio Nino Diaz | 35c8cfc | 2018-04-23 15:43:29 +0100 | [diff] [blame] | 671 | - ``SMCCC_MAJOR_VERSION``: Numeric value that indicates the major version of |
| 672 | the SMC Calling Convention that the Trusted Firmware supports. The only two |
| 673 | allowed values are 1 and 2, and it defaults to 1. The minor version is |
| 674 | determined using this value. |
| 675 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 676 | - ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. |
| 677 | This build option is only valid if ``ARCH=aarch64``. The value should be |
| 678 | the path to the directory containing the SPD source, relative to |
| 679 | ``services/spd/``; the directory is expected to contain a makefile called |
| 680 | ``<spd-value>.mk``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 681 | |
| 682 | - ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can |
| 683 | take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops |
| 684 | execution in BL1 just before handing over to BL31. At this point, all |
| 685 | firmware images have been loaded in memory, and the MMU and caches are |
| 686 | turned off. Refer to the "Debugging options" section for more details. |
| 687 | |
Antonio Nino Diaz | d9166ac | 2018-05-11 11:15:10 +0100 | [diff] [blame] | 688 | - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles |
Etienne Carriere | dc0fea7 | 2017-08-09 15:48:53 +0200 | [diff] [blame] | 689 | secure interrupts (caught through the FIQ line). Platforms can enable |
| 690 | this directive if they need to handle such interruption. When enabled, |
| 691 | the FIQ are handled in monitor mode and non secure world is not allowed |
| 692 | to mask these events. Platforms that enable FIQ handling in SP_MIN shall |
| 693 | implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. |
| 694 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 695 | - ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board |
| 696 | Boot feature. When set to '1', BL1 and BL2 images include support to load |
| 697 | and verify the certificates and images in a FIP, and BL1 includes support |
| 698 | for the Firmware Update. The default value is '0'. Generation and inclusion |
| 699 | of certificates in the FIP and FWU\_FIP depends upon the value of the |
| 700 | ``GENERATE_COT`` option. |
| 701 | |
| 702 | Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys |
| 703 | already exist in disk, they will be overwritten without further notice. |
| 704 | |
| 705 | - ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It |
| 706 | specifies the file that contains the Trusted World private key in PEM |
| 707 | format. If ``SAVE_KEYS=1``, this file name will be used to save the key. |
| 708 | |
| 709 | - ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or |
| 710 | synchronous, (see "Initializing a BL32 Image" section in |
| 711 | `Firmware Design`_). It can take the value 0 (BL32 is initialized using |
| 712 | synchronous method) or 1 (BL32 is initialized using asynchronous method). |
| 713 | Default is 0. |
| 714 | |
| 715 | - ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt |
| 716 | routing model which routes non-secure interrupts asynchronously from TSP |
| 717 | to EL3 causing immediate preemption of TSP. The EL3 is responsible |
| 718 | for saving and restoring the TSP context in this routing model. The |
| 719 | default routing model (when the value is 0) is to route non-secure |
| 720 | interrupts to TSP allowing it to save its context and hand over |
| 721 | synchronously to EL3 via an SMC. |
| 722 | |
Jeenu Viswambharan | 2f40f32 | 2018-01-11 14:30:22 +0000 | [diff] [blame] | 723 | Note: when ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` |
| 724 | must also be set to ``1``. |
| 725 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 726 | - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent |
| 727 | memory region in the BL memory map or not (see "Use of Coherent memory in |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 728 | TF-A" section in `Firmware Design`_). It can take the value 1 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 729 | (Coherent memory region is included) or 0 (Coherent memory region is |
| 730 | excluded). Default is 1. |
| 731 | |
| 732 | - ``V``: Verbose build. If assigned anything other than 0, the build commands |
| 733 | are printed. Default is 0. |
| 734 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 735 | - ``VERSION_STRING``: String used in the log output for each TF-A image. |
| 736 | Defaults to a string formed by concatenating the version number, build type |
| 737 | and build string. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 738 | |
| 739 | - ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on |
| 740 | the CPU after warm boot. This is applicable for platforms which do not |
| 741 | require interconnect programming to enable cache coherency (eg: single |
| 742 | cluster platforms). If this option is enabled, then warm boot path |
| 743 | enables D-caches immediately after enabling MMU. This option defaults to 0. |
| 744 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 745 | Arm development platform specific build options |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 746 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 747 | |
| 748 | - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured |
| 749 | DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load |
| 750 | BL31 in TZC secured DRAM. If TSP is present, then setting this option also |
| 751 | sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build |
| 752 | flag. |
| 753 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 754 | - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>`` |
| 755 | frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The |
| 756 | frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should |
| 757 | match the frame used by the Non-Secure image (normally the Linux kernel). |
| 758 | Default is true (access to the frame is allowed). |
| 759 | |
| 760 | - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog. |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 761 | By default, Arm platforms use a watchdog to trigger a system reset in case |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 762 | an error is encountered during the boot process (for example, when an image |
| 763 | could not be loaded or authenticated). The watchdog is enabled in the early |
| 764 | platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The |
| 765 | Trusted Watchdog may be disabled at build time for testing or development |
| 766 | purposes. |
| 767 | |
Antonio Nino Diaz | d9166ac | 2018-05-11 11:15:10 +0100 | [diff] [blame] | 768 | - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to |
| 769 | have specific values at boot. This boolean option allows the Trusted Firmware |
| 770 | to have a Linux kernel image as BL33 by preparing the registers to these |
Manish Pandey | 37c4ec2 | 2018-11-02 13:28:25 +0000 | [diff] [blame] | 771 | values before jumping to BL33. This option defaults to 0 (disabled). For |
| 772 | AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when |
| 773 | using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set |
| 774 | to the location of a device tree blob (DTB) already loaded in memory. The |
| 775 | Linux Image address must be specified using the ``PRELOADED_BL33_BASE`` |
| 776 | option. |
Antonio Nino Diaz | d9166ac | 2018-05-11 11:15:10 +0100 | [diff] [blame] | 777 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 778 | - ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding |
| 779 | for the construction of composite state-ID in the power-state parameter. |
| 780 | The existing PSCI clients currently do not support this encoding of |
| 781 | State-ID yet. Hence this flag is used to configure whether to use the |
| 782 | recommended State-ID encoding or not. The default value of this flag is 0, |
| 783 | in which case the platform is configured to expect NULL in the State-ID |
| 784 | field of power-state parameter. |
| 785 | |
| 786 | - ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the |
| 787 | location of the ROTPK hash returned by the function ``plat_get_rotpk_info()`` |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 788 | for Arm platforms. Depending on the selected option, the proper private key |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 789 | must be specified using the ``ROT_KEY`` option when building the Trusted |
| 790 | Firmware. This private key will be used by the certificate generation tool |
| 791 | to sign the BL2 and Trusted Key certificates. Available options for |
| 792 | ``ARM_ROTPK_LOCATION`` are: |
| 793 | |
| 794 | - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage |
| 795 | registers. The private key corresponding to this ROTPK hash is not |
| 796 | currently available. |
| 797 | - ``devel_rsa`` : return a development public key hash embedded in the BL1 |
| 798 | and BL2 binaries. This hash has been obtained from the RSA public key |
| 799 | ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use |
| 800 | this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when |
| 801 | creating the certificates. |
Qixiang Xu | 1c2aef1 | 2017-08-24 15:12:20 +0800 | [diff] [blame] | 802 | - ``devel_ecdsa`` : return a development public key hash embedded in the BL1 |
| 803 | and BL2 binaries. This hash has been obtained from the ECDSA public key |
| 804 | ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use |
| 805 | this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY`` |
| 806 | when creating the certificates. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 807 | |
| 808 | - ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options: |
| 809 | |
Qixiang Xu | c7b12c5 | 2017-10-13 09:04:12 +0800 | [diff] [blame] | 810 | - ``tsram`` : Trusted SRAM (default option when TBB is not enabled) |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 811 | - ``tdram`` : Trusted DRAM (if available) |
John Tsichritzis | ee10e79 | 2018-06-06 09:38:10 +0100 | [diff] [blame] | 812 | - ``dram`` : Secure region in DRAM (default option when TBB is enabled, |
| 813 | configured by the TrustZone controller) |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 814 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 815 | - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1 |
| 816 | of the translation tables library instead of version 2. It is set to 0 by |
| 817 | default, which selects version 2. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 818 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 819 | - ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm® |
| 820 | TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm |
| 821 | platforms. If this option is specified, then the path to the CryptoCell |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 822 | SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag. |
| 823 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 824 | For a better understanding of these options, the Arm development platform memory |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 825 | map is explained in the `Firmware Design`_. |
| 826 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 827 | Arm CSS platform specific build options |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 828 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 829 | |
| 830 | - ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version |
| 831 | incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards |
| 832 | compatible change to the MTL protocol, used for AP/SCP communication. |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 833 | TF-A no longer supports earlier SCP versions. If this option is set to 1 |
| 834 | then TF-A will detect if an earlier version is in use. Default is 1. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 835 | |
| 836 | - ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and |
| 837 | SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded |
| 838 | during boot. Default is 1. |
| 839 | |
Soby Mathew | 1ced6b8 | 2017-06-12 12:37:10 +0100 | [diff] [blame] | 840 | - ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers |
| 841 | instead of SCPI/BOM driver for communicating with the SCP during power |
| 842 | management operations and for SCP RAM Firmware transfer. If this option |
| 843 | is set to 1, then SCMI/SDS drivers will be used. Default is 0. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 844 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 845 | Arm FVP platform specific build options |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 846 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 847 | |
| 848 | - ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 849 | build the topology tree within TF-A. By default TF-A is configured for dual |
| 850 | cluster topology and this option can be used to override the default value. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 851 | |
| 852 | - ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The |
| 853 | default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as |
| 854 | explained in the options below: |
| 855 | |
| 856 | - ``FVP_CCI`` : The CCI driver is selected. This is the default |
| 857 | if 0 < ``FVP_CLUSTER_COUNT`` <= 2. |
| 858 | - ``FVP_CCN`` : The CCN driver is selected. This is the default |
| 859 | if ``FVP_CLUSTER_COUNT`` > 2. |
| 860 | |
Jeenu Viswambharan | 7542113 | 2018-01-31 14:52:08 +0000 | [diff] [blame] | 861 | - ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in |
| 862 | a single cluster. This option defaults to 4. |
| 863 | |
Jeenu Viswambharan | 528d21b | 2016-11-15 13:53:57 +0000 | [diff] [blame] | 864 | - ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU |
| 865 | in the system. This option defaults to 1. Note that the build option |
| 866 | ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. |
| 867 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 868 | - ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: |
| 869 | |
| 870 | - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected |
| 871 | - ``FVP_GICV2`` : The GICv2 only driver is selected |
| 872 | - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 873 | |
| 874 | - ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer |
| 875 | for functions that wait for an arbitrary time length (udelay and mdelay). |
| 876 | The default value is 0. |
| 877 | |
Soby Mathew | b1bf044 | 2018-02-16 14:52:52 +0000 | [diff] [blame] | 878 | - ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled |
| 879 | to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for |
| 880 | details on HW_CONFIG. By default, this is initialized to a sensible DTS |
| 881 | file in ``fdts/`` folder depending on other build options. But some cases, |
| 882 | like shifted affinity format for MPIDR, cannot be detected at build time |
| 883 | and this option is needed to specify the appropriate DTS file. |
| 884 | |
| 885 | - ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in |
| 886 | FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is |
| 887 | similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the |
| 888 | HW_CONFIG blob instead of the DTS file. This option is useful to override |
| 889 | the default HW_CONFIG selected by the build system. |
| 890 | |
Summer Qin | 13b95c2 | 2018-03-02 15:51:14 +0800 | [diff] [blame] | 891 | ARM JUNO platform specific build options |
| 892 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 893 | |
| 894 | - ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone |
| 895 | Media Protection (TZ-MP1). Default value of this flag is 0. |
| 896 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 897 | Debugging options |
| 898 | ~~~~~~~~~~~~~~~~~ |
| 899 | |
| 900 | To compile a debug version and make the build more verbose use |
| 901 | |
| 902 | :: |
| 903 | |
| 904 | make PLAT=<platform> DEBUG=1 V=1 all |
| 905 | |
| 906 | AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for |
| 907 | example DS-5) might not support this and may need an older version of DWARF |
| 908 | symbols to be emitted by GCC. This can be achieved by using the |
| 909 | ``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the |
| 910 | version to 2 is recommended for DS-5 versions older than 5.16. |
| 911 | |
| 912 | When debugging logic problems it might also be useful to disable all compiler |
| 913 | optimizations by using ``-O0``. |
| 914 | |
| 915 | NOTE: Using ``-O0`` could cause output images to be larger and base addresses |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 916 | might need to be recalculated (see the **Memory layout on Arm development |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 917 | platforms** section in the `Firmware Design`_). |
| 918 | |
| 919 | Extra debug options can be passed to the build system by setting ``CFLAGS`` or |
| 920 | ``LDFLAGS``: |
| 921 | |
| 922 | .. code:: makefile |
| 923 | |
| 924 | CFLAGS='-O0 -gdwarf-2' \ |
| 925 | make PLAT=<platform> DEBUG=1 V=1 all |
| 926 | |
| 927 | Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be |
| 928 | ignored as the linker is called directly. |
| 929 | |
| 930 | It is also possible to introduce an infinite loop to help in debugging the |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 931 | post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the |
| 932 | ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 933 | section. In this case, the developer may take control of the target using a |
| 934 | debugger when indicated by the console output. When using DS-5, the following |
| 935 | commands can be used: |
| 936 | |
| 937 | :: |
| 938 | |
| 939 | # Stop target execution |
| 940 | interrupt |
| 941 | |
| 942 | # |
| 943 | # Prepare your debugging environment, e.g. set breakpoints |
| 944 | # |
| 945 | |
| 946 | # Jump over the debug loop |
| 947 | set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 |
| 948 | |
| 949 | # Resume execution |
| 950 | continue |
| 951 | |
| 952 | Building the Test Secure Payload |
| 953 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 954 | |
| 955 | The TSP is coupled with a companion runtime service in the BL31 firmware, |
| 956 | called the TSPD. Therefore, if you intend to use the TSP, the BL31 image |
| 957 | must be recompiled as well. For more information on SPs and SPDs, see the |
| 958 | `Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_. |
| 959 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 960 | First clean the TF-A build directory to get rid of any previous BL31 binary. |
| 961 | Then to build the TSP image use: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 962 | |
| 963 | :: |
| 964 | |
| 965 | make PLAT=<platform> SPD=tspd all |
| 966 | |
| 967 | An additional boot loader binary file is created in the ``build`` directory: |
| 968 | |
| 969 | :: |
| 970 | |
| 971 | build/<platform>/<build-type>/bl32.bin |
| 972 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 973 | |
| 974 | Building and using the FIP tool |
| 975 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 976 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 977 | Firmware Image Package (FIP) is a packaging format used by TF-A to package |
| 978 | firmware images in a single binary. The number and type of images that should |
| 979 | be packed in a FIP is platform specific and may include TF-A images and other |
| 980 | firmware images required by the platform. For example, most platforms require |
| 981 | a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or |
| 982 | U-Boot). |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 983 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 984 | The TF-A build system provides the make target ``fip`` to create a FIP file |
| 985 | for the specified platform using the FIP creation tool included in the TF-A |
| 986 | project. Examples below show how to build a FIP file for FVP, packaging TF-A |
| 987 | and BL33 images. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 988 | |
| 989 | For AArch64: |
| 990 | |
| 991 | :: |
| 992 | |
| 993 | make PLAT=fvp BL33=<path/to/bl33.bin> fip |
| 994 | |
| 995 | For AArch32: |
| 996 | |
| 997 | :: |
| 998 | |
| 999 | make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path/to/bl33.bin> fip |
| 1000 | |
| 1001 | Note that AArch32 support for Normal world boot loader (BL33), like U-boot or |
| 1002 | UEFI, on FVP is not available upstream. Hence custom solutions are required to |
| 1003 | allow Linux boot on FVP. These instructions assume such a custom boot loader |
| 1004 | (BL33) is available. |
| 1005 | |
| 1006 | The resulting FIP may be found in: |
| 1007 | |
| 1008 | :: |
| 1009 | |
| 1010 | build/fvp/<build-type>/fip.bin |
| 1011 | |
| 1012 | For advanced operations on FIP files, it is also possible to independently build |
| 1013 | the tool and create or modify FIPs using this tool. To do this, follow these |
| 1014 | steps: |
| 1015 | |
| 1016 | It is recommended to remove old artifacts before building the tool: |
| 1017 | |
| 1018 | :: |
| 1019 | |
| 1020 | make -C tools/fiptool clean |
| 1021 | |
| 1022 | Build the tool: |
| 1023 | |
| 1024 | :: |
| 1025 | |
| 1026 | make [DEBUG=1] [V=1] fiptool |
| 1027 | |
| 1028 | The tool binary can be located in: |
| 1029 | |
| 1030 | :: |
| 1031 | |
| 1032 | ./tools/fiptool/fiptool |
| 1033 | |
| 1034 | Invoking the tool with ``--help`` will print a help message with all available |
| 1035 | options. |
| 1036 | |
| 1037 | Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31: |
| 1038 | |
| 1039 | :: |
| 1040 | |
| 1041 | ./tools/fiptool/fiptool create \ |
| 1042 | --tb-fw build/<platform>/<build-type>/bl2.bin \ |
| 1043 | --soc-fw build/<platform>/<build-type>/bl31.bin \ |
| 1044 | fip.bin |
| 1045 | |
| 1046 | Example 2: view the contents of an existing Firmware package: |
| 1047 | |
| 1048 | :: |
| 1049 | |
| 1050 | ./tools/fiptool/fiptool info <path-to>/fip.bin |
| 1051 | |
| 1052 | Example 3: update the entries of an existing Firmware package: |
| 1053 | |
| 1054 | :: |
| 1055 | |
| 1056 | # Change the BL2 from Debug to Release version |
| 1057 | ./tools/fiptool/fiptool update \ |
| 1058 | --tb-fw build/<platform>/release/bl2.bin \ |
| 1059 | build/<platform>/debug/fip.bin |
| 1060 | |
| 1061 | Example 4: unpack all entries from an existing Firmware package: |
| 1062 | |
| 1063 | :: |
| 1064 | |
| 1065 | # Images will be unpacked to the working directory |
| 1066 | ./tools/fiptool/fiptool unpack <path-to>/fip.bin |
| 1067 | |
| 1068 | Example 5: remove an entry from an existing Firmware package: |
| 1069 | |
| 1070 | :: |
| 1071 | |
| 1072 | ./tools/fiptool/fiptool remove \ |
| 1073 | --tb-fw build/<platform>/debug/fip.bin |
| 1074 | |
| 1075 | Note that if the destination FIP file exists, the create, update and |
| 1076 | remove operations will automatically overwrite it. |
| 1077 | |
| 1078 | The unpack operation will fail if the images already exist at the |
| 1079 | destination. In that case, use -f or --force to continue. |
| 1080 | |
| 1081 | More information about FIP can be found in the `Firmware Design`_ document. |
| 1082 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1083 | Building FIP images with support for Trusted Board Boot |
| 1084 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1085 | |
| 1086 | Trusted Board Boot primarily consists of the following two features: |
| 1087 | |
| 1088 | - Image Authentication, described in `Trusted Board Boot`_, and |
| 1089 | - Firmware Update, described in `Firmware Update`_ |
| 1090 | |
| 1091 | The following steps should be followed to build FIP and (optionally) FWU\_FIP |
| 1092 | images with support for these features: |
| 1093 | |
| 1094 | #. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser |
| 1095 | modules by checking out a recent version of the `mbed TLS Repository`_. It |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1096 | is important to use a version that is compatible with TF-A and fixes any |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1097 | known security vulnerabilities. See `mbed TLS Security Center`_ for more |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1098 | information. The latest version of TF-A is tested with tag |
David Cunado | 05845bf | 2017-12-19 16:33:25 +0000 | [diff] [blame] | 1099 | ``mbedtls-2.12.0``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1100 | |
| 1101 | The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS |
| 1102 | source files the modules depend upon. |
| 1103 | ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration |
| 1104 | options required to build the mbed TLS sources. |
| 1105 | |
| 1106 | Note that the mbed TLS library is licensed under the Apache version 2.0 |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1107 | license. Using mbed TLS source code will affect the licensing of TF-A |
| 1108 | binaries that are built using this library. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1109 | |
| 1110 | #. To build the FIP image, ensure the following command line variables are set |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1111 | while invoking ``make`` to build TF-A: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1112 | |
| 1113 | - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>`` |
| 1114 | - ``TRUSTED_BOARD_BOOT=1`` |
| 1115 | - ``GENERATE_COT=1`` |
| 1116 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1117 | In the case of Arm platforms, the location of the ROTPK hash must also be |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1118 | specified at build time. Two locations are currently supported (see |
| 1119 | ``ARM_ROTPK_LOCATION`` build option): |
| 1120 | |
| 1121 | - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted |
| 1122 | root-key storage registers present in the platform. On Juno, this |
| 1123 | registers are read-only. On FVP Base and Cortex models, the registers |
| 1124 | are read-only, but the value can be specified using the command line |
| 1125 | option ``bp.trusted_key_storage.public_key`` when launching the model. |
| 1126 | On both Juno and FVP models, the default value corresponds to an |
| 1127 | ECDSA-SECP256R1 public key hash, whose private part is not currently |
| 1128 | available. |
| 1129 | |
| 1130 | - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1131 | in the Arm platform port. The private/public RSA key pair may be |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1132 | found in ``plat/arm/board/common/rotpk``. |
| 1133 | |
Qixiang Xu | 1c2aef1 | 2017-08-24 15:12:20 +0800 | [diff] [blame] | 1134 | - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1135 | in the Arm platform port. The private/public ECDSA key pair may be |
Qixiang Xu | 1c2aef1 | 2017-08-24 15:12:20 +0800 | [diff] [blame] | 1136 | found in ``plat/arm/board/common/rotpk``. |
| 1137 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1138 | Example of command line using RSA development keys: |
| 1139 | |
| 1140 | :: |
| 1141 | |
| 1142 | MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \ |
| 1143 | make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ |
| 1144 | ARM_ROTPK_LOCATION=devel_rsa \ |
| 1145 | ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ |
| 1146 | BL33=<path-to>/<bl33_image> \ |
| 1147 | all fip |
| 1148 | |
| 1149 | The result of this build will be the bl1.bin and the fip.bin binaries. This |
| 1150 | FIP will include the certificates corresponding to the Chain of Trust |
| 1151 | described in the TBBR-client document. These certificates can also be found |
| 1152 | in the output build directory. |
| 1153 | |
| 1154 | #. The optional FWU\_FIP contains any additional images to be loaded from |
| 1155 | Non-Volatile storage during the `Firmware Update`_ process. To build the |
| 1156 | FWU\_FIP, any FWU images required by the platform must be specified on the |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1157 | command line. On Arm development platforms like Juno, these are: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1158 | |
| 1159 | - NS\_BL2U. The AP non-secure Firmware Updater image. |
| 1160 | - SCP\_BL2U. The SCP Firmware Update Configuration image. |
| 1161 | |
| 1162 | Example of Juno command line for generating both ``fwu`` and ``fwu_fip`` |
| 1163 | targets using RSA development: |
| 1164 | |
| 1165 | :: |
| 1166 | |
| 1167 | MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \ |
| 1168 | make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ |
| 1169 | ARM_ROTPK_LOCATION=devel_rsa \ |
| 1170 | ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ |
| 1171 | BL33=<path-to>/<bl33_image> \ |
| 1172 | SCP_BL2=<path-to>/<scp_bl2_image> \ |
| 1173 | SCP_BL2U=<path-to>/<scp_bl2u_image> \ |
| 1174 | NS_BL2U=<path-to>/<ns_bl2u_image> \ |
| 1175 | all fip fwu_fip |
| 1176 | |
| 1177 | Note: The BL2U image will be built by default and added to the FWU\_FIP. |
| 1178 | The user may override this by adding ``BL2U=<path-to>/<bl2u_image>`` |
| 1179 | to the command line above. |
| 1180 | |
| 1181 | Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U, |
| 1182 | NS\_BL2U and SCP\_BL2U) is outside the scope of this document. |
| 1183 | |
| 1184 | The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries. |
| 1185 | Both the FIP and FWU\_FIP will include the certificates corresponding to the |
| 1186 | Chain of Trust described in the TBBR-client document. These certificates |
| 1187 | can also be found in the output build directory. |
| 1188 | |
| 1189 | Building the Certificate Generation Tool |
| 1190 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1191 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1192 | The ``cert_create`` tool is built as part of the TF-A build process when the |
| 1193 | ``fip`` make target is specified and TBB is enabled (as described in the |
| 1194 | previous section), but it can also be built separately with the following |
| 1195 | command: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1196 | |
| 1197 | :: |
| 1198 | |
| 1199 | make PLAT=<platform> [DEBUG=1] [V=1] certtool |
| 1200 | |
Antonio Nino Diaz | d8d734c | 2018-09-25 09:41:08 +0100 | [diff] [blame] | 1201 | For platforms that require their own IDs in certificate files, the generic |
| 1202 | 'cert\_create' tool can be built with the following command: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1203 | |
| 1204 | :: |
| 1205 | |
Antonio Nino Diaz | d8d734c | 2018-09-25 09:41:08 +0100 | [diff] [blame] | 1206 | make USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1207 | |
| 1208 | ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more |
| 1209 | verbose. The following command should be used to obtain help about the tool: |
| 1210 | |
| 1211 | :: |
| 1212 | |
| 1213 | ./tools/cert_create/cert_create -h |
| 1214 | |
| 1215 | Building a FIP for Juno and FVP |
| 1216 | ------------------------------- |
| 1217 | |
| 1218 | This section provides Juno and FVP specific instructions to build Trusted |
| 1219 | Firmware, obtain the additional required firmware, and pack it all together in |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1220 | a single FIP binary. It assumes that a `Linaro Release`_ has been installed. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1221 | |
David Cunado | b2de099 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 1222 | Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12 |
| 1223 | onwards. Before that release, pre-built binaries are only available for AArch64. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1224 | |
Joel Hutton | fe02771 | 2018-03-19 11:59:57 +0000 | [diff] [blame] | 1225 | Note: Follow the full instructions for one platform before switching to a |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1226 | different one. Mixing instructions for different platforms may result in |
| 1227 | corrupted binaries. |
| 1228 | |
Joel Hutton | fe02771 | 2018-03-19 11:59:57 +0000 | [diff] [blame] | 1229 | Note: The uboot image downloaded by the Linaro workspace script does not always |
| 1230 | match the uboot image packaged as BL33 in the corresponding fip file. It is |
| 1231 | recommended to use the version that is packaged in the fip file using the |
| 1232 | instructions below. |
| 1233 | |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1234 | Note: For the FVP, the kernel FDT is packaged in FIP during build and loaded |
| 1235 | by the firmware at runtime. See `Obtaining the Flattened Device Trees`_ |
| 1236 | section for more info on selecting the right FDT to use. |
| 1237 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1238 | #. Clean the working directory |
| 1239 | |
| 1240 | :: |
| 1241 | |
| 1242 | make realclean |
| 1243 | |
| 1244 | #. Obtain SCP\_BL2 (Juno) and BL33 (all platforms) |
| 1245 | |
| 1246 | Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP |
| 1247 | package included in the Linaro release: |
| 1248 | |
| 1249 | :: |
| 1250 | |
| 1251 | # Build the fiptool |
| 1252 | make [DEBUG=1] [V=1] fiptool |
| 1253 | |
| 1254 | # Unpack firmware images from Linaro FIP |
| 1255 | ./tools/fiptool/fiptool unpack \ |
| 1256 | <path/to/linaro/release>/fip.bin |
| 1257 | |
| 1258 | The unpack operation will result in a set of binary images extracted to the |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1259 | current working directory. The SCP\_BL2 image corresponds to |
| 1260 | ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1261 | |
Joel Hutton | fe02771 | 2018-03-19 11:59:57 +0000 | [diff] [blame] | 1262 | Note: The fiptool will complain if the images to be unpacked already |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1263 | exist in the current directory. If that is the case, either delete those |
| 1264 | files or use the ``--force`` option to overwrite. |
| 1265 | |
Joel Hutton | fe02771 | 2018-03-19 11:59:57 +0000 | [diff] [blame] | 1266 | Note: For AArch32, the instructions below assume that nt-fw.bin is a custom |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1267 | Normal world boot loader that supports AArch32. |
| 1268 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1269 | #. Build TF-A images and create a new FIP for FVP |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1270 | |
| 1271 | :: |
| 1272 | |
| 1273 | # AArch64 |
| 1274 | make PLAT=fvp BL33=nt-fw.bin all fip |
| 1275 | |
| 1276 | # AArch32 |
| 1277 | make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip |
| 1278 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1279 | #. Build TF-A images and create a new FIP for Juno |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1280 | |
| 1281 | For AArch64: |
| 1282 | |
| 1283 | Building for AArch64 on Juno simply requires the addition of ``SCP_BL2`` |
| 1284 | as a build parameter. |
| 1285 | |
| 1286 | :: |
| 1287 | |
| 1288 | make PLAT=juno all fip \ |
| 1289 | BL33=<path-to-juno-oe-uboot>/SOFTWARE/bl33-uboot.bin \ |
| 1290 | SCP_BL2=<path-to-juno-busybox-uboot>/SOFTWARE/scp_bl2.bin |
| 1291 | |
| 1292 | For AArch32: |
| 1293 | |
| 1294 | Hardware restrictions on Juno prevent cold reset into AArch32 execution mode, |
| 1295 | therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled |
| 1296 | separately for AArch32. |
| 1297 | |
| 1298 | - Before building BL32, the environment variable ``CROSS_COMPILE`` must point |
| 1299 | to the AArch32 Linaro cross compiler. |
| 1300 | |
| 1301 | :: |
| 1302 | |
| 1303 | export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf- |
| 1304 | |
| 1305 | - Build BL32 in AArch32. |
| 1306 | |
| 1307 | :: |
| 1308 | |
| 1309 | make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \ |
| 1310 | RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32 |
| 1311 | |
| 1312 | - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE`` |
| 1313 | must point to the AArch64 Linaro cross compiler. |
| 1314 | |
| 1315 | :: |
| 1316 | |
| 1317 | export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- |
| 1318 | |
| 1319 | - The following parameters should be used to build BL1 and BL2 in AArch64 |
| 1320 | and point to the BL32 file. |
| 1321 | |
| 1322 | :: |
| 1323 | |
Soby Mathew | 97b1bff | 2018-09-27 16:46:41 +0100 | [diff] [blame] | 1324 | make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1325 | BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \ |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 1326 | SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1327 | BL32=<path-to-bl32>/bl32.bin all fip |
| 1328 | |
| 1329 | The resulting BL1 and FIP images may be found in: |
| 1330 | |
| 1331 | :: |
| 1332 | |
| 1333 | # Juno |
| 1334 | ./build/juno/release/bl1.bin |
| 1335 | ./build/juno/release/fip.bin |
| 1336 | |
| 1337 | # FVP |
| 1338 | ./build/fvp/release/bl1.bin |
| 1339 | ./build/fvp/release/fip.bin |
| 1340 | |
Roberto Vargas | 096f3a0 | 2017-10-17 10:19:00 +0100 | [diff] [blame] | 1341 | |
| 1342 | Booting Firmware Update images |
| 1343 | ------------------------------------- |
| 1344 | |
| 1345 | When Firmware Update (FWU) is enabled there are at least 2 new images |
| 1346 | that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the |
| 1347 | FWU FIP. |
| 1348 | |
| 1349 | Juno |
| 1350 | ~~~~ |
| 1351 | |
| 1352 | The new images must be programmed in flash memory by adding |
| 1353 | an entry in the ``SITE1/HBI0262x/images.txt`` configuration file |
| 1354 | on the Juno SD card (where ``x`` depends on the revision of the Juno board). |
| 1355 | Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory |
| 1356 | programming" for more information. User should ensure these do not |
| 1357 | overlap with any other entries in the file. |
| 1358 | |
| 1359 | :: |
| 1360 | |
| 1361 | NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE |
| 1362 | NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address] |
| 1363 | NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name |
| 1364 | NOR10LOAD: 00000000 ;Image Load Address |
| 1365 | NOR10ENTRY: 00000000 ;Image Entry Point |
| 1366 | |
| 1367 | NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE |
| 1368 | NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address] |
| 1369 | NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name |
| 1370 | NOR11LOAD: 00000000 ;Image Load Address |
| 1371 | |
| 1372 | The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000. |
| 1373 | In the same way, the address ns_bl2u_base_address is the value of |
| 1374 | NS_BL2U_BASE - 0x8000000. |
| 1375 | |
| 1376 | FVP |
| 1377 | ~~~ |
| 1378 | |
| 1379 | The additional fip images must be loaded with: |
| 1380 | |
| 1381 | :: |
| 1382 | |
| 1383 | --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] |
| 1384 | --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] |
| 1385 | |
| 1386 | The address ns_bl1u_base_address is the value of NS_BL1U_BASE. |
| 1387 | In the same way, the address ns_bl2u_base_address is the value of |
| 1388 | NS_BL2U_BASE. |
| 1389 | |
| 1390 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1391 | EL3 payloads alternative boot flow |
| 1392 | ---------------------------------- |
| 1393 | |
| 1394 | On a pre-production system, the ability to execute arbitrary, bare-metal code at |
| 1395 | the highest exception level is required. It allows full, direct access to the |
| 1396 | hardware, for example to run silicon soak tests. |
| 1397 | |
| 1398 | Although it is possible to implement some baremetal secure firmware from |
| 1399 | scratch, this is a complex task on some platforms, depending on the level of |
| 1400 | configuration required to put the system in the expected state. |
| 1401 | |
| 1402 | Rather than booting a baremetal application, a possible compromise is to boot |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1403 | ``EL3 payloads`` through TF-A instead. This is implemented as an alternative |
| 1404 | boot flow, where a modified BL2 boots an EL3 payload, instead of loading the |
| 1405 | other BL images and passing control to BL31. It reduces the complexity of |
| 1406 | developing EL3 baremetal code by: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1407 | |
| 1408 | - putting the system into a known architectural state; |
| 1409 | - taking care of platform secure world initialization; |
| 1410 | - loading the SCP\_BL2 image if required by the platform. |
| 1411 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1412 | When booting an EL3 payload on Arm standard platforms, the configuration of the |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1413 | TrustZone controller is simplified such that only region 0 is enabled and is |
| 1414 | configured to permit secure access only. This gives full access to the whole |
| 1415 | DRAM to the EL3 payload. |
| 1416 | |
| 1417 | The system is left in the same state as when entering BL31 in the default boot |
| 1418 | flow. In particular: |
| 1419 | |
| 1420 | - Running in EL3; |
| 1421 | - Current state is AArch64; |
| 1422 | - Little-endian data access; |
| 1423 | - All exceptions disabled; |
| 1424 | - MMU disabled; |
| 1425 | - Caches disabled. |
| 1426 | |
| 1427 | Booting an EL3 payload |
| 1428 | ~~~~~~~~~~~~~~~~~~~~~~ |
| 1429 | |
| 1430 | The EL3 payload image is a standalone image and is not part of the FIP. It is |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1431 | not loaded by TF-A. Therefore, there are 2 possible scenarios: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1432 | |
| 1433 | - The EL3 payload may reside in non-volatile memory (NVM) and execute in |
| 1434 | place. In this case, booting it is just a matter of specifying the right |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1435 | address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1436 | |
| 1437 | - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at |
| 1438 | run-time. |
| 1439 | |
| 1440 | To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be |
| 1441 | used. The infinite loop that it introduces in BL1 stops execution at the right |
| 1442 | moment for a debugger to take control of the target and load the payload (for |
| 1443 | example, over JTAG). |
| 1444 | |
| 1445 | It is expected that this loading method will work in most cases, as a debugger |
| 1446 | connection is usually available in a pre-production system. The user is free to |
| 1447 | use any other platform-specific mechanism to load the EL3 payload, though. |
| 1448 | |
| 1449 | Booting an EL3 payload on FVP |
| 1450 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 1451 | |
| 1452 | The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for |
| 1453 | the secondary CPUs holding pen to work properly. Unfortunately, its reset value |
| 1454 | is undefined on the FVP platform and the FVP platform code doesn't clear it. |
| 1455 | Therefore, one must modify the way the model is normally invoked in order to |
| 1456 | clear the mailbox at start-up. |
| 1457 | |
| 1458 | One way to do that is to create an 8-byte file containing all zero bytes using |
| 1459 | the following command: |
| 1460 | |
| 1461 | :: |
| 1462 | |
| 1463 | dd if=/dev/zero of=mailbox.dat bs=1 count=8 |
| 1464 | |
| 1465 | and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) |
| 1466 | using the following model parameters: |
| 1467 | |
| 1468 | :: |
| 1469 | |
| 1470 | --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] |
| 1471 | --data=mailbox.dat@0x04000000 [Foundation FVP] |
| 1472 | |
| 1473 | To provide the model with the EL3 payload image, the following methods may be |
| 1474 | used: |
| 1475 | |
| 1476 | #. If the EL3 payload is able to execute in place, it may be programmed into |
| 1477 | flash memory. On Base Cortex and AEM FVPs, the following model parameter |
| 1478 | loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already |
| 1479 | used for the FIP): |
| 1480 | |
| 1481 | :: |
| 1482 | |
| 1483 | -C bp.flashloader1.fname="/path/to/el3-payload" |
| 1484 | |
| 1485 | On Foundation FVP, there is no flash loader component and the EL3 payload |
| 1486 | may be programmed anywhere in flash using method 3 below. |
| 1487 | |
| 1488 | #. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 |
| 1489 | command may be used to load the EL3 payload ELF image over JTAG: |
| 1490 | |
| 1491 | :: |
| 1492 | |
| 1493 | load /path/to/el3-payload.elf |
| 1494 | |
| 1495 | #. The EL3 payload may be pre-loaded in volatile memory using the following |
| 1496 | model parameters: |
| 1497 | |
| 1498 | :: |
| 1499 | |
| 1500 | --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs] |
| 1501 | --data="/path/to/el3-payload"@address [Foundation FVP] |
| 1502 | |
| 1503 | The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1504 | used when building TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1505 | |
| 1506 | Booting an EL3 payload on Juno |
| 1507 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 1508 | |
| 1509 | If the EL3 payload is able to execute in place, it may be programmed in flash |
| 1510 | memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file |
| 1511 | on the Juno SD card (where ``x`` depends on the revision of the Juno board). |
| 1512 | Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory |
| 1513 | programming" for more information. |
| 1514 | |
| 1515 | Alternatively, the same DS-5 command mentioned in the FVP section above can |
| 1516 | be used to load the EL3 payload's ELF file over JTAG on Juno. |
| 1517 | |
| 1518 | Preloaded BL33 alternative boot flow |
| 1519 | ------------------------------------ |
| 1520 | |
| 1521 | Some platforms have the ability to preload BL33 into memory instead of relying |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1522 | on TF-A to load it. This may simplify packaging of the normal world code and |
| 1523 | improve performance in a development environment. When secure world cold boot |
| 1524 | is complete, TF-A simply jumps to a BL33 base address provided at build time. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1525 | |
| 1526 | For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1527 | used when compiling TF-A. For example, the following command will create a FIP |
| 1528 | without a BL33 and prepare to jump to a BL33 image loaded at address |
| 1529 | 0x80000000: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1530 | |
| 1531 | :: |
| 1532 | |
| 1533 | make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip |
| 1534 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1535 | Boot of a preloaded kernel image on Base FVP |
| 1536 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1537 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1538 | The following example uses a simplified boot flow by directly jumping from the |
| 1539 | TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be |
| 1540 | useful if both the kernel and the device tree blob (DTB) are already present in |
| 1541 | memory (like in FVP). |
| 1542 | |
| 1543 | For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at |
| 1544 | address ``0x82000000``, the firmware can be built like this: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1545 | |
| 1546 | :: |
| 1547 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1548 | CROSS_COMPILE=aarch64-linux-gnu- \ |
| 1549 | make PLAT=fvp DEBUG=1 \ |
| 1550 | RESET_TO_BL31=1 \ |
| 1551 | ARM_LINUX_KERNEL_AS_BL33=1 \ |
| 1552 | PRELOADED_BL33_BASE=0x80080000 \ |
| 1553 | ARM_PRELOADED_DTB_BASE=0x82000000 \ |
| 1554 | all fip |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1555 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1556 | Now, it is needed to modify the DTB so that the kernel knows the address of the |
| 1557 | ramdisk. The following script generates a patched DTB from the provided one, |
| 1558 | assuming that the ramdisk is loaded at address ``0x84000000``. Note that this |
| 1559 | script assumes that the user is using a ramdisk image prepared for U-Boot, like |
| 1560 | the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` |
| 1561 | offset in ``INITRD_START`` has to be removed. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1562 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1563 | .. code:: bash |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1564 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1565 | #!/bin/bash |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1566 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1567 | # Path to the input DTB |
| 1568 | KERNEL_DTB=<path-to>/<fdt> |
| 1569 | # Path to the output DTB |
| 1570 | PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> |
| 1571 | # Base address of the ramdisk |
| 1572 | INITRD_BASE=0x84000000 |
| 1573 | # Path to the ramdisk |
| 1574 | INITRD=<path-to>/<ramdisk.img> |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1575 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1576 | # Skip uboot header (64 bytes) |
| 1577 | INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) |
| 1578 | INITRD_SIZE=$(stat -Lc %s ${INITRD}) |
| 1579 | INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) |
| 1580 | |
| 1581 | CHOSEN_NODE=$(echo \ |
| 1582 | "/ { \ |
| 1583 | chosen { \ |
| 1584 | linux,initrd-start = <${INITRD_START}>; \ |
| 1585 | linux,initrd-end = <${INITRD_END}>; \ |
| 1586 | }; \ |
| 1587 | };") |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1588 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1589 | echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ |
| 1590 | dtc -O dtb -o ${PATCHED_KERNEL_DTB} - |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1591 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1592 | And the FVP binary can be run with the following command: |
| 1593 | |
| 1594 | :: |
| 1595 | |
| 1596 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 1597 | -C pctl.startup=0.0.0.0 \ |
| 1598 | -C bp.secure_memory=1 \ |
| 1599 | -C cluster0.NUM_CORES=4 \ |
| 1600 | -C cluster1.NUM_CORES=4 \ |
| 1601 | -C cache_state_modelled=1 \ |
| 1602 | -C cluster0.cpu0.RVBAR=0x04020000 \ |
| 1603 | -C cluster0.cpu1.RVBAR=0x04020000 \ |
| 1604 | -C cluster0.cpu2.RVBAR=0x04020000 \ |
| 1605 | -C cluster0.cpu3.RVBAR=0x04020000 \ |
| 1606 | -C cluster1.cpu0.RVBAR=0x04020000 \ |
| 1607 | -C cluster1.cpu1.RVBAR=0x04020000 \ |
| 1608 | -C cluster1.cpu2.RVBAR=0x04020000 \ |
| 1609 | -C cluster1.cpu3.RVBAR=0x04020000 \ |
| 1610 | --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \ |
| 1611 | --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ |
| 1612 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 1613 | --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 |
| 1614 | |
| 1615 | Boot of a preloaded kernel image on Juno |
| 1616 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1617 | |
Antonio Nino Diaz | b188155 | 2018-05-14 09:12:34 +0100 | [diff] [blame] | 1618 | The Trusted Firmware must be compiled in a similar way as for FVP explained |
| 1619 | above. The process to load binaries to memory is the one explained in |
| 1620 | `Booting an EL3 payload on Juno`_. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1621 | |
| 1622 | Running the software on FVP |
| 1623 | --------------------------- |
| 1624 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1625 | The latest version of the AArch64 build of TF-A has been tested on the following |
| 1626 | Arm FVPs without shifted affinities, and that do not support threaded CPU cores |
| 1627 | (64-bit host machine only). |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1628 | |
David Cunado | 05845bf | 2017-12-19 16:33:25 +0000 | [diff] [blame] | 1629 | NOTE: Unless otherwise stated, the model version is Version 11.4 Build 37. |
David Cunado | 124415e | 2017-06-27 17:31:12 +0100 | [diff] [blame] | 1630 | |
David Cunado | 05845bf | 2017-12-19 16:33:25 +0000 | [diff] [blame] | 1631 | - ``FVP_Base_Aresx4`` |
| 1632 | - ``FVP_Base_AEMv8A-AEMv8A`` |
| 1633 | - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` |
| 1634 | - ``FVP_Base_AEMv8A-AEMv8A`` |
| 1635 | - ``FVP_Base_RevC-2xAEMv8A`` |
| 1636 | - ``FVP_Base_Cortex-A32x4`` |
David Cunado | 124415e | 2017-06-27 17:31:12 +0100 | [diff] [blame] | 1637 | - ``FVP_Base_Cortex-A35x4`` |
| 1638 | - ``FVP_Base_Cortex-A53x4`` |
David Cunado | 05845bf | 2017-12-19 16:33:25 +0000 | [diff] [blame] | 1639 | - ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` |
| 1640 | - ``FVP_Base_Cortex-A55x4`` |
David Cunado | 124415e | 2017-06-27 17:31:12 +0100 | [diff] [blame] | 1641 | - ``FVP_Base_Cortex-A57x4-A53x4`` |
| 1642 | - ``FVP_Base_Cortex-A57x4`` |
| 1643 | - ``FVP_Base_Cortex-A72x4-A53x4`` |
| 1644 | - ``FVP_Base_Cortex-A72x4`` |
| 1645 | - ``FVP_Base_Cortex-A73x4-A53x4`` |
| 1646 | - ``FVP_Base_Cortex-A73x4`` |
David Cunado | 05845bf | 2017-12-19 16:33:25 +0000 | [diff] [blame] | 1647 | - ``FVP_Base_Cortex-A75x4`` |
| 1648 | - ``FVP_Base_Cortex-A76x4`` |
| 1649 | - ``FVP_CSS_SGI-575`` (Version 11.3 build 40) |
| 1650 | - ``Foundation_Platform`` |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1651 | |
| 1652 | The latest version of the AArch32 build of TF-A has been tested on the following |
| 1653 | Arm FVPs without shifted affinities, and that do not support threaded CPU cores |
| 1654 | (64-bit host machine only). |
| 1655 | |
| 1656 | - ``FVP_Base_AEMv8A-AEMv8A`` |
David Cunado | 124415e | 2017-06-27 17:31:12 +0100 | [diff] [blame] | 1657 | - ``FVP_Base_Cortex-A32x4`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1658 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1659 | NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which |
| 1660 | is not compatible with legacy GIC configurations. Therefore this FVP does not |
| 1661 | support these legacy GIC configurations. |
| 1662 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1663 | NOTE: The build numbers quoted above are those reported by launching the FVP |
| 1664 | with the ``--version`` parameter. |
| 1665 | |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1666 | NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full |
| 1667 | file systems that can be downloaded separately. To run an FVP with a virtio |
| 1668 | file system image an additional FVP configuration option |
| 1669 | ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be |
| 1670 | used. |
| 1671 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1672 | NOTE: The software will not work on Version 1.0 of the Foundation FVP. |
| 1673 | The commands below would report an ``unhandled argument`` error in this case. |
| 1674 | |
| 1675 | NOTE: FVPs can be launched with ``--cadi-server`` option such that a |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1676 | CADI-compliant debugger (for example, Arm DS-5) can connect to and control its |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1677 | execution. |
| 1678 | |
Eleanor Bonnici | e124dc4 | 2017-10-04 15:03:33 +0100 | [diff] [blame] | 1679 | NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 |
David Cunado | 9730946 | 2017-07-31 12:24:51 +0100 | [diff] [blame] | 1680 | the internal synchronisation timings changed compared to older versions of the |
| 1681 | models. The models can be launched with ``-Q 100`` option if they are required |
| 1682 | to match the run time characteristics of the older versions. |
| 1683 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1684 | The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1685 | downloaded for free from `Arm's website`_. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1686 | |
David Cunado | 124415e | 2017-06-27 17:31:12 +0100 | [diff] [blame] | 1687 | The Cortex-A models listed above are also available to download from |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1688 | `Arm's website`_. |
David Cunado | 124415e | 2017-06-27 17:31:12 +0100 | [diff] [blame] | 1689 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1690 | Please refer to the FVP documentation for a detailed description of the model |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1691 | parameter options. A brief description of the important ones that affect TF-A |
| 1692 | and normal world software behavior is provided below. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1693 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1694 | Obtaining the Flattened Device Trees |
| 1695 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1696 | |
| 1697 | Depending on the FVP configuration and Linux configuration used, different |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1698 | FDT files are required. FDT source files for the Foundation and Base FVPs can |
| 1699 | be found in the TF-A source directory under ``fdts/``. The Foundation FVP has |
| 1700 | a subset of the Base FVP components. For example, the Foundation FVP lacks |
| 1701 | CLCD and MMC support, and has only one CPU cluster. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1702 | |
| 1703 | Note: It is not recommended to use the FDTs built along the kernel because not |
| 1704 | all FDTs are available from there. |
| 1705 | |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1706 | The dynamic configuration capability is enabled in the firmware for FVPs. |
| 1707 | This means that the firmware can authenticate and load the FDT if present in |
| 1708 | FIP. A default FDT is packaged into FIP during the build based on |
| 1709 | the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` |
| 1710 | or ``FVP_HW_CONFIG_DTS`` build options (refer to the |
| 1711 | `Arm FVP platform specific build options`_ section for detail on the options). |
| 1712 | |
| 1713 | - ``fvp-base-gicv2-psci.dts`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1714 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1715 | For use with models such as the Cortex-A57-A53 Base FVPs without shifted |
| 1716 | affinities and with Base memory map configuration. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1717 | |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1718 | - ``fvp-base-gicv2-psci-aarch32.dts`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1719 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1720 | For use with models such as the Cortex-A32 Base FVPs without shifted |
| 1721 | affinities and running Linux in AArch32 state with Base memory map |
| 1722 | configuration. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1723 | |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1724 | - ``fvp-base-gicv3-psci.dts`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1725 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1726 | For use with models such as the Cortex-A57-A53 Base FVPs without shifted |
| 1727 | affinities and with Base memory map configuration and Linux GICv3 support. |
| 1728 | |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1729 | - ``fvp-base-gicv3-psci-1t.dts`` |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1730 | |
| 1731 | For use with models such as the AEMv8-RevC Base FVP with shifted affinities, |
| 1732 | single threaded CPUs, Base memory map configuration and Linux GICv3 support. |
| 1733 | |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1734 | - ``fvp-base-gicv3-psci-dynamiq.dts`` |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1735 | |
| 1736 | For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, |
| 1737 | single cluster, single threaded CPUs, Base memory map configuration and Linux |
| 1738 | GICv3 support. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1739 | |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1740 | - ``fvp-base-gicv3-psci-aarch32.dts`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1741 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1742 | For use with models such as the Cortex-A32 Base FVPs without shifted |
| 1743 | affinities and running Linux in AArch32 state with Base memory map |
| 1744 | configuration and Linux GICv3 support. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1745 | |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1746 | - ``fvp-foundation-gicv2-psci.dts`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1747 | |
| 1748 | For use with Foundation FVP with Base memory map configuration. |
| 1749 | |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1750 | - ``fvp-foundation-gicv3-psci.dts`` |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1751 | |
| 1752 | (Default) For use with Foundation FVP with Base memory map configuration |
| 1753 | and Linux GICv3 support. |
| 1754 | |
| 1755 | Running on the Foundation FVP with reset to BL1 entrypoint |
| 1756 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1757 | |
| 1758 | The following ``Foundation_Platform`` parameters should be used to boot Linux with |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1759 | 4 CPUs using the AArch64 build of TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1760 | |
| 1761 | :: |
| 1762 | |
| 1763 | <path-to>/Foundation_Platform \ |
| 1764 | --cores=4 \ |
Antonio Nino Diaz | b44eda5 | 2018-02-23 11:01:31 +0000 | [diff] [blame] | 1765 | --arm-v8.0 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1766 | --secure-memory \ |
| 1767 | --visualization \ |
| 1768 | --gicv3 \ |
| 1769 | --data="<path-to>/<bl1-binary>"@0x0 \ |
| 1770 | --data="<path-to>/<FIP-binary>"@0x08000000 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1771 | --data="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1772 | --data="<path-to>/<ramdisk-binary>"@0x84000000 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1773 | |
| 1774 | Notes: |
| 1775 | |
| 1776 | - BL1 is loaded at the start of the Trusted ROM. |
| 1777 | - The Firmware Image Package is loaded at the start of NOR FLASH0. |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1778 | - The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address |
| 1779 | is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1780 | - The default use-case for the Foundation FVP is to use the ``--gicv3`` option |
| 1781 | and enable the GICv3 device in the model. Note that without this option, |
| 1782 | the Foundation FVP defaults to legacy (Versatile Express) memory map which |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1783 | is not supported by TF-A. |
| 1784 | - In order for TF-A to run correctly on the Foundation FVP, the architecture |
| 1785 | versions must match. The Foundation FVP defaults to the highest v8.x |
| 1786 | version it supports but the default build for TF-A is for v8.0. To avoid |
| 1787 | issues either start the Foundation FVP to use v8.0 architecture using the |
| 1788 | ``--arm-v8.0`` option, or build TF-A with an appropriate value for |
| 1789 | ``ARM_ARCH_MINOR``. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1790 | |
| 1791 | Running on the AEMv8 Base FVP with reset to BL1 entrypoint |
| 1792 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1793 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1794 | The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1795 | with 8 CPUs using the AArch64 build of TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1796 | |
| 1797 | :: |
| 1798 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1799 | <path-to>/FVP_Base_RevC-2xAEMv8A \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1800 | -C pctl.startup=0.0.0.0 \ |
| 1801 | -C bp.secure_memory=1 \ |
| 1802 | -C bp.tzc_400.diagnostics=1 \ |
| 1803 | -C cluster0.NUM_CORES=4 \ |
| 1804 | -C cluster1.NUM_CORES=4 \ |
| 1805 | -C cache_state_modelled=1 \ |
| 1806 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 1807 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1808 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1809 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1810 | |
| 1811 | Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint |
| 1812 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1813 | |
| 1814 | The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1815 | with 8 CPUs using the AArch32 build of TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1816 | |
| 1817 | :: |
| 1818 | |
| 1819 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 1820 | -C pctl.startup=0.0.0.0 \ |
| 1821 | -C bp.secure_memory=1 \ |
| 1822 | -C bp.tzc_400.diagnostics=1 \ |
| 1823 | -C cluster0.NUM_CORES=4 \ |
| 1824 | -C cluster1.NUM_CORES=4 \ |
| 1825 | -C cache_state_modelled=1 \ |
| 1826 | -C cluster0.cpu0.CONFIG64=0 \ |
| 1827 | -C cluster0.cpu1.CONFIG64=0 \ |
| 1828 | -C cluster0.cpu2.CONFIG64=0 \ |
| 1829 | -C cluster0.cpu3.CONFIG64=0 \ |
| 1830 | -C cluster1.cpu0.CONFIG64=0 \ |
| 1831 | -C cluster1.cpu1.CONFIG64=0 \ |
| 1832 | -C cluster1.cpu2.CONFIG64=0 \ |
| 1833 | -C cluster1.cpu3.CONFIG64=0 \ |
| 1834 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 1835 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1836 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1837 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1838 | |
| 1839 | Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint |
| 1840 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1841 | |
| 1842 | The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1843 | boot Linux with 8 CPUs using the AArch64 build of TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1844 | |
| 1845 | :: |
| 1846 | |
| 1847 | <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ |
| 1848 | -C pctl.startup=0.0.0.0 \ |
| 1849 | -C bp.secure_memory=1 \ |
| 1850 | -C bp.tzc_400.diagnostics=1 \ |
| 1851 | -C cache_state_modelled=1 \ |
| 1852 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 1853 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1854 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1855 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1856 | |
| 1857 | Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint |
| 1858 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1859 | |
| 1860 | The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1861 | boot Linux with 4 CPUs using the AArch32 build of TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1862 | |
| 1863 | :: |
| 1864 | |
| 1865 | <path-to>/FVP_Base_Cortex-A32x4 \ |
| 1866 | -C pctl.startup=0.0.0.0 \ |
| 1867 | -C bp.secure_memory=1 \ |
| 1868 | -C bp.tzc_400.diagnostics=1 \ |
| 1869 | -C cache_state_modelled=1 \ |
| 1870 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 1871 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1872 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1873 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1874 | |
| 1875 | Running on the AEMv8 Base FVP with reset to BL31 entrypoint |
| 1876 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1877 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1878 | The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1879 | with 8 CPUs using the AArch64 build of TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1880 | |
| 1881 | :: |
| 1882 | |
David Cunado | 7c03264 | 2018-03-12 18:47:05 +0000 | [diff] [blame] | 1883 | <path-to>/FVP_Base_RevC-2xAEMv8A \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1884 | -C pctl.startup=0.0.0.0 \ |
| 1885 | -C bp.secure_memory=1 \ |
| 1886 | -C bp.tzc_400.diagnostics=1 \ |
| 1887 | -C cluster0.NUM_CORES=4 \ |
| 1888 | -C cluster1.NUM_CORES=4 \ |
| 1889 | -C cache_state_modelled=1 \ |
Soby Mathew | ba678c3 | 2018-12-12 14:54:23 +0000 | [diff] [blame] | 1890 | -C cluster0.cpu0.RVBAR=0x04010000 \ |
| 1891 | -C cluster0.cpu1.RVBAR=0x04010000 \ |
| 1892 | -C cluster0.cpu2.RVBAR=0x04010000 \ |
| 1893 | -C cluster0.cpu3.RVBAR=0x04010000 \ |
| 1894 | -C cluster1.cpu0.RVBAR=0x04010000 \ |
| 1895 | -C cluster1.cpu1.RVBAR=0x04010000 \ |
| 1896 | -C cluster1.cpu2.RVBAR=0x04010000 \ |
| 1897 | -C cluster1.cpu3.RVBAR=0x04010000 \ |
| 1898 | --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ |
| 1899 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1900 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1901 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1902 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1903 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1904 | |
| 1905 | Notes: |
| 1906 | |
Soby Mathew | ba678c3 | 2018-12-12 14:54:23 +0000 | [diff] [blame] | 1907 | - Since Position Independent Executable (PIE) support is enabled for BL31 |
| 1908 | in this config, it can be loaded at any valid address for execution. |
| 1909 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1910 | - Since a FIP is not loaded when using BL31 as reset entrypoint, the |
| 1911 | ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` |
| 1912 | parameter is needed to load the individual bootloader images in memory. |
| 1913 | BL32 image is only needed if BL31 has been built to expect a Secure-EL1 |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 1914 | Payload. For the same reason, the FDT needs to be compiled from the DT source |
| 1915 | and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` |
| 1916 | parameter. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1917 | |
| 1918 | - The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where |
| 1919 | X and Y are the cluster and CPU numbers respectively, is used to set the |
| 1920 | reset vector for each core. |
| 1921 | |
| 1922 | - Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require |
| 1923 | changing the value of |
| 1924 | ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of |
| 1925 | ``BL32_BASE``. |
| 1926 | |
| 1927 | Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint |
| 1928 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1929 | |
| 1930 | The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1931 | with 8 CPUs using the AArch32 build of TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1932 | |
| 1933 | :: |
| 1934 | |
| 1935 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 1936 | -C pctl.startup=0.0.0.0 \ |
| 1937 | -C bp.secure_memory=1 \ |
| 1938 | -C bp.tzc_400.diagnostics=1 \ |
| 1939 | -C cluster0.NUM_CORES=4 \ |
| 1940 | -C cluster1.NUM_CORES=4 \ |
| 1941 | -C cache_state_modelled=1 \ |
| 1942 | -C cluster0.cpu0.CONFIG64=0 \ |
| 1943 | -C cluster0.cpu1.CONFIG64=0 \ |
| 1944 | -C cluster0.cpu2.CONFIG64=0 \ |
| 1945 | -C cluster0.cpu3.CONFIG64=0 \ |
| 1946 | -C cluster1.cpu0.CONFIG64=0 \ |
| 1947 | -C cluster1.cpu1.CONFIG64=0 \ |
| 1948 | -C cluster1.cpu2.CONFIG64=0 \ |
| 1949 | -C cluster1.cpu3.CONFIG64=0 \ |
Soby Mathew | ba678c3 | 2018-12-12 14:54:23 +0000 | [diff] [blame] | 1950 | -C cluster0.cpu0.RVBAR=0x04002000 \ |
| 1951 | -C cluster0.cpu1.RVBAR=0x04002000 \ |
| 1952 | -C cluster0.cpu2.RVBAR=0x04002000 \ |
| 1953 | -C cluster0.cpu3.RVBAR=0x04002000 \ |
| 1954 | -C cluster1.cpu0.RVBAR=0x04002000 \ |
| 1955 | -C cluster1.cpu1.RVBAR=0x04002000 \ |
| 1956 | -C cluster1.cpu2.RVBAR=0x04002000 \ |
| 1957 | -C cluster1.cpu3.RVBAR=0x04002000 \ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 1958 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1959 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1960 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1961 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1962 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1963 | |
| 1964 | Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``. |
| 1965 | It should match the address programmed into the RVBAR register as well. |
| 1966 | |
| 1967 | Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint |
| 1968 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1969 | |
| 1970 | The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1971 | boot Linux with 8 CPUs using the AArch64 build of TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1972 | |
| 1973 | :: |
| 1974 | |
| 1975 | <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ |
| 1976 | -C pctl.startup=0.0.0.0 \ |
| 1977 | -C bp.secure_memory=1 \ |
| 1978 | -C bp.tzc_400.diagnostics=1 \ |
| 1979 | -C cache_state_modelled=1 \ |
Soby Mathew | ba678c3 | 2018-12-12 14:54:23 +0000 | [diff] [blame] | 1980 | -C cluster0.cpu0.RVBARADDR=0x04010000 \ |
| 1981 | -C cluster0.cpu1.RVBARADDR=0x04010000 \ |
| 1982 | -C cluster0.cpu2.RVBARADDR=0x04010000 \ |
| 1983 | -C cluster0.cpu3.RVBARADDR=0x04010000 \ |
| 1984 | -C cluster1.cpu0.RVBARADDR=0x04010000 \ |
| 1985 | -C cluster1.cpu1.RVBARADDR=0x04010000 \ |
| 1986 | -C cluster1.cpu2.RVBARADDR=0x04010000 \ |
| 1987 | -C cluster1.cpu3.RVBARADDR=0x04010000 \ |
| 1988 | --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ |
| 1989 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1990 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1991 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1992 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 1993 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 1994 | |
| 1995 | Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint |
| 1996 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 1997 | |
| 1998 | The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 1999 | boot Linux with 4 CPUs using the AArch32 build of TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2000 | |
| 2001 | :: |
| 2002 | |
| 2003 | <path-to>/FVP_Base_Cortex-A32x4 \ |
| 2004 | -C pctl.startup=0.0.0.0 \ |
| 2005 | -C bp.secure_memory=1 \ |
| 2006 | -C bp.tzc_400.diagnostics=1 \ |
| 2007 | -C cache_state_modelled=1 \ |
Soby Mathew | ba678c3 | 2018-12-12 14:54:23 +0000 | [diff] [blame] | 2008 | -C cluster0.cpu0.RVBARADDR=0x04002000 \ |
| 2009 | -C cluster0.cpu1.RVBARADDR=0x04002000 \ |
| 2010 | -C cluster0.cpu2.RVBARADDR=0x04002000 \ |
| 2011 | -C cluster0.cpu3.RVBARADDR=0x04002000 \ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 2012 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2013 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 2014 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2015 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 2016 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2017 | |
| 2018 | Running the software on Juno |
| 2019 | ---------------------------- |
| 2020 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2021 | This version of TF-A has been tested on variants r0, r1 and r2 of Juno. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2022 | |
| 2023 | To execute the software stack on Juno, the version of the Juno board recovery |
| 2024 | image indicated in the `Linaro Release Notes`_ must be installed. If you have an |
| 2025 | earlier version installed or are unsure which version is installed, please |
| 2026 | re-install the recovery image by following the |
| 2027 | `Instructions for using Linaro's deliverables on Juno`_. |
| 2028 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2029 | Preparing TF-A images |
| 2030 | ~~~~~~~~~~~~~~~~~~~~~ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2031 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2032 | After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the |
| 2033 | ``SOFTWARE/`` directory of the Juno SD card. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2034 | |
| 2035 | Other Juno software information |
| 2036 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2037 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2038 | Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2039 | software information. Please also refer to the `Juno Getting Started Guide`_ to |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2040 | get more detailed information about the Juno Arm development platform and how to |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2041 | configure it. |
| 2042 | |
| 2043 | Testing SYSTEM SUSPEND on Juno |
| 2044 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2045 | |
| 2046 | The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend |
| 2047 | to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend |
| 2048 | on Juno, at the linux shell prompt, issue the following command: |
| 2049 | |
| 2050 | :: |
| 2051 | |
| 2052 | echo +10 > /sys/class/rtc/rtc0/wakealarm |
| 2053 | echo -n mem > /sys/power/state |
| 2054 | |
| 2055 | The Juno board should suspend to RAM and then wakeup after 10 seconds due to |
| 2056 | wakeup interrupt from RTC. |
| 2057 | |
| 2058 | -------------- |
| 2059 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2060 | *Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.* |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2061 | |
David Cunado | b2de099 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 2062 | .. _Linaro: `Linaro Release Notes`_ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 2063 | .. _Linaro Release: `Linaro Release Notes`_ |
David Cunado | 82509be | 2017-12-19 16:33:25 +0000 | [diff] [blame] | 2064 | .. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-linaro-release-notes |
David Cunado | 82509be | 2017-12-19 16:33:25 +0000 | [diff] [blame] | 2065 | .. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/linaro-software-deliverables |
| 2066 | .. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2067 | .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/ |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2068 | .. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php |
Paul Beesley | 8b4bdeb | 2019-01-21 12:06:24 +0000 | [diff] [blame] | 2069 | .. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html |
Sandrine Bailleux | 771535b | 2018-09-20 10:27:13 +0200 | [diff] [blame] | 2070 | .. _Linux master tree: https://github.com/torvalds/linux/tree/master/ |
Antonio Nino Diaz | b5d6809 | 2017-05-23 11:49:22 +0100 | [diff] [blame] | 2071 | .. _Dia: https://wiki.gnome.org/Apps/Dia/Download |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 2072 | .. _here: psci-lib-integration-guide.rst |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2073 | .. _Trusted Board Boot: trusted-board-boot.rst |
Soby Mathew | ecd94ad | 2018-05-09 13:59:29 +0100 | [diff] [blame] | 2074 | .. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2075 | .. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 2076 | .. _Firmware Update: firmware-update.rst |
| 2077 | .. _Firmware Design: firmware-design.rst |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2078 | .. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git |
| 2079 | .. _mbed TLS Security Center: https://tls.mbed.org/security |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 2080 | .. _Arm's website: `FVP models`_ |
Eleanor Bonnici | c61b22e | 2017-07-07 14:33:24 +0100 | [diff] [blame] | 2081 | .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 2082 | .. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf |
David Cunado | b2de099 | 2017-06-29 12:01:33 +0100 | [diff] [blame] | 2083 | .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf |
Sandrine Bailleux | 604f0a4 | 2018-09-20 12:44:39 +0200 | [diff] [blame] | 2084 | .. _Secure Partition Manager Design guide: secure-partition-manager-design.rst |
Paul Beesley | 8b4bdeb | 2019-01-21 12:06:24 +0000 | [diff] [blame] | 2085 | .. _`Trusted Firmware-A Coding Guidelines`: coding-guidelines.rst |