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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Manish V Badarkhedd6f2522021-02-22 17:30:17 +00002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
10#include <platform_def.h>
11
Zelalem Aweke5085abd2021-07-13 17:19:54 -050012#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <arch_helpers.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
16#include <common/desc_image_load.h>
17#include <drivers/generic_delay_timer.h>
Manish V Badarkhedd6f2522021-02-22 17:30:17 +000018#include <drivers/partition/partition.h>
Louis Mayencourt81bd9162019-10-17 15:14:25 +010019#include <lib/fconf/fconf.h>
Manish V Badarkhe99a8e142020-06-11 22:32:11 +010020#include <lib/fconf/fconf_dyn_cfg_getter.h>
johpow019d134022021-06-16 17:57:28 -050021#if ENABLE_RME
22#include <lib/gpt_rme/gpt_rme.h>
23#endif /* ENABLE_RME */
Summer Qin9db8f2e2017-04-24 16:49:28 +010024#ifdef SPD_opteed
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000025#include <lib/optee_utils.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010026#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000027#include <lib/utils.h>
johpow019d134022021-06-16 17:57:28 -050028#if ENABLE_RME
Zelalem Aweke5085abd2021-07-13 17:19:54 -050029#include <plat/arm/common/arm_pas_def.h>
johpow019d134022021-06-16 17:57:28 -050030#endif /* ENABLE_RME */
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000031#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000032#include <plat/common/platform.h>
33
Dan Handley9df48042015-03-19 18:58:55 +000034/* Data structure which holds the extents of the trusted SRAM for BL2 */
35static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
36
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +010037/* Base address of fw_config received from BL1 */
Jimmy Brissond7297c72020-08-05 14:05:53 -050038static uintptr_t config_base;
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +010039
Soby Mathewc44110d2018-02-20 12:50:47 +000040/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010041 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
Soby Mathewaf14b462018-06-01 16:53:38 +010042 * for `meminfo_t` data structure and fw_configs passed from BL1.
Soby Mathewc44110d2018-02-20 12:50:47 +000043 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010044CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
Soby Mathewc44110d2018-02-20 12:50:47 +000045
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010046/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000047#pragma weak bl2_early_platform_setup2
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010048#pragma weak bl2_platform_setup
49#pragma weak bl2_plat_arch_setup
50#pragma weak bl2_plat_sec_mem_layout
51
Zelalem Aweke65e92632021-07-12 22:33:55 -050052#if ENABLE_RME
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010053#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
54 bl2_tzram_layout.total_base, \
55 bl2_tzram_layout.total_size, \
Zelalem Aweke65e92632021-07-12 22:33:55 -050056 MT_MEMORY | MT_RW | MT_ROOT)
57#else
58#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
59 bl2_tzram_layout.total_base, \
60 bl2_tzram_layout.total_size, \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010061 MT_MEMORY | MT_RW | MT_SECURE)
Zelalem Aweke65e92632021-07-12 22:33:55 -050062#endif /* ENABLE_RME */
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010063
Daniel Boulby07d26872018-06-27 16:45:48 +010064#pragma weak arm_bl2_plat_handle_post_image_load
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010065
Dan Handley9df48042015-03-19 18:58:55 +000066/*******************************************************************************
67 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
68 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
69 * Copy it to a safe location before its reclaimed by later BL2 functionality.
70 ******************************************************************************/
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010071void arm_bl2_early_platform_setup(uintptr_t fw_config,
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020072 struct meminfo *mem_layout)
Dan Handley9df48042015-03-19 18:58:55 +000073{
74 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010075 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000076
77 /* Setup the BL2 memory layout */
78 bl2_tzram_layout = *mem_layout;
79
Jimmy Brissond7297c72020-08-05 14:05:53 -050080 config_base = fw_config;
Louis Mayencourt81bd9162019-10-17 15:14:25 +010081
Dan Handley9df48042015-03-19 18:58:55 +000082 /* Initialise the IO layer and register platform IO devices */
83 plat_arm_io_setup();
Manish V Badarkhedd6f2522021-02-22 17:30:17 +000084
85 /* Load partition table */
86#if ARM_GPT_SUPPORT
87 partition_init(GPT_IMAGE_ID);
88#endif /* ARM_GPT_SUPPORT */
89
Dan Handley9df48042015-03-19 18:58:55 +000090}
91
Soby Mathew7d5a2e72018-01-10 15:59:31 +000092void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +000093{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000094 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
95
Soby Mathew1ced6b82017-06-12 12:37:10 +010096 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +000097}
98
99/*
Soby Mathew45e39e22018-03-26 15:16:46 +0100100 * Perform BL2 preload setup. Currently we initialise the dynamic
101 * configuration here.
Dan Handley9df48042015-03-19 18:58:55 +0000102 */
Soby Mathew45e39e22018-03-26 15:16:46 +0100103void bl2_plat_preload_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +0000104{
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000105 arm_bl2_dyn_cfg_init();
Manish V Badarkhedd6f2522021-02-22 17:30:17 +0000106
Manish V Badarkhed2f0a7a2021-06-25 23:43:33 +0100107#if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT
108 /* Always use the FIP from bank 0 */
109 arm_set_fip_addr(0U);
110#endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */
Soby Mathew45e39e22018-03-26 15:16:46 +0100111}
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000112
Soby Mathew45e39e22018-03-26 15:16:46 +0100113/*
114 * Perform ARM standard platform setup.
115 */
116void arm_bl2_platform_setup(void)
117{
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500118#if !ENABLE_RME
Dan Handley9df48042015-03-19 18:58:55 +0000119 /* Initialize the secure environment */
120 plat_arm_security_setup();
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500121#endif
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100122
123#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargas550eb082018-01-05 16:00:05 +0000124 arm_nor_psci_do_static_mem_protect();
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100125#endif
Dan Handley9df48042015-03-19 18:58:55 +0000126}
127
128void bl2_platform_setup(void)
129{
130 arm_bl2_platform_setup();
131}
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500132
133#if ENABLE_RME
johpow019d134022021-06-16 17:57:28 -0500134
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500135static void arm_bl2_plat_gpt_setup(void)
136{
137 /*
138 * The GPT library might modify the gpt regions structure to optimize
139 * the layout, so the array cannot be constant.
140 */
141 pas_region_t pas_regions[] = {
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500142 ARM_PAS_KERNEL,
johpow019d134022021-06-16 17:57:28 -0500143 ARM_PAS_SECURE,
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500144 ARM_PAS_REALM,
145 ARM_PAS_EL3_DRAM,
AlexeiFedorovaa442492022-11-29 13:32:41 +0000146 ARM_PAS_GPTS,
147 ARM_PAS_KERNEL_1
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500148 };
149
johpow019d134022021-06-16 17:57:28 -0500150 /* Initialize entire protected space to GPT_GPI_ANY. */
AlexeiFedorovaa442492022-11-29 13:32:41 +0000151 if (gpt_init_l0_tables(GPCCR_PPS_64GB, ARM_L0_GPT_ADDR_BASE,
johpow019d134022021-06-16 17:57:28 -0500152 ARM_L0_GPT_SIZE) < 0) {
153 ERROR("gpt_init_l0_tables() failed!\n");
154 panic();
155 }
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500156
johpow019d134022021-06-16 17:57:28 -0500157 /* Carve out defined PAS ranges. */
158 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K,
159 ARM_L1_GPT_ADDR_BASE,
160 ARM_L1_GPT_SIZE,
161 pas_regions,
162 (unsigned int)(sizeof(pas_regions) /
163 sizeof(pas_region_t))) < 0) {
164 ERROR("gpt_init_pas_l1_tables() failed!\n");
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500165 panic();
166 }
167
johpow019d134022021-06-16 17:57:28 -0500168 INFO("Enabling Granule Protection Checks\n");
169 if (gpt_enable() < 0) {
170 ERROR("gpt_enable() failed!\n");
171 panic();
172 }
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500173}
johpow019d134022021-06-16 17:57:28 -0500174
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500175#endif /* ENABLE_RME */
Dan Handley9df48042015-03-19 18:58:55 +0000176
177/*******************************************************************************
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500178 * Perform the very early platform specific architectural setup here.
179 * When RME is enabled the secure environment is initialised before
180 * initialising and enabling Granule Protection.
181 * This function initialises the MMU in a quick and dirty way.
Dan Handley9df48042015-03-19 18:58:55 +0000182 ******************************************************************************/
183void arm_bl2_plat_arch_setup(void)
184{
Soby Mathewb9856482018-09-18 11:42:42 +0100185#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
186 /*
187 * Ensure ARM platforms don't use coherent memory in BL2 unless
188 * cryptocell integration is enabled.
189 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100190 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000191#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100192
193 const mmap_region_t bl_regions[] = {
194 MAP_BL2_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100195 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100196#if USE_ROMLIB
197 ARM_MAP_ROMLIB_CODE,
198 ARM_MAP_ROMLIB_DATA,
199#endif
Soby Mathewb9856482018-09-18 11:42:42 +0100200#if ARM_CRYPTOCELL_INTEG
201 ARM_MAP_BL_COHERENT_RAM,
202#endif
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100203 ARM_MAP_BL_CONFIG_REGION,
Zelalem Awekec43c5632021-07-12 23:41:05 -0500204#if ENABLE_RME
205 ARM_MAP_L0_GPT_REGION,
206#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100207 {0}
208 };
209
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500210#if ENABLE_RME
211 /* Initialise the secure environment */
212 plat_arm_security_setup();
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500213#endif
Roberto Vargas344ff022018-10-19 16:44:18 +0100214 setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100215
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700216#ifdef __aarch64__
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500217#if ENABLE_RME
218 /* BL2 runs in EL3 when RME enabled. */
219 assert(get_armv9_2_feat_rme_support() != 0U);
220 enable_mmu_el3(0);
johpow019d134022021-06-16 17:57:28 -0500221
222 /* Initialise and enable granule protection after MMU. */
223 arm_bl2_plat_gpt_setup();
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500224#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100225 enable_mmu_el1(0);
Zelalem Aweke5085abd2021-07-13 17:19:54 -0500226#endif
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700227#else
228 enable_mmu_svc_mon(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100229#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100230
231 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000232}
233
234void bl2_plat_arch_setup(void)
235{
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100236 const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
237
Dan Handley9df48042015-03-19 18:58:55 +0000238 arm_bl2_plat_arch_setup();
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100239
240 /* Fill the properties struct with the info from the config dtb */
Jimmy Brissond7297c72020-08-05 14:05:53 -0500241 fconf_populate("FW_CONFIG", config_base);
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100242
243 /* TB_FW_CONFIG was also loaded by BL1 */
244 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
245 assert(tb_fw_config_info != NULL);
246
247 fconf_populate("TB_FW", tb_fw_config_info->config_addr);
Dan Handley9df48042015-03-19 18:58:55 +0000248}
249
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000250int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100251{
252 int err = 0;
253 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100254#ifdef SPD_opteed
255 bl_mem_params_node_t *pager_mem_params = NULL;
256 bl_mem_params_node_t *paged_mem_params = NULL;
257#endif
Zelaleme8dadb12020-02-05 14:12:39 -0600258 assert(bl_mem_params != NULL);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100259
260 switch (image_id) {
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700261#ifdef __aarch64__
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100262 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100263#ifdef SPD_opteed
264 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
265 assert(pager_mem_params);
266
267 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
268 assert(paged_mem_params);
269
270 err = parse_optee_header(&bl_mem_params->ep_info,
271 &pager_mem_params->image_info,
272 &paged_mem_params->image_info);
273 if (err != 0) {
274 WARN("OPTEE header parse error.\n");
275 }
276#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100277 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
278 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100279#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100280
281 case BL33_IMAGE_ID:
282 /* BL33 expects to receive the primary CPU MPID (through r0) */
283 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
284 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
285 break;
286
287#ifdef SCP_BL2_BASE
288 case SCP_BL2_IMAGE_ID:
289 /* The subsequent handling of SCP_BL2 is platform specific */
290 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
291 if (err) {
292 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
293 }
294 break;
295#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000296 default:
297 /* Do nothing in default case */
298 break;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100299 }
300
301 return err;
302}
303
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000304/*******************************************************************************
305 * This function can be used by the platforms to update/use image
306 * information for given `image_id`.
307 ******************************************************************************/
Daniel Boulby07d26872018-06-27 16:45:48 +0100308int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000309{
Balint Dobszay719ba9c2021-03-26 16:23:18 +0100310#if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD
Manish Pandey1fa6ecb2020-02-25 11:38:19 +0000311 /* For Secure Partitions we don't need post processing */
312 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) &&
313 (image_id < MAX_NUMBER_IDS)) {
314 return 0;
315 }
316#endif
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000317 return arm_bl2_handle_post_image_load(image_id);
318}
319
Daniel Boulby07d26872018-06-27 16:45:48 +0100320int bl2_plat_handle_post_image_load(unsigned int image_id)
321{
322 return arm_bl2_plat_handle_post_image_load(image_id);
323}