blob: e07db300b56c6c3651742da21111a9298ded3ad7 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diazc326c342019-01-11 11:20:10 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00007#ifndef ARCH_HELPERS_H
8#define ARCH_HELPERS_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000010#include <cdefs.h>
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000011#include <stdbool.h>
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010012#include <stdint.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010013#include <string.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010014
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <arch.h>
16
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010017/**********************************************************************
18 * Macros which create inline functions to read or write CPU system
19 * registers
20 *********************************************************************/
21
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000022#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090023static inline u_register_t read_ ## _name(void) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000024{ \
Masahiro Yamada6292d772018-02-02 21:19:17 +090025 u_register_t v; \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000026 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
27 return v; \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010028}
29
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000030#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
Masahiro Yamada6292d772018-02-02 21:19:17 +090031static inline void write_ ## _name(u_register_t v) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000032{ \
33 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010034}
35
Roberto Vargasc51cdb72017-09-18 09:53:25 +010036#define SYSREG_WRITE_CONST(reg_name, v) \
37 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010038
39/* Define read function for system register */
40#define DEFINE_SYSREG_READ_FUNC(_name) \
41 _DEFINE_SYSREG_READ_FUNC(_name, _name)
42
43/* Define read & write function for system register */
44#define DEFINE_SYSREG_RW_FUNCS(_name) \
45 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
46 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
47
48/* Define read & write function for renamed system register */
49#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
50 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
51 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
52
Achin Gupta92712a52015-09-03 14:18:02 +010053/* Define read function for renamed system register */
54#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
55 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
56
57/* Define write function for renamed system register */
58#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
60
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010061/**********************************************************************
62 * Macros to create inline functions for system instructions
63 *********************************************************************/
64
65/* Define function for simple system instruction */
66#define DEFINE_SYSOP_FUNC(_op) \
Juan Castillo2d552402014-06-13 17:05:10 +010067static inline void _op(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010068{ \
69 __asm__ (#_op); \
70}
71
72/* Define function for system instruction with type specifier */
73#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
Juan Castillo2d552402014-06-13 17:05:10 +010074static inline void _op ## _type(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010075{ \
76 __asm__ (#_op " " #_type); \
77}
78
79/* Define function for system instruction with register parameter */
80#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
81static inline void _op ## _type(uint64_t v) \
82{ \
83 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
84}
Achin Gupta4f6ad662013-10-25 09:08:21 +010085
86/*******************************************************************************
87 * TLB maintenance accessor prototypes
88 ******************************************************************************/
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +000089
90#if ERRATA_A57_813419
91/*
92 * Define function for TLBI instruction with type specifier that implements
93 * the workaround for errata 813419 of Cortex-A57.
94 */
95#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\
96static inline void tlbi ## _type(void) \
97{ \
98 __asm__("tlbi " #_type "\n" \
99 "dsb ish\n" \
100 "tlbi " #_type); \
101}
102
103/*
104 * Define function for TLBI instruction with register parameter that implements
105 * the workaround for errata 813419 of Cortex-A57.
106 */
107#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \
108static inline void tlbi ## _type(uint64_t v) \
109{ \
110 __asm__("tlbi " #_type ", %0\n" \
111 "dsb ish\n" \
112 "tlbi " #_type ", %0" : : "r" (v)); \
113}
114#endif /* ERRATA_A57_813419 */
115
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100116DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
117DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
118DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
119DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000120#if ERRATA_A57_813419
121DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3)
122DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is)
123#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100124DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
125DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000126#endif
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100127DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128
Antonio Nino Diazac998032017-02-27 17:23:54 +0000129DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
130DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
131DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
132DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000133#if ERRATA_A57_813419
134DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is)
135DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is)
136#else
Antonio Nino Diazac998032017-02-27 17:23:54 +0000137DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
138DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000139#endif
Antonio Nino Diazac998032017-02-27 17:23:54 +0000140
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141/*******************************************************************************
142 * Cache maintenance accessor prototypes
143 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100144DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
145DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
146DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
147DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
148DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
149DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
150DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
151DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
152
Varun Wadekar97625e32015-03-13 14:59:03 +0530153/*******************************************************************************
154 * Address translation accessor prototypes
155 ******************************************************************************/
156DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
157DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
158DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
159DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
Douglas Raillard77414632018-08-21 12:54:45 +0100160DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100161DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
Douglas Raillard77414632018-08-21 12:54:45 +0100162DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
Varun Wadekar97625e32015-03-13 14:59:03 +0530163
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000164void flush_dcache_range(uintptr_t addr, size_t size);
165void clean_dcache_range(uintptr_t addr, size_t size);
166void inv_dcache_range(uintptr_t addr, size_t size);
167
168void dcsw_op_louis(u_register_t op_type);
169void dcsw_op_all(u_register_t op_type);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100170
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100171void disable_mmu_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100172void disable_mmu_el3(void);
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100173void disable_mmu_icache_el1(void);
Dan Handleya17fefa2014-05-14 12:38:32 +0100174void disable_mmu_icache_el3(void);
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100175
Achin Gupta4f6ad662013-10-25 09:08:21 +0100176/*******************************************************************************
177 * Misc. accessor prototypes
178 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179
Roberto Vargasc51cdb72017-09-18 09:53:25 +0100180#define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
181#define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100182
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000183DEFINE_SYSREG_RW_FUNCS(par_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100184DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000185DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100186DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
dp-armee3457b2017-05-23 09:32:49 +0100187DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
Varun Wadekard1301a92019-01-23 09:41:28 -0800188DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100189DEFINE_SYSREG_READ_FUNC(CurrentEl)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000190DEFINE_SYSREG_READ_FUNC(ctr_el0)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100191DEFINE_SYSREG_RW_FUNCS(daif)
192DEFINE_SYSREG_RW_FUNCS(spsr_el1)
193DEFINE_SYSREG_RW_FUNCS(spsr_el2)
194DEFINE_SYSREG_RW_FUNCS(spsr_el3)
195DEFINE_SYSREG_RW_FUNCS(elr_el1)
196DEFINE_SYSREG_RW_FUNCS(elr_el2)
197DEFINE_SYSREG_RW_FUNCS(elr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100199DEFINE_SYSOP_FUNC(wfi)
200DEFINE_SYSOP_FUNC(wfe)
201DEFINE_SYSOP_FUNC(sev)
202DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
Soby Mathewed995662014-12-30 16:11:42 +0000203DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Juan Castillo2e86cb12016-01-13 15:01:09 +0000204DEFINE_SYSOP_TYPE_FUNC(dmb, st)
205DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Soby Mathewed995662014-12-30 16:11:42 +0000206DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100207DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000208DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000209DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
210DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
211DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
212DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
213DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
214DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
215DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100216DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000217DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100218DEFINE_SYSOP_FUNC(isb)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100219
Antonio Nino Diazb4e3e4b2018-11-23 15:04:01 +0000220static inline void enable_irq(void)
221{
222 /*
223 * The compiler memory barrier will prevent the compiler from
224 * scheduling non-volatile memory access after the write to the
225 * register.
226 *
227 * This could happen if some initialization code issues non-volatile
228 * accesses to an area used by an interrupt handler, in the assumption
229 * that it is safe as the interrupts are disabled at the time it does
230 * that (according to program order). However, non-volatile accesses
231 * are not necessarily in program order relatively with volatile inline
232 * assembly statements (and volatile accesses).
233 */
234 COMPILER_BARRIER();
235 write_daifclr(DAIF_IRQ_BIT);
236 isb();
237}
238
239static inline void enable_fiq(void)
240{
241 COMPILER_BARRIER();
242 write_daifclr(DAIF_FIQ_BIT);
243 isb();
244}
245
246static inline void enable_serror(void)
247{
248 COMPILER_BARRIER();
249 write_daifclr(DAIF_ABT_BIT);
250 isb();
251}
252
253static inline void enable_debug_exceptions(void)
254{
255 COMPILER_BARRIER();
256 write_daifclr(DAIF_DBG_BIT);
257 isb();
258}
259
260static inline void disable_irq(void)
261{
262 COMPILER_BARRIER();
263 write_daifset(DAIF_IRQ_BIT);
264 isb();
265}
266
267static inline void disable_fiq(void)
268{
269 COMPILER_BARRIER();
270 write_daifset(DAIF_FIQ_BIT);
271 isb();
272}
273
274static inline void disable_serror(void)
275{
276 COMPILER_BARRIER();
277 write_daifset(DAIF_ABT_BIT);
278 isb();
279}
280
281static inline void disable_debug_exceptions(void)
282{
283 COMPILER_BARRIER();
284 write_daifset(DAIF_DBG_BIT);
285 isb();
286}
287
Antonio Nino Diaz13344de2018-11-23 13:54:41 +0000288#if !ERROR_DEPRECATED
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100289uint32_t get_afflvl_shift(uint32_t);
290uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100291
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100292void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
293 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
Antonio Nino Diaz13344de2018-11-23 13:54:41 +0000294#endif
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100295void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
296 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100297
298/*******************************************************************************
299 * System register accessor prototypes
300 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100301DEFINE_SYSREG_READ_FUNC(midr_el1)
302DEFINE_SYSREG_READ_FUNC(mpidr_el1)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000303DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100304
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100305DEFINE_SYSREG_RW_FUNCS(scr_el3)
306DEFINE_SYSREG_RW_FUNCS(hcr_el2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100307
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100308DEFINE_SYSREG_RW_FUNCS(vbar_el1)
309DEFINE_SYSREG_RW_FUNCS(vbar_el2)
310DEFINE_SYSREG_RW_FUNCS(vbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100311
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100312DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
313DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
314DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100315
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100316DEFINE_SYSREG_RW_FUNCS(actlr_el1)
317DEFINE_SYSREG_RW_FUNCS(actlr_el2)
318DEFINE_SYSREG_RW_FUNCS(actlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100319
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100320DEFINE_SYSREG_RW_FUNCS(esr_el1)
321DEFINE_SYSREG_RW_FUNCS(esr_el2)
322DEFINE_SYSREG_RW_FUNCS(esr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100323
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100324DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
325DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
326DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100327
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100328DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
329DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
330DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100331
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100332DEFINE_SYSREG_RW_FUNCS(far_el1)
333DEFINE_SYSREG_RW_FUNCS(far_el2)
334DEFINE_SYSREG_RW_FUNCS(far_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100335
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100336DEFINE_SYSREG_RW_FUNCS(mair_el1)
337DEFINE_SYSREG_RW_FUNCS(mair_el2)
338DEFINE_SYSREG_RW_FUNCS(mair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100339
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100340DEFINE_SYSREG_RW_FUNCS(amair_el1)
341DEFINE_SYSREG_RW_FUNCS(amair_el2)
342DEFINE_SYSREG_RW_FUNCS(amair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100343
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100344DEFINE_SYSREG_READ_FUNC(rvbar_el1)
345DEFINE_SYSREG_READ_FUNC(rvbar_el2)
346DEFINE_SYSREG_READ_FUNC(rvbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100347
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100348DEFINE_SYSREG_RW_FUNCS(rmr_el1)
349DEFINE_SYSREG_RW_FUNCS(rmr_el2)
350DEFINE_SYSREG_RW_FUNCS(rmr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100351
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100352DEFINE_SYSREG_RW_FUNCS(tcr_el1)
353DEFINE_SYSREG_RW_FUNCS(tcr_el2)
354DEFINE_SYSREG_RW_FUNCS(tcr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100355
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100356DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
357DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
358DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100359
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100360DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100361
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000362DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
363
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100364DEFINE_SYSREG_RW_FUNCS(cptr_el2)
365DEFINE_SYSREG_RW_FUNCS(cptr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100366
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100367DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
368DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000369DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
370DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
371DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100372DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
373DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
374DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000375DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
376DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
377DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100378DEFINE_SYSREG_READ_FUNC(cntpct_el0)
379DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100380
Antonio Nino Diazdc4ed3d2018-11-23 13:54:00 +0000381#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
382 CNTP_CTL_ENABLE_MASK)
383#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
384 CNTP_CTL_IMASK_MASK)
385#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
386 CNTP_CTL_ISTATUS_MASK)
387
388#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
389#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
390
391#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
392#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
393
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100394DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100395
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100396DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
397
Andrew Thoelke4e126072014-06-04 21:10:52 +0100398DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
399DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
400
Soby Mathew26fb90e2015-01-06 21:36:55 +0000401DEFINE_SYSREG_READ_FUNC(isr_el1)
402
David Cunado5f55e282016-10-31 17:37:34 +0000403DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100404DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
David Cunadoc14b08e2016-11-25 00:21:59 +0000405DEFINE_SYSREG_RW_FUNCS(hstr_el2)
David Cunado4168f2f2017-10-02 17:41:39 +0100406DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
David Cunado5f55e282016-10-31 17:37:34 +0000407
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000408/* GICv3 System Registers */
409
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100410DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
411DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
412DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
413DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100414DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100415DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000416DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100417DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
418DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
419DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
420DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
421DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
422DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
423DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100424DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000425DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100426
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000427DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100428DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
429DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
430DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
431DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
432
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100433DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
434DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
435DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
436DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
437
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100438DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100439
David Cunadoce88eee2017-10-20 11:30:57 +0100440DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
441DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
442
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000443DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
444DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
445
446DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
447DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
448DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
449DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
450DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
451DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
452
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000453/* Armv8.2 Registers */
454DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
455
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000456/* Armv8.3 Pointer Authentication Registers */
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000457DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
458DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000459
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100460#define IS_IN_EL(x) \
461 (GET_EL(read_CurrentEl()) == MODE_EL##x)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100462
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100463#define IS_IN_EL1() IS_IN_EL(1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000464#define IS_IN_EL2() IS_IN_EL(2)
Douglas Raillard77414632018-08-21 12:54:45 +0100465#define IS_IN_EL3() IS_IN_EL(3)
466
467static inline unsigned int get_current_el(void)
468{
469 return GET_EL(read_CurrentEl());
470}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100471
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000472/*
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000473 * Check if an EL is implemented from AA64PFR0 register fields.
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000474 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000475static inline uint64_t el_implemented(unsigned int el)
476{
477 if (el > 3U) {
478 return EL_IMPL_NONE;
479 } else {
480 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
481
482 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
483 }
484}
485
486#if !ERROR_DEPRECATED
487#define EL_IMPLEMENTED(_el) el_implemented(_el)
488#endif
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000489
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100490/* Previously defined accesor functions with incomplete register names */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100491
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100492#define read_current_el() read_CurrentEl()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100493
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100494#define dsb() dsbsy()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100495
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100496#define read_midr() read_midr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100497
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100498#define read_mpidr() read_mpidr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100499
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100500#define read_scr() read_scr_el3()
501#define write_scr(_v) write_scr_el3(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100502
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100503#define read_hcr() read_hcr_el2()
504#define write_hcr(_v) write_hcr_el2(_v)
Sandrine Bailleux25232af2014-05-09 11:23:11 +0100505
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100506#define read_cpacr() read_cpacr_el1()
507#define write_cpacr(_v) write_cpacr_el1(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100508
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000509#endif /* ARCH_HELPERS_H */