blob: f178f1af2228044eb15385c925693da84bd5ab17 [file] [log] [blame]
Soby Mathew802f8652014-08-14 16:19:29 +01001#
John Tsichritzis56369c12019-02-19 13:49:06 +00002# Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
Soby Mathew802f8652014-08-14 16:19:29 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Soby Mathew802f8652014-08-14 16:19:29 +01005#
6
Soby Mathew937488b2014-09-22 14:13:34 +01007# Cortex A57 specific optimisation to skip L1 cache flush when
8# cluster is powered down.
9SKIP_A57_L1_FLUSH_PWR_DWN ?=0
10
Sandrine Bailleuxd4817592016-01-13 14:57:38 +000011# Flag to disable the cache non-temporal hint.
12# It is enabled by default.
13A53_DISABLE_NON_TEMPORAL_HINT ?=1
14
15# Flag to disable the cache non-temporal hint.
16# It is enabled by default.
17A57_DISABLE_NON_TEMPORAL_HINT ?=1
18
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000019WORKAROUND_CVE_2017_5715 ?=1
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010020WORKAROUND_CVE_2018_3639 ?=1
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010021DYNAMIC_WORKAROUND_CVE_2018_3639 ?=0
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000022
Soby Mathew937488b2014-09-22 14:13:34 +010023# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
24$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
25$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
26
Sandrine Bailleuxd4817592016-01-13 14:57:38 +000027# Process A53_DISABLE_NON_TEMPORAL_HINT flag
28$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT))
29$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT))
30
31# Process A57_DISABLE_NON_TEMPORAL_HINT flag
32$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT))
33$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT))
34
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000035# Process WORKAROUND_CVE_2017_5715 flag
36$(eval $(call assert_boolean,WORKAROUND_CVE_2017_5715))
37$(eval $(call add_define,WORKAROUND_CVE_2017_5715))
Soby Mathew937488b2014-09-22 14:13:34 +010038
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010039# Process WORKAROUND_CVE_2018_3639 flag
40$(eval $(call assert_boolean,WORKAROUND_CVE_2018_3639))
41$(eval $(call add_define,WORKAROUND_CVE_2018_3639))
42
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010043$(eval $(call assert_boolean,DYNAMIC_WORKAROUND_CVE_2018_3639))
44$(eval $(call add_define,DYNAMIC_WORKAROUND_CVE_2018_3639))
45
46ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
47 ifeq (${WORKAROUND_CVE_2018_3639},0)
48 $(error "Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1")
49 endif
50endif
51
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010052# CPU Errata Build flags.
53# These should be enabled by the platform if the erratum workaround needs to be
54# applied.
Soby Mathew802f8652014-08-14 16:19:29 +010055
Ambroise Vincentd4a51eb2019-03-04 16:56:26 +000056# Flag to apply erratum 816470 workaround during power down. This erratum
57# applies only to revision >= r3p0 of the Cortex A15 cpu.
58ERRATA_A15_816470 ?=0
59
Ambroise Vincent68b38122019-03-05 09:54:21 +000060# Flag to apply erratum 827671 workaround during reset. This erratum applies
61# only to revision >= r3p0 of the Cortex A15 cpu.
62ERRATA_A15_827671 ?=0
63
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +000064# Flag to apply erratum 819472 workaround during reset. This erratum applies
65# only to revision <= r0p1 of the Cortex A53 cpu.
66ERRATA_A53_819472 ?=0
67
68# Flag to apply erratum 824069 workaround during reset. This erratum applies
69# only to revision <= r0p2 of the Cortex A53 cpu.
70ERRATA_A53_824069 ?=0
71
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010072# Flag to apply erratum 826319 workaround during reset. This erratum applies
73# only to revision <= r0p2 of the Cortex A53 cpu.
developer4fceaca2015-07-29 20:55:31 +080074ERRATA_A53_826319 ?=0
75
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +000076# Flag to apply erratum 827319 workaround during reset. This erratum applies
77# only to revision <= r0p2 of the Cortex A53 cpu.
78ERRATA_A53_827319 ?=0
79
Douglas Raillardd56fb042017-06-19 15:38:02 +010080# Flag to apply erratum 835769 workaround at compile and link time. This
81# erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
82# workaround can lead the linker to create "*.stub" sections.
83ERRATA_A53_835769 ?=0
84
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010085# Flag to apply erratum 836870 workaround during reset. This erratum applies
86# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this
Douglas Raillardc847f662017-02-15 17:38:43 +000087# erratum workaround is enabled by default in hardware.
developer4fceaca2015-07-29 20:55:31 +080088ERRATA_A53_836870 ?=0
89
Douglas Raillardd56fb042017-06-19 15:38:02 +010090# Flag to apply erratum 843419 workaround at link time.
91# This erratum applies to revision <= r0p4 of the Cortex A53 cpu. Enabling this
92# workaround could lead the linker to emit "*.stub" sections which are 4kB
93# aligned.
94ERRATA_A53_843419 ?=0
95
Andre Przywara00eefd92016-10-06 16:54:53 +010096# Flag to apply errata 855873 during reset. This errata applies to all
97# revisions of the Cortex A53 CPU, but this firmware workaround only works
98# for revisions r0p3 and higher. Earlier revisions are taken care
99# of by the rich OS.
100ERRATA_A53_855873 ?=0
101
Ambroise Vincent7927fa02019-02-21 16:20:43 +0000102# Flag to apply erratum 768277 workaround during reset. This erratum applies
103# only to revision r0p0 of the Cortex A55 cpu.
104ERRATA_A55_768277 ?=0
105
Ambroise Vincent6f319602019-02-21 16:25:37 +0000106# Flag to apply erratum 778703 workaround during reset. This erratum applies
107# only to revision r0p0 of the Cortex A55 cpu.
108ERRATA_A55_778703 ?=0
109
Ambroise Vincent6a77f052019-02-21 16:27:34 +0000110# Flag to apply erratum 798797 workaround during reset. This erratum applies
111# only to revision r0p0 of the Cortex A55 cpu.
112ERRATA_A55_798797 ?=0
113
Ambroise Vincentdd961f72019-02-21 16:29:16 +0000114# Flag to apply erratum 846532 workaround during reset. This erratum applies
115# only to revision <= r0p1 of the Cortex A55 cpu.
116ERRATA_A55_846532 ?=0
117
Ambroise Vincenta1d64462019-02-21 16:29:50 +0000118# Flag to apply erratum 903758 workaround during reset. This erratum applies
119# only to revision <= r0p1 of the Cortex A55 cpu.
120ERRATA_A55_903758 ?=0
121
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +0100122# Flag to apply erratum 806969 workaround during reset. This erratum applies
123# only to revision r0p0 of the Cortex A57 cpu.
Soby Mathew802f8652014-08-14 16:19:29 +0100124ERRATA_A57_806969 ?=0
125
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000126# Flag to apply erratum 813419 workaround during reset. This erratum applies
127# only to revision r0p0 of the Cortex A57 cpu.
128ERRATA_A57_813419 ?=0
129
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +0100130# Flag to apply erratum 813420 workaround during reset. This erratum applies
131# only to revision r0p0 of the Cortex A57 cpu.
Soby Mathew802f8652014-08-14 16:19:29 +0100132ERRATA_A57_813420 ?=0
133
Ambroise Vincent1b0db762019-02-21 16:35:07 +0000134# Flag to apply erratum 814670 workaround during reset. This erratum applies
135# only to revision r0p0 of the Cortex A57 cpu.
136ERRATA_A57_814670 ?=0
137
Ambroise Vincentaa2c0292019-02-21 16:35:49 +0000138# Flag to apply erratum 817169 workaround during power down. This erratum
139# applies only to revision <= r0p1 of the Cortex A57 cpu.
140ERRATA_A57_817169 ?=0
141
Sandrine Bailleuxa7e0c532016-04-14 13:32:31 +0100142# Flag to apply erratum 826974 workaround during reset. This erratum applies
143# only to revision <= r1p1 of the Cortex A57 cpu.
144ERRATA_A57_826974 ?=0
145
Sandrine Bailleuxadcbd552016-04-14 14:24:13 +0100146# Flag to apply erratum 826977 workaround during reset. This erratum applies
147# only to revision <= r1p1 of the Cortex A57 cpu.
148ERRATA_A57_826977 ?=0
149
Sandrine Bailleuxc11116f2016-04-14 14:04:48 +0100150# Flag to apply erratum 828024 workaround during reset. This erratum applies
151# only to revision <= r1p1 of the Cortex A57 cpu.
152ERRATA_A57_828024 ?=0
153
Sandrine Bailleux48cbe852016-04-14 14:18:07 +0100154# Flag to apply erratum 829520 workaround during reset. This erratum applies
155# only to revision <= r1p2 of the Cortex A57 cpu.
156ERRATA_A57_829520 ?=0
157
Sandrine Bailleux143ef1a2016-04-21 11:10:52 +0100158# Flag to apply erratum 833471 workaround during reset. This erratum applies
159# only to revision <= r1p2 of the Cortex A57 cpu.
160ERRATA_A57_833471 ?=0
161
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100162# Flag to apply erratum 855972 workaround during reset. This erratum applies
163# only to revision <= r1p3 of the Cortex A57 cpu.
164ERRATA_A57_859972 ?=0
165
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100166# Flag to apply erratum 855971 workaround during reset. This erratum applies
167# only to revision <= r0p3 of the Cortex A72 cpu.
168ERRATA_A72_859971 ?=0
169
Louis Mayencourtd69722c2019-02-27 14:24:16 +0000170# Flag to apply erratum 852427 workaround during reset. This erratum applies
171# only to revision r0p0 of the Cortex A73 cpu.
172ERRATA_A73_852427 ?=0
173
Louis Mayencourt4405de62019-02-21 16:38:16 +0000174# Flag to apply erratum 855423 workaround during reset. This erratum applies
175# only to revision <= r0p1 of the Cortex A73 cpu.
176ERRATA_A73_855423 ?=0
177
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000178# Flag to apply erratum 764081 workaround during reset. This erratum applies
179# only to revision <= r0p0 of the Cortex A75 cpu.
180ERRATA_A75_764081 ?=0
181
Louis Mayencourt8d868702019-02-25 14:57:57 +0000182# Flag to apply erratum 790748 workaround during reset. This erratum applies
183# only to revision <= r0p0 of the Cortex A75 cpu.
184ERRATA_A75_790748 ?=0
185
Louis Mayencourt59fa2182019-02-25 15:17:44 +0000186# Flag to apply erratum 1073348 workaround during reset. This erratum applies
187# only to revision <= r1p0 of the Cortex A76 cpu.
188ERRATA_A76_1073348 ?=0
189
Louis Mayencourt09924472019-02-21 17:35:07 +0000190# Flag to apply erratum 1130799 workaround during reset. This erratum applies
191# only to revision <= r2p0 of the Cortex A76 cpu.
192ERRATA_A76_1130799 ?=0
193
Louis Mayencourtadda9d42019-02-25 11:37:38 +0000194# Flag to apply erratum 1220197 workaround during reset. This erratum applies
195# only to revision <= r2p0 of the Cortex A76 cpu.
196ERRATA_A76_1220197 ?=0
197
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100198# Flag to apply T32 CLREX workaround during reset. This erratum applies
John Tsichritzis56369c12019-02-19 13:49:06 +0000199# only to r0p0 and r1p0 of the Neoverse N1 cpu.
200ERRATA_N1_1043202 ?=1
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100201
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100202# Flag to apply DSU erratum 936184. This erratum applies to DSUs containing
203# the ACP interface and revision < r2p0. Applying the workaround results in
204# higher DSU power consumption on idle.
205ERRATA_DSU_936184 ?=0
206
Ambroise Vincentd4a51eb2019-03-04 16:56:26 +0000207# Process ERRATA_A15_816470 flag
208$(eval $(call assert_boolean,ERRATA_A15_816470))
209$(eval $(call add_define,ERRATA_A15_816470))
210
Ambroise Vincent68b38122019-03-05 09:54:21 +0000211# Process ERRATA_A15_827671 flag
212$(eval $(call assert_boolean,ERRATA_A15_827671))
213$(eval $(call add_define,ERRATA_A15_827671))
214
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000215# Process ERRATA_A53_819472 flag
216$(eval $(call assert_boolean,ERRATA_A53_819472))
217$(eval $(call add_define,ERRATA_A53_819472))
218
219# Process ERRATA_A53_824069 flag
220$(eval $(call assert_boolean,ERRATA_A53_824069))
221$(eval $(call add_define,ERRATA_A53_824069))
222
developer4fceaca2015-07-29 20:55:31 +0800223# Process ERRATA_A53_826319 flag
224$(eval $(call assert_boolean,ERRATA_A53_826319))
225$(eval $(call add_define,ERRATA_A53_826319))
226
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000227# Process ERRATA_A53_827319 flag
228$(eval $(call assert_boolean,ERRATA_A53_827319))
229$(eval $(call add_define,ERRATA_A53_827319))
230
Douglas Raillardd56fb042017-06-19 15:38:02 +0100231# Process ERRATA_A53_835769 flag
232$(eval $(call assert_boolean,ERRATA_A53_835769))
233$(eval $(call add_define,ERRATA_A53_835769))
234
developer4fceaca2015-07-29 20:55:31 +0800235# Process ERRATA_A53_836870 flag
236$(eval $(call assert_boolean,ERRATA_A53_836870))
237$(eval $(call add_define,ERRATA_A53_836870))
238
Douglas Raillardd56fb042017-06-19 15:38:02 +0100239# Process ERRATA_A53_843419 flag
240$(eval $(call assert_boolean,ERRATA_A53_843419))
241$(eval $(call add_define,ERRATA_A53_843419))
242
Andre Przywara00eefd92016-10-06 16:54:53 +0100243# Process ERRATA_A53_855873 flag
244$(eval $(call assert_boolean,ERRATA_A53_855873))
245$(eval $(call add_define,ERRATA_A53_855873))
246
Ambroise Vincent7927fa02019-02-21 16:20:43 +0000247# Process ERRATA_A55_768277 flag
248$(eval $(call assert_boolean,ERRATA_A55_768277))
249$(eval $(call add_define,ERRATA_A55_768277))
250
Ambroise Vincent6f319602019-02-21 16:25:37 +0000251# Process ERRATA_A55_778703 flag
252$(eval $(call assert_boolean,ERRATA_A55_778703))
253$(eval $(call add_define,ERRATA_A55_778703))
254
Ambroise Vincent6a77f052019-02-21 16:27:34 +0000255# Process ERRATA_A55_798797 flag
256$(eval $(call assert_boolean,ERRATA_A55_798797))
257$(eval $(call add_define,ERRATA_A55_798797))
258
Ambroise Vincentdd961f72019-02-21 16:29:16 +0000259# Process ERRATA_A55_846532 flag
260$(eval $(call assert_boolean,ERRATA_A55_846532))
261$(eval $(call add_define,ERRATA_A55_846532))
262
Ambroise Vincenta1d64462019-02-21 16:29:50 +0000263# Process ERRATA_A55_903758 flag
264$(eval $(call assert_boolean,ERRATA_A55_903758))
265$(eval $(call add_define,ERRATA_A55_903758))
266
Soby Mathew802f8652014-08-14 16:19:29 +0100267# Process ERRATA_A57_806969 flag
268$(eval $(call assert_boolean,ERRATA_A57_806969))
269$(eval $(call add_define,ERRATA_A57_806969))
270
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000271# Process ERRATA_A57_813419 flag
272$(eval $(call assert_boolean,ERRATA_A57_813419))
273$(eval $(call add_define,ERRATA_A57_813419))
274
Soby Mathew802f8652014-08-14 16:19:29 +0100275# Process ERRATA_A57_813420 flag
276$(eval $(call assert_boolean,ERRATA_A57_813420))
277$(eval $(call add_define,ERRATA_A57_813420))
Sandrine Bailleuxa7e0c532016-04-14 13:32:31 +0100278
Ambroise Vincent1b0db762019-02-21 16:35:07 +0000279# Process ERRATA_A57_814670 flag
280$(eval $(call assert_boolean,ERRATA_A57_814670))
281$(eval $(call add_define,ERRATA_A57_814670))
282
Ambroise Vincentaa2c0292019-02-21 16:35:49 +0000283# Process ERRATA_A57_817169 flag
284$(eval $(call assert_boolean,ERRATA_A57_817169))
285$(eval $(call add_define,ERRATA_A57_817169))
286
Sandrine Bailleuxa7e0c532016-04-14 13:32:31 +0100287# Process ERRATA_A57_826974 flag
288$(eval $(call assert_boolean,ERRATA_A57_826974))
289$(eval $(call add_define,ERRATA_A57_826974))
Sandrine Bailleuxc11116f2016-04-14 14:04:48 +0100290
Sandrine Bailleuxadcbd552016-04-14 14:24:13 +0100291# Process ERRATA_A57_826977 flag
292$(eval $(call assert_boolean,ERRATA_A57_826977))
293$(eval $(call add_define,ERRATA_A57_826977))
294
Sandrine Bailleuxc11116f2016-04-14 14:04:48 +0100295# Process ERRATA_A57_828024 flag
296$(eval $(call assert_boolean,ERRATA_A57_828024))
297$(eval $(call add_define,ERRATA_A57_828024))
Sandrine Bailleux48cbe852016-04-14 14:18:07 +0100298
299# Process ERRATA_A57_829520 flag
300$(eval $(call assert_boolean,ERRATA_A57_829520))
301$(eval $(call add_define,ERRATA_A57_829520))
Sandrine Bailleux143ef1a2016-04-21 11:10:52 +0100302
303# Process ERRATA_A57_833471 flag
304$(eval $(call assert_boolean,ERRATA_A57_833471))
305$(eval $(call add_define,ERRATA_A57_833471))
Douglas Raillardd56fb042017-06-19 15:38:02 +0100306
Eleanor Bonnici0c9bd272017-08-02 16:35:04 +0100307# Process ERRATA_A57_859972 flag
308$(eval $(call assert_boolean,ERRATA_A57_859972))
309$(eval $(call add_define,ERRATA_A57_859972))
310
Eleanor Bonnicic3b4ca12017-08-02 18:33:41 +0100311# Process ERRATA_A72_859971 flag
312$(eval $(call assert_boolean,ERRATA_A72_859971))
313$(eval $(call add_define,ERRATA_A72_859971))
314
Louis Mayencourtd69722c2019-02-27 14:24:16 +0000315# Process ERRATA_A73_852427 flag
316$(eval $(call assert_boolean,ERRATA_A73_852427))
317$(eval $(call add_define,ERRATA_A73_852427))
318
Louis Mayencourt4405de62019-02-21 16:38:16 +0000319# Process ERRATA_A73_855423 flag
320$(eval $(call assert_boolean,ERRATA_A73_855423))
321$(eval $(call add_define,ERRATA_A73_855423))
322
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000323# Process ERRATA_A75_764081 flag
324$(eval $(call assert_boolean,ERRATA_A75_764081))
325$(eval $(call add_define,ERRATA_A75_764081))
326
Louis Mayencourt8d868702019-02-25 14:57:57 +0000327# Process ERRATA_A75_790748 flag
328$(eval $(call assert_boolean,ERRATA_A75_790748))
329$(eval $(call add_define,ERRATA_A75_790748))
330
Louis Mayencourt59fa2182019-02-25 15:17:44 +0000331# Process ERRATA_A76_1073348 flag
332$(eval $(call assert_boolean,ERRATA_A76_1073348))
333$(eval $(call add_define,ERRATA_A76_1073348))
334
Louis Mayencourt09924472019-02-21 17:35:07 +0000335# Process ERRATA_A76_1130799 flag
336$(eval $(call assert_boolean,ERRATA_A76_1130799))
337$(eval $(call add_define,ERRATA_A76_1130799))
338
Louis Mayencourtadda9d42019-02-25 11:37:38 +0000339# Process ERRATA_A76_1220197 flag
340$(eval $(call assert_boolean,ERRATA_A76_1220197))
341$(eval $(call add_define,ERRATA_A76_1220197))
342
John Tsichritzis56369c12019-02-19 13:49:06 +0000343# Process ERRATA_N1_1043202 flag
344$(eval $(call assert_boolean,ERRATA_N1_1043202))
345$(eval $(call add_define,ERRATA_N1_1043202))
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +0100346
John Tsichritzis4daa1de2018-07-23 09:11:59 +0100347# Process ERRATA_DSU_936184 flag
348$(eval $(call assert_boolean,ERRATA_DSU_936184))
349$(eval $(call add_define,ERRATA_DSU_936184))
350
Douglas Raillardd56fb042017-06-19 15:38:02 +0100351# Errata build flags
352ifneq (${ERRATA_A53_843419},0)
Douglas Raillardd0c82732017-06-22 14:44:48 +0100353TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419
Douglas Raillardd56fb042017-06-19 15:38:02 +0100354endif
355
356ifneq (${ERRATA_A53_835769},0)
357TF_CFLAGS_aarch64 += -mfix-cortex-a53-835769
Douglas Raillardd0c82732017-06-22 14:44:48 +0100358TF_LDFLAGS_aarch64 += --fix-cortex-a53-835769
Douglas Raillardd56fb042017-06-19 15:38:02 +0100359endif