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Soby Mathew802f8652014-08-14 16:19:29 +01001#
Sandrine Bailleuxd4817592016-01-13 14:57:38 +00002# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
Soby Mathew802f8652014-08-14 16:19:29 +01003#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are met:
6#
7# Redistributions of source code must retain the above copyright notice, this
8# list of conditions and the following disclaimer.
9#
10# Redistributions in binary form must reproduce the above copyright notice,
11# this list of conditions and the following disclaimer in the documentation
12# and/or other materials provided with the distribution.
13#
14# Neither the name of ARM nor the names of its contributors may be used
15# to endorse or promote products derived from this software without specific
16# prior written permission.
17#
18# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28# POSSIBILITY OF SUCH DAMAGE.
29#
30
Soby Mathew937488b2014-09-22 14:13:34 +010031# Cortex A57 specific optimisation to skip L1 cache flush when
32# cluster is powered down.
33SKIP_A57_L1_FLUSH_PWR_DWN ?=0
34
Sandrine Bailleuxd4817592016-01-13 14:57:38 +000035# Flag to disable the cache non-temporal hint.
36# It is enabled by default.
37A53_DISABLE_NON_TEMPORAL_HINT ?=1
38
39# Flag to disable the cache non-temporal hint.
40# It is enabled by default.
41A57_DISABLE_NON_TEMPORAL_HINT ?=1
42
Soby Mathew937488b2014-09-22 14:13:34 +010043# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
44$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
45$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
46
Sandrine Bailleuxd4817592016-01-13 14:57:38 +000047# Process A53_DISABLE_NON_TEMPORAL_HINT flag
48$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT))
49$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT))
50
51# Process A57_DISABLE_NON_TEMPORAL_HINT flag
52$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT))
53$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT))
54
Soby Mathew937488b2014-09-22 14:13:34 +010055
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010056# CPU Errata Build flags.
57# These should be enabled by the platform if the erratum workaround needs to be
58# applied.
Soby Mathew802f8652014-08-14 16:19:29 +010059
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010060# Flag to apply erratum 826319 workaround during reset. This erratum applies
61# only to revision <= r0p2 of the Cortex A53 cpu.
developer4fceaca2015-07-29 20:55:31 +080062ERRATA_A53_826319 ?=0
63
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010064# Flag to apply erratum 836870 workaround during reset. This erratum applies
65# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this
Douglas Raillardc847f662017-02-15 17:38:43 +000066# erratum workaround is enabled by default in hardware.
developer4fceaca2015-07-29 20:55:31 +080067ERRATA_A53_836870 ?=0
68
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010069# Flag to apply erratum 806969 workaround during reset. This erratum applies
70# only to revision r0p0 of the Cortex A57 cpu.
Soby Mathew802f8652014-08-14 16:19:29 +010071ERRATA_A57_806969 ?=0
72
Sandrine Bailleuxafa8a782016-04-14 12:59:42 +010073# Flag to apply erratum 813420 workaround during reset. This erratum applies
74# only to revision r0p0 of the Cortex A57 cpu.
Soby Mathew802f8652014-08-14 16:19:29 +010075ERRATA_A57_813420 ?=0
76
Sandrine Bailleuxa7e0c532016-04-14 13:32:31 +010077# Flag to apply erratum 826974 workaround during reset. This erratum applies
78# only to revision <= r1p1 of the Cortex A57 cpu.
79ERRATA_A57_826974 ?=0
80
Sandrine Bailleuxadcbd552016-04-14 14:24:13 +010081# Flag to apply erratum 826977 workaround during reset. This erratum applies
82# only to revision <= r1p1 of the Cortex A57 cpu.
83ERRATA_A57_826977 ?=0
84
Sandrine Bailleuxc11116f2016-04-14 14:04:48 +010085# Flag to apply erratum 828024 workaround during reset. This erratum applies
86# only to revision <= r1p1 of the Cortex A57 cpu.
87ERRATA_A57_828024 ?=0
88
Sandrine Bailleux48cbe852016-04-14 14:18:07 +010089# Flag to apply erratum 829520 workaround during reset. This erratum applies
90# only to revision <= r1p2 of the Cortex A57 cpu.
91ERRATA_A57_829520 ?=0
92
Sandrine Bailleux143ef1a2016-04-21 11:10:52 +010093# Flag to apply erratum 833471 workaround during reset. This erratum applies
94# only to revision <= r1p2 of the Cortex A57 cpu.
95ERRATA_A57_833471 ?=0
96
developer4fceaca2015-07-29 20:55:31 +080097# Process ERRATA_A53_826319 flag
98$(eval $(call assert_boolean,ERRATA_A53_826319))
99$(eval $(call add_define,ERRATA_A53_826319))
100
101# Process ERRATA_A53_836870 flag
102$(eval $(call assert_boolean,ERRATA_A53_836870))
103$(eval $(call add_define,ERRATA_A53_836870))
104
Soby Mathew802f8652014-08-14 16:19:29 +0100105# Process ERRATA_A57_806969 flag
106$(eval $(call assert_boolean,ERRATA_A57_806969))
107$(eval $(call add_define,ERRATA_A57_806969))
108
109# Process ERRATA_A57_813420 flag
110$(eval $(call assert_boolean,ERRATA_A57_813420))
111$(eval $(call add_define,ERRATA_A57_813420))
Sandrine Bailleuxa7e0c532016-04-14 13:32:31 +0100112
113# Process ERRATA_A57_826974 flag
114$(eval $(call assert_boolean,ERRATA_A57_826974))
115$(eval $(call add_define,ERRATA_A57_826974))
Sandrine Bailleuxc11116f2016-04-14 14:04:48 +0100116
Sandrine Bailleuxadcbd552016-04-14 14:24:13 +0100117# Process ERRATA_A57_826977 flag
118$(eval $(call assert_boolean,ERRATA_A57_826977))
119$(eval $(call add_define,ERRATA_A57_826977))
120
Sandrine Bailleuxc11116f2016-04-14 14:04:48 +0100121# Process ERRATA_A57_828024 flag
122$(eval $(call assert_boolean,ERRATA_A57_828024))
123$(eval $(call add_define,ERRATA_A57_828024))
Sandrine Bailleux48cbe852016-04-14 14:18:07 +0100124
125# Process ERRATA_A57_829520 flag
126$(eval $(call assert_boolean,ERRATA_A57_829520))
127$(eval $(call add_define,ERRATA_A57_829520))
Sandrine Bailleux143ef1a2016-04-21 11:10:52 +0100128
129# Process ERRATA_A57_833471 flag
130$(eval $(call assert_boolean,ERRATA_A57_833471))
131$(eval $(call add_define,ERRATA_A57_833471))