blob: 1c5512e9c4f675879d3d851cf69db141b834802c [file] [log] [blame]
Soby Mathew802f8652014-08-14 16:19:29 +01001#
2# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are met:
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8# list of conditions and the following disclaimer.
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10# Redistributions in binary form must reproduce the above copyright notice,
11# this list of conditions and the following disclaimer in the documentation
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14# Neither the name of ARM nor the names of its contributors may be used
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16# prior written permission.
17#
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27# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28# POSSIBILITY OF SUCH DAMAGE.
29#
30
Soby Mathew937488b2014-09-22 14:13:34 +010031# Cortex A57 specific optimisation to skip L1 cache flush when
32# cluster is powered down.
33SKIP_A57_L1_FLUSH_PWR_DWN ?=0
34
35# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
36$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
37$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
38
39
Soby Mathew802f8652014-08-14 16:19:29 +010040# CPU Errata Build flags. These should be enabled by the
41# platform if the errata needs to be applied.
42
43# Flag to apply errata 806969 during reset. This errata applies only to
44# revision r0p0 of the Cortex A57 cpu.
45ERRATA_A57_806969 ?=0
46
47# Flag to apply errata 813420 during reset. This errata applies only to
48# revision r0p0 of the Cortex A57 cpu.
49ERRATA_A57_813420 ?=0
50
51# Process ERRATA_A57_806969 flag
52$(eval $(call assert_boolean,ERRATA_A57_806969))
53$(eval $(call add_define,ERRATA_A57_806969))
54
55# Process ERRATA_A57_813420 flag
56$(eval $(call assert_boolean,ERRATA_A57_813420))
57$(eval $(call add_define,ERRATA_A57_813420))