blob: 72865a5176f4b0ec8514ca1acf2f96968935d98c [file] [log] [blame]
Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Porting Guide
2=============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Douglas Raillardd7c21b72017-06-28 15:23:03 +01004Introduction
5------------
6
Dan Handley610e7e12018-03-01 18:44:00 +00007Porting Trusted Firmware-A (TF-A) to a new platform involves making some
Douglas Raillardd7c21b72017-06-28 15:23:03 +01008mandatory and optional modifications for both the cold and warm boot paths.
9Modifications consist of:
10
11- Implementing a platform-specific function or variable,
12- Setting up the execution context in a certain way, or
13- Defining certain constants (for example #defines).
14
15The platform-specific functions and variables are declared in
16`include/plat/common/platform.h`_. The firmware provides a default implementation
17of variables and functions to fulfill the optional requirements. These
18implementations are all weakly defined; they are provided to ease the porting
19effort. Each platform port can override them with its own implementation if the
20default implementation is inadequate.
21
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022Some modifications are common to all Boot Loader (BL) stages. Section 2
23discusses these in detail. The subsequent sections discuss the remaining
24modifications for each BL stage in detail.
25
Dan Handley610e7e12018-03-01 18:44:00 +000026This document should be read in conjunction with the TF-A `User Guide`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010027
Soby Mathew02bdbb92018-09-26 11:17:23 +010028Please refer to the `Platform compatibility policy`_ for the policy regarding
29compatibility and deprecation of these porting interfaces.
30
Antonio Nino Diaz645feb42019-02-13 14:07:38 +000031Only Arm development platforms (such as FVP and Juno) may use the
32functions/definitions in ``include/plat/arm/common/`` and the corresponding
33source files in ``plat/arm/common/``. This is done so that there are no
34dependencies between platforms maintained by different people/companies. If you
35want to use any of the functionality present in ``plat/arm`` files, please
36create a pull request that moves the code to ``plat/common`` so that it can be
37discussed.
38
Douglas Raillardd7c21b72017-06-28 15:23:03 +010039Common modifications
40--------------------
41
42This section covers the modifications that should be made by the platform for
43each BL stage to correctly port the firmware stack. They are categorized as
44either mandatory or optional.
45
46Common mandatory modifications
47------------------------------
48
49A platform port must enable the Memory Management Unit (MMU) as well as the
50instruction and data caches for each BL stage. Setting up the translation
51tables is the responsibility of the platform port because memory maps differ
52across platforms. A memory translation library (see ``lib/xlat_tables/``) is
Sandrine Bailleux1861b7a2017-07-20 16:11:01 +010053provided to help in this setup.
54
55Note that although this library supports non-identity mappings, this is intended
56only for re-mapping peripheral physical addresses and allows platforms with high
57I/O addresses to reduce their virtual address space. All other addresses
58corresponding to code and data must currently use an identity mapping.
59
Dan Handley610e7e12018-03-01 18:44:00 +000060Also, the only translation granule size supported in TF-A is 4KB, as various
61parts of the code assume that is the case. It is not possible to switch to
6216 KB or 64 KB granule sizes at the moment.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010063
Dan Handley610e7e12018-03-01 18:44:00 +000064In Arm standard platforms, each BL stage configures the MMU in the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010065platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
66an identity mapping for all addresses.
67
68If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
69block of identity mapped secure memory with Device-nGnRE attributes aligned to
70page boundary (4K) for each BL stage. All sections which allocate coherent
71memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
72section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
73possible for the firmware to place variables in it using the following C code
74directive:
75
76::
77
78 __section("bakery_lock")
79
80Or alternatively the following assembler code directive:
81
82::
83
84 .section bakery_lock
85
86The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
87used to allocate any data structures that are accessed both when a CPU is
88executing with its MMU and caches enabled, and when it's running with its MMU
89and caches disabled. Examples are given below.
90
91The following variables, functions and constants must be defined by the platform
92for the firmware to work correctly.
93
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +010094File : platform_def.h [mandatory]
95~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +010096
97Each platform must ensure that a header file of this name is in the system
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +000098include path with the following constants defined. This will require updating
99the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100100
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100101Platform ports may optionally use the file `include/plat/common/common_def.h`_,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100102which provides typical values for some of the constants below. These values are
103likely to be suitable for all platform ports.
104
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100105- **#define : PLATFORM_LINKER_FORMAT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100106
107 Defines the linker format used by the platform, for example
108 ``elf64-littleaarch64``.
109
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100110- **#define : PLATFORM_LINKER_ARCH**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100111
112 Defines the processor architecture for the linker by the platform, for
113 example ``aarch64``.
114
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100115- **#define : PLATFORM_STACK_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100116
117 Defines the normal stack memory available to each CPU. This constant is used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100118 by `plat/common/aarch64/platform_mp_stack.S`_ and
119 `plat/common/aarch64/platform_up_stack.S`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100120
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100121- **define : CACHE_WRITEBACK_GRANULE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100122
123 Defines the size in bits of the largest cache line across all the cache
124 levels in the platform.
125
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100126- **#define : FIRMWARE_WELCOME_STR**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100127
128 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
129 function.
130
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100131- **#define : PLATFORM_CORE_COUNT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100132
133 Defines the total number of CPUs implemented by the platform across all
134 clusters in the system.
135
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100136- **#define : PLAT_NUM_PWR_DOMAINS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100137
138 Defines the total number of nodes in the power domain topology
139 tree at all the power domain levels used by the platform.
140 This macro is used by the PSCI implementation to allocate
141 data structures to represent power domain topology.
142
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100143- **#define : PLAT_MAX_PWR_LVL**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100144
145 Defines the maximum power domain level that the power management operations
146 should apply to. More often, but not always, the power domain level
147 corresponds to affinity level. This macro allows the PSCI implementation
148 to know the highest power domain level that it should consider for power
149 management operations in the system that the platform implements. For
150 example, the Base AEM FVP implements two clusters with a configurable
151 number of CPUs and it reports the maximum power domain level as 1.
152
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100153- **#define : PLAT_MAX_OFF_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100154
155 Defines the local power state corresponding to the deepest power down
156 possible at every power domain level in the platform. The local power
157 states for each level may be sparsely allocated between 0 and this value
158 with 0 being reserved for the RUN state. The PSCI implementation uses this
159 value to initialize the local power states of the power domain nodes and
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100160 to specify the requested power state for a PSCI_CPU_OFF call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100161
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100162- **#define : PLAT_MAX_RET_STATE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100163
164 Defines the local power state corresponding to the deepest retention state
165 possible at every power domain level in the platform. This macro should be
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100166 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100167 PSCI implementation to distinguish between retention and power down local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100168 power states within PSCI_CPU_SUSPEND call.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100170- **#define : PLAT_MAX_PWR_LVL_STATES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100171
172 Defines the maximum number of local power states per power domain level
173 that the platform supports. The default value of this macro is 2 since
174 most platforms just support a maximum of two local power states at each
175 power domain level (power-down and retention). If the platform needs to
176 account for more local power states, then it must redefine this macro.
177
178 Currently, this macro is used by the Generic PSCI implementation to size
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100179 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100181- **#define : BL1_RO_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100182
183 Defines the base address in secure ROM where BL1 originally lives. Must be
184 aligned on a page-size boundary.
185
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100186- **#define : BL1_RO_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100187
188 Defines the maximum address in secure ROM that BL1's actual content (i.e.
189 excluding any data section allocated at runtime) can occupy.
190
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100191- **#define : BL1_RW_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100192
193 Defines the base address in secure RAM where BL1's read-write data will live
194 at runtime. Must be aligned on a page-size boundary.
195
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100196- **#define : BL1_RW_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100197
198 Defines the maximum address in secure RAM that BL1's read-write data can
199 occupy at runtime.
200
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100201- **#define : BL2_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100202
203 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000204 Must be aligned on a page-size boundary. This constant is not applicable
205 when BL2_IN_XIP_MEM is set to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100207- **#define : BL2_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100208
209 Defines the maximum address in secure RAM that the BL2 image can occupy.
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000210 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
211
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100212- **#define : BL2_RO_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000213
214 Defines the base address in secure XIP memory where BL2 RO section originally
215 lives. Must be aligned on a page-size boundary. This constant is only needed
216 when BL2_IN_XIP_MEM is set to '1'.
217
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100218- **#define : BL2_RO_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000219
220 Defines the maximum address in secure XIP memory that BL2's actual content
221 (i.e. excluding any data section allocated at runtime) can occupy. This
222 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
223
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100224- **#define : BL2_RW_BASE**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000225
226 Defines the base address in secure RAM where BL2's read-write data will live
227 at runtime. Must be aligned on a page-size boundary. This constant is only
228 needed when BL2_IN_XIP_MEM is set to '1'.
229
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100230- **#define : BL2_RW_LIMIT**
Jiafei Pan43a7bf42018-03-21 07:20:09 +0000231
232 Defines the maximum address in secure RAM that BL2's read-write data can
233 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
234 to '1'.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100235
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100236- **#define : BL31_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100237
238 Defines the base address in secure RAM where BL2 loads the BL31 binary
239 image. Must be aligned on a page-size boundary.
240
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100241- **#define : BL31_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100242
243 Defines the maximum address in secure RAM that the BL31 image can occupy.
244
245For every image, the platform must define individual identifiers that will be
246used by BL1 or BL2 to load the corresponding image into memory from non-volatile
247storage. For the sake of performance, integer numbers will be used as
248identifiers. The platform will use those identifiers to return the relevant
249information about the image to be loaded (file handler, load address,
250authentication information, etc.). The following image identifiers are
251mandatory:
252
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100253- **#define : BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100254
255 BL2 image identifier, used by BL1 to load BL2.
256
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100257- **#define : BL31_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100258
259 BL31 image identifier, used by BL2 to load BL31.
260
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100261- **#define : BL33_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100262
263 BL33 image identifier, used by BL2 to load BL33.
264
265If Trusted Board Boot is enabled, the following certificate identifiers must
266also be defined:
267
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100268- **#define : TRUSTED_BOOT_FW_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100269
270 BL2 content certificate identifier, used by BL1 to load the BL2 content
271 certificate.
272
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100273- **#define : TRUSTED_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100274
275 Trusted key certificate identifier, used by BL2 to load the trusted key
276 certificate.
277
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100278- **#define : SOC_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100279
280 BL31 key certificate identifier, used by BL2 to load the BL31 key
281 certificate.
282
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100283- **#define : SOC_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100284
285 BL31 content certificate identifier, used by BL2 to load the BL31 content
286 certificate.
287
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100288- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100289
290 BL33 key certificate identifier, used by BL2 to load the BL33 key
291 certificate.
292
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100293- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100294
295 BL33 content certificate identifier, used by BL2 to load the BL33 content
296 certificate.
297
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100298- **#define : FWU_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100299
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100300 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100301 FWU content certificate.
302
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100303- **#define : PLAT_CRYPTOCELL_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100304
Dan Handley610e7e12018-03-01 18:44:00 +0000305 This defines the base address of Arm® TrustZone® CryptoCell and must be
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100306 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
Dan Handley610e7e12018-03-01 18:44:00 +0000307 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100308 set.
309
310If the AP Firmware Updater Configuration image, BL2U is used, the following
311must also be defined:
312
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100313- **#define : BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100314
315 Defines the base address in secure memory where BL1 copies the BL2U binary
316 image. Must be aligned on a page-size boundary.
317
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100318- **#define : BL2U_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100319
320 Defines the maximum address in secure memory that the BL2U image can occupy.
321
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100322- **#define : BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100323
324 BL2U image identifier, used by BL1 to fetch an image descriptor
325 corresponding to BL2U.
326
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100327If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100328must also be defined:
329
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100330- **#define : SCP_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100331
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100332 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
333 corresponding to SCP_BL2U.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000334
335 .. note::
336 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100337
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100338If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100339also be defined:
340
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100341- **#define : NS_BL1U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100342
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100343 Defines the base address in non-secure ROM where NS_BL1U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100344 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000345
346 .. note::
347 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100348
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100349- **#define : NS_BL1U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100350
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100351 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
352 corresponding to NS_BL1U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100353
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100354If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100355be defined:
356
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100357- **#define : NS_BL2U_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100358
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100359 Defines the base address in non-secure memory where NS_BL2U executes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100360 Must be aligned on a page-size boundary.
Paul Beesleyba3ed402019-03-13 16:20:44 +0000361
362 .. note::
363 TF-A does not provide source code for this image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100364
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100365- **#define : NS_BL2U_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100366
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100367 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
368 corresponding to NS_BL2U.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100369
370For the the Firmware update capability of TRUSTED BOARD BOOT, the following
371macros may also be defined:
372
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100373- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374
375 Total number of images that can be loaded simultaneously. If the platform
376 doesn't specify any value, it defaults to 10.
377
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100378If a SCP_BL2 image is supported by the platform, the following constants must
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100379also be defined:
380
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100381- **#define : SCP_BL2_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100382
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100383 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000384 from platform storage before being transferred to the SCP.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100385
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100386- **#define : SCP_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100387
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100388 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100389 certificate (mandatory when Trusted Board Boot is enabled).
390
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100391- **#define : SCP_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100393 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100394 content certificate (mandatory when Trusted Board Boot is enabled).
395
396If a BL32 image is supported by the platform, the following constants must
397also be defined:
398
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100399- **#define : BL32_IMAGE_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100400
401 BL32 image identifier, used by BL2 to load BL32.
402
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100403- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100404
405 BL32 key certificate identifier, used by BL2 to load the BL32 key
406 certificate (mandatory when Trusted Board Boot is enabled).
407
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100408- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100409
410 BL32 content certificate identifier, used by BL2 to load the BL32 content
411 certificate (mandatory when Trusted Board Boot is enabled).
412
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100413- **#define : BL32_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100414
415 Defines the base address in secure memory where BL2 loads the BL32 binary
416 image. Must be aligned on a page-size boundary.
417
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100418- **#define : BL32_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100419
420 Defines the maximum address that the BL32 image can occupy.
421
422If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
423platform, the following constants must also be defined:
424
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100425- **#define : TSP_SEC_MEM_BASE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100426
427 Defines the base address of the secure memory used by the TSP image on the
428 platform. This must be at the same address or below ``BL32_BASE``.
429
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100430- **#define : TSP_SEC_MEM_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100431
432 Defines the size of the secure memory used by the BL32 image on the
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000433 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
434 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
435 and ``BL32_LIMIT``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100436
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100437- **#define : TSP_IRQ_SEC_PHY_TIMER**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100438
439 Defines the ID of the secure physical generic timer interrupt used by the
440 TSP's interrupt handling code.
441
442If the platform port uses the translation table library code, the following
443constants must also be defined:
444
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100445- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100446
447 Optional flag that can be set per-image to enable the dynamic allocation of
448 regions even when the MMU is enabled. If not defined, only static
449 functionality will be available, if defined and set to 1 it will also
450 include the dynamic functionality.
451
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100452- **#define : MAX_XLAT_TABLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100453
454 Defines the maximum number of translation tables that are allocated by the
455 translation table library code. To minimize the amount of runtime memory
456 used, choose the smallest value needed to map the required virtual addresses
457 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
458 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
459 as well.
460
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100461- **#define : MAX_MMAP_REGIONS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100462
463 Defines the maximum number of regions that are allocated by the translation
464 table library code. A region consists of physical base address, virtual base
465 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
466 defined in the ``mmap_region_t`` structure. The platform defines the regions
467 that should be mapped. Then, the translation table library will create the
468 corresponding tables and descriptors at runtime. To minimize the amount of
469 runtime memory used, choose the smallest value needed to register the
470 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
471 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
472 the dynamic regions as well.
473
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100474- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100475
476 Defines the total size of the virtual address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000477 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100478
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100479- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100480
481 Defines the total size of the physical address space in bytes. For example,
David Cunadoc1503122018-02-16 21:12:58 +0000482 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100483
484If the platform port uses the IO storage framework, the following constants
485must also be defined:
486
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100487- **#define : MAX_IO_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100488
489 Defines the maximum number of registered IO devices. Attempting to register
490 more devices than this value using ``io_register_device()`` will fail with
491 -ENOMEM.
492
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100493- **#define : MAX_IO_HANDLES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100494
495 Defines the maximum number of open IO handles. Attempting to open more IO
496 entities than this value using ``io_open()`` will fail with -ENOMEM.
497
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100498- **#define : MAX_IO_BLOCK_DEVICES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100499
500 Defines the maximum number of registered IO block devices. Attempting to
501 register more devices this value using ``io_dev_open()`` will fail
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100502 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100503 With this macro, multiple block devices could be supported at the same
504 time.
505
506If the platform needs to allocate data within the per-cpu data framework in
507BL31, it should define the following macro. Currently this is only required if
508the platform decides not to use the coherent memory section by undefining the
509``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
510required memory within the the per-cpu data to minimize wastage.
511
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100512- **#define : PLAT_PCPU_DATA_SIZE**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100513
514 Defines the memory (in bytes) to be reserved within the per-cpu data
515 structure for use by the platform layer.
516
517The following constants are optional. They should be defined when the platform
Dan Handley610e7e12018-03-01 18:44:00 +0000518memory layout implies some image overlaying like in Arm standard platforms.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100519
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100520- **#define : BL31_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100521
522 Defines the maximum address in secure RAM that the BL31's progbits sections
523 can occupy.
524
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100525- **#define : TSP_PROGBITS_LIMIT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100526
527 Defines the maximum address that the TSP's progbits sections can occupy.
528
529If the platform port uses the PL061 GPIO driver, the following constant may
530optionally be defined:
531
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100532- **PLAT_PL061_MAX_GPIOS**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100533 Maximum number of GPIOs required by the platform. This allows control how
534 much memory is allocated for PL061 GPIO controllers. The default value is
535
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100536 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100537
538If the platform port uses the partition driver, the following constant may
539optionally be defined:
540
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100541- **PLAT_PARTITION_MAX_ENTRIES**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100542 Maximum number of partition entries required by the platform. This allows
543 control how much memory is allocated for partition entries. The default
544 value is 128.
545 `For example, define the build flag in platform.mk`_:
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100546 PLAT_PARTITION_MAX_ENTRIES := 12
547 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100548
549The following constant is optional. It should be defined to override the default
550behaviour of the ``assert()`` function (for example, to save memory).
551
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100552- **PLAT_LOG_LEVEL_ASSERT**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100553 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
554 ``assert()`` prints the name of the file, the line number and the asserted
555 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
556 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
557 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
558 defined, it defaults to ``LOG_LEVEL``.
559
Dimitris Papastamos60346db2017-12-13 10:54:37 +0000560If the platform port uses the Activity Monitor Unit, the following constants
561may be defined:
562
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100563- **PLAT_AMU_GROUP1_COUNTERS_MASK**
Dimitris Papastamos60346db2017-12-13 10:54:37 +0000564 This mask reflects the set of group counters that should be enabled. The
565 maximum number of group 1 counters supported by AMUv1 is 16 so the mask
566 can be at most 0xffff. If the platform does not define this mask, no group 1
567 counters are enabled. If the platform defines this mask, the following
568 constant needs to also be defined.
569
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100570- **PLAT_AMU_GROUP1_NR_COUNTERS**
Dimitris Papastamos60346db2017-12-13 10:54:37 +0000571 This value is used to allocate an array to save and restore the counters
572 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend.
573 This value should be equal to the highest bit position set in the
574 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16.
575
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100576File : plat_macros.S [mandatory]
577~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100578
579Each platform must ensure a file of this name is in the system include path with
Dan Handley610e7e12018-03-01 18:44:00 +0000580the following macro defined. In the Arm development platforms, this file is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100581found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
582
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100583- **Macro : plat_crash_print_regs**
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100584
585 This macro allows the crash reporting routine to print relevant platform
586 registers in case of an unhandled exception in BL31. This aids in debugging
587 and this macro can be defined to be empty in case register reporting is not
588 desired.
589
590 For instance, GIC or interconnect registers may be helpful for
591 troubleshooting.
592
593Handling Reset
594--------------
595
596BL1 by default implements the reset vector where execution starts from a cold
597or warm boot. BL31 can be optionally set as a reset vector using the
598``RESET_TO_BL31`` make variable.
599
600For each CPU, the reset vector code is responsible for the following tasks:
601
602#. Distinguishing between a cold boot and a warm boot.
603
604#. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
605 the CPU is placed in a platform-specific state until the primary CPU
606 performs the necessary steps to remove it from this state.
607
608#. In the case of a warm boot, ensuring that the CPU jumps to a platform-
609 specific address in the BL31 image in the same processor mode as it was
610 when released from reset.
611
612The following functions need to be implemented by the platform port to enable
613reset vector code to perform the above tasks.
614
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100615Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
616~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100617
618::
619
620 Argument : void
621 Return : uintptr_t
622
623This function is called with the MMU and caches disabled
624(``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
625distinguishing between a warm and cold reset for the current CPU using
626platform-specific means. If it's a warm reset, then it returns the warm
627reset entrypoint point provided to ``plat_setup_psci_ops()`` during
628BL31 initialization. If it's a cold reset then this function must return zero.
629
630This function does not follow the Procedure Call Standard used by the
Dan Handley610e7e12018-03-01 18:44:00 +0000631Application Binary Interface for the Arm 64-bit architecture. The caller should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100632not assume that callee saved registers are preserved across a call to this
633function.
634
635This function fulfills requirement 1 and 3 listed above.
636
637Note that for platforms that support programming the reset address, it is
638expected that a CPU will start executing code directly at the right address,
639both on a cold and warm reset. In this case, there is no need to identify the
640type of reset nor to query the warm reset entrypoint. Therefore, implementing
641this function is not required on such platforms.
642
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100643Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
644~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100645
646::
647
648 Argument : void
649
650This function is called with the MMU and data caches disabled. It is responsible
651for placing the executing secondary CPU in a platform-specific state until the
652primary CPU performs the necessary actions to bring it out of that state and
653allow entry into the OS. This function must not return.
654
Dan Handley610e7e12018-03-01 18:44:00 +0000655In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100656itself off. The primary CPU is responsible for powering up the secondary CPUs
657when normal world software requires them. When booting an EL3 payload instead,
658they stay powered on and are put in a holding pen until their mailbox gets
659populated.
660
661This function fulfills requirement 2 above.
662
663Note that for platforms that can't release secondary CPUs out of reset, only the
664primary CPU will execute the cold boot code. Therefore, implementing this
665function is not required on such platforms.
666
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100667Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
668~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100669
670::
671
672 Argument : void
673 Return : unsigned int
674
675This function identifies whether the current CPU is the primary CPU or a
676secondary CPU. A return value of zero indicates that the CPU is not the
677primary CPU, while a non-zero return value indicates that the CPU is the
678primary CPU.
679
680Note that for platforms that can't release secondary CPUs out of reset, only the
681primary CPU will execute the cold boot code. Therefore, there is no need to
682distinguish between primary and secondary CPUs and implementing this function is
683not required.
684
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100685Function : platform_mem_init() [mandatory]
686~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100687
688::
689
690 Argument : void
691 Return : void
692
693This function is called before any access to data is made by the firmware, in
694order to carry out any essential memory initialization.
695
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100696Function: plat_get_rotpk_info()
697~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100698
699::
700
701 Argument : void *, void **, unsigned int *, unsigned int *
702 Return : int
703
704This function is mandatory when Trusted Board Boot is enabled. It returns a
705pointer to the ROTPK stored in the platform (or a hash of it) and its length.
706The ROTPK must be encoded in DER format according to the following ASN.1
707structure:
708
709::
710
711 AlgorithmIdentifier ::= SEQUENCE {
712 algorithm OBJECT IDENTIFIER,
713 parameters ANY DEFINED BY algorithm OPTIONAL
714 }
715
716 SubjectPublicKeyInfo ::= SEQUENCE {
717 algorithm AlgorithmIdentifier,
718 subjectPublicKey BIT STRING
719 }
720
721In case the function returns a hash of the key:
722
723::
724
725 DigestInfo ::= SEQUENCE {
726 digestAlgorithm AlgorithmIdentifier,
727 digest OCTET STRING
728 }
729
730The function returns 0 on success. Any other value is treated as error by the
731Trusted Board Boot. The function also reports extra information related
732to the ROTPK in the flags parameter:
733
734::
735
736 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
737 hash.
738 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
739 verification while the platform ROTPK is not deployed.
740 When this flag is set, the function does not need to
741 return a platform ROTPK, and the authentication
742 framework uses the ROTPK in the certificate without
743 verifying it against the platform value. This flag
744 must not be used in a deployed production environment.
745
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100746Function: plat_get_nv_ctr()
747~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100748
749::
750
751 Argument : void *, unsigned int *
752 Return : int
753
754This function is mandatory when Trusted Board Boot is enabled. It returns the
755non-volatile counter value stored in the platform in the second argument. The
756cookie in the first argument may be used to select the counter in case the
757platform provides more than one (for example, on platforms that use the default
758TBBR CoT, the cookie will correspond to the OID values defined in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100759TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100760
761The function returns 0 on success. Any other value means the counter value could
762not be retrieved from the platform.
763
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100764Function: plat_set_nv_ctr()
765~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100766
767::
768
769 Argument : void *, unsigned int
770 Return : int
771
772This function is mandatory when Trusted Board Boot is enabled. It sets a new
773counter value in the platform. The cookie in the first argument may be used to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100774select the counter (as explained in plat_get_nv_ctr()). The second argument is
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100775the updated counter value to be written to the NV counter.
776
777The function returns 0 on success. Any other value means the counter value could
778not be updated.
779
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100780Function: plat_set_nv_ctr2()
781~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100782
783::
784
785 Argument : void *, const auth_img_desc_t *, unsigned int
786 Return : int
787
788This function is optional when Trusted Board Boot is enabled. If this
789interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
790first argument passed is a cookie and is typically used to
791differentiate between a Non Trusted NV Counter and a Trusted NV
792Counter. The second argument is a pointer to an authentication image
793descriptor and may be used to decide if the counter is allowed to be
794updated or not. The third argument is the updated counter value to
795be written to the NV counter.
796
797The function returns 0 on success. Any other value means the counter value
798either could not be updated or the authentication image descriptor indicates
799that it is not allowed to be updated.
800
801Common mandatory function modifications
802---------------------------------------
803
804The following functions are mandatory functions which need to be implemented
805by the platform port.
806
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100807Function : plat_my_core_pos()
808~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100809
810::
811
812 Argument : void
813 Return : unsigned int
814
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000815This function returns the index of the calling CPU which is used as a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100816CPU-specific linear index into blocks of memory (for example while allocating
817per-CPU stacks). This function will be invoked very early in the
818initialization sequence which mandates that this function should be
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000819implemented in assembly and should not rely on the availability of a C
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100820runtime environment. This function can clobber x0 - x8 and must preserve
821x9 - x29.
822
823This function plays a crucial role in the power domain topology framework in
824PSCI and details of this can be found in `Power Domain Topology Design`_.
825
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100826Function : plat_core_pos_by_mpidr()
827~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100828
829::
830
831 Argument : u_register_t
832 Return : int
833
834This function validates the ``MPIDR`` of a CPU and converts it to an index,
835which can be used as a CPU-specific linear index into blocks of memory. In
836case the ``MPIDR`` is invalid, this function returns -1. This function will only
837be invoked by BL31 after the power domain topology is initialized and can
Dan Handley610e7e12018-03-01 18:44:00 +0000838utilize the C runtime environment. For further details about how TF-A
839represents the power domain topology and how this relates to the linear CPU
840index, please refer `Power Domain Topology Design`_.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100841
Ambroise Vincentd207f562019-04-10 12:50:27 +0100842Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
843~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
844
845::
846
847 Arguments : void **heap_addr, size_t *heap_size
848 Return : int
849
850This function is invoked during Mbed TLS library initialisation to get a heap,
851by means of a starting address and a size. This heap will then be used
852internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
853must be able to provide a heap to it.
854
855A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
856which a heap is statically reserved during compile time inside every image
857(i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
858the function simply returns the address and size of this "pre-allocated" heap.
859For a platform to use this default implementation, only a call to the helper
860from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
861
862However, by writting their own implementation, platforms have the potential to
863optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
864shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
865twice.
866
867On success the function should return 0 and a negative error code otherwise.
868
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100869Common optional modifications
870-----------------------------
871
872The following are helper functions implemented by the firmware that perform
873common platform-specific tasks. A platform may choose to override these
874definitions.
875
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100876Function : plat_set_my_stack()
877~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100878
879::
880
881 Argument : void
882 Return : void
883
884This function sets the current stack pointer to the normal memory stack that
885has been allocated for the current CPU. For BL images that only require a
886stack for the primary CPU, the UP version of the function is used. The size
887of the stack allocated to each CPU is specified by the platform defined
888constant ``PLATFORM_STACK_SIZE``.
889
890Common implementations of this function for the UP and MP BL images are
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100891provided in `plat/common/aarch64/platform_up_stack.S`_ and
892`plat/common/aarch64/platform_mp_stack.S`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100893
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100894Function : plat_get_my_stack()
895~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100896
897::
898
899 Argument : void
900 Return : uintptr_t
901
902This function returns the base address of the normal memory stack that
903has been allocated for the current CPU. For BL images that only require a
904stack for the primary CPU, the UP version of the function is used. The size
905of the stack allocated to each CPU is specified by the platform defined
906constant ``PLATFORM_STACK_SIZE``.
907
908Common implementations of this function for the UP and MP BL images are
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100909provided in `plat/common/aarch64/platform_up_stack.S`_ and
910`plat/common/aarch64/platform_mp_stack.S`_
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100911
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100912Function : plat_report_exception()
913~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100914
915::
916
917 Argument : unsigned int
918 Return : void
919
920A platform may need to report various information about its status when an
921exception is taken, for example the current exception level, the CPU security
922state (secure/non-secure), the exception type, and so on. This function is
923called in the following circumstances:
924
925- In BL1, whenever an exception is taken.
926- In BL2, whenever an exception is taken.
927
928The default implementation doesn't do anything, to avoid making assumptions
929about the way the platform displays its status information.
930
931For AArch64, this function receives the exception type as its argument.
932Possible values for exceptions types are listed in the
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100933`include/common/bl_common.h`_ header file. Note that these constants are not
Dan Handley610e7e12018-03-01 18:44:00 +0000934related to any architectural exception code; they are just a TF-A convention.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100935
936For AArch32, this function receives the exception mode as its argument.
937Possible values for exception modes are listed in the
938`include/lib/aarch32/arch.h`_ header file.
939
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100940Function : plat_reset_handler()
941~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100942
943::
944
945 Argument : void
946 Return : void
947
948A platform may need to do additional initialization after reset. This function
949allows the platform to do the platform specific intializations. Platform
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000950specific errata workarounds could also be implemented here. The API should
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100951preserve the values of callee saved registers x19 to x29.
952
953The default implementation doesn't do anything. If a platform needs to override
954the default implementation, refer to the `Firmware Design`_ for general
955guidelines.
956
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100957Function : plat_disable_acp()
958~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100959
960::
961
962 Argument : void
963 Return : void
964
John Tsichritzis6dda9762018-07-23 09:18:04 +0100965This API allows a platform to disable the Accelerator Coherency Port (if
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100966present) during a cluster power down sequence. The default weak implementation
John Tsichritzis6dda9762018-07-23 09:18:04 +0100967doesn't do anything. Since this API is called during the power down sequence,
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100968it has restrictions for stack usage and it can use the registers x0 - x17 as
969scratch registers. It should preserve the value in x18 register as it is used
970by the caller to store the return address.
971
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100972Function : plat_error_handler()
973~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100974
975::
976
977 Argument : int
978 Return : void
979
980This API is called when the generic code encounters an error situation from
981which it cannot continue. It allows the platform to perform error reporting or
982recovery actions (for example, reset the system). This function must not return.
983
984The parameter indicates the type of error using standard codes from ``errno.h``.
985Possible errors reported by the generic code are:
986
987- ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
988 Board Boot is enabled)
989- ``-ENOENT``: the requested image or certificate could not be found or an IO
990 error was detected
Dan Handley610e7e12018-03-01 18:44:00 +0000991- ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
992 error is usually an indication of an incorrect array size
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100993
994The default implementation simply spins.
995
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +0100996Function : plat_panic_handler()
997~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100998
999::
1000
1001 Argument : void
1002 Return : void
1003
1004This API is called when the generic code encounters an unexpected error
1005situation from which it cannot recover. This function must not return,
1006and must be implemented in assembly because it may be called before the C
1007environment is initialized.
1008
Paul Beesleyba3ed402019-03-13 16:20:44 +00001009.. note::
1010 The address from where it was called is stored in x30 (Link Register).
1011 The default implementation simply spins.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001012
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001013Function : plat_get_bl_image_load_info()
1014~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001015
1016::
1017
1018 Argument : void
1019 Return : bl_load_info_t *
1020
1021This function returns pointer to the list of images that the platform has
Soby Mathew97b1bff2018-09-27 16:46:41 +01001022populated to load. This function is invoked in BL2 to load the
1023BL3xx images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001024
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001025Function : plat_get_next_bl_params()
1026~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001027
1028::
1029
1030 Argument : void
1031 Return : bl_params_t *
1032
1033This function returns a pointer to the shared memory that the platform has
Dan Handley610e7e12018-03-01 18:44:00 +00001034kept aside to pass TF-A related information that next BL image needs. This
Soby Mathew97b1bff2018-09-27 16:46:41 +01001035function is invoked in BL2 to pass this information to the next BL
1036image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001037
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001038Function : plat_get_stack_protector_canary()
1039~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001040
1041::
1042
1043 Argument : void
1044 Return : u_register_t
1045
1046This function returns a random value that is used to initialize the canary used
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001047when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001048value will weaken the protection as the attacker could easily write the right
1049value as part of the attack most of the time. Therefore, it should return a
1050true random number.
1051
Paul Beesleyba3ed402019-03-13 16:20:44 +00001052.. warning::
1053 For the protection to be effective, the global data need to be placed at
1054 a lower address than the stack bases. Failure to do so would allow an
1055 attacker to overwrite the canary as part of the stack buffer overflow attack.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001056
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001057Function : plat_flush_next_bl_params()
1058~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001059
1060::
1061
1062 Argument : void
1063 Return : void
1064
1065This function flushes to main memory all the image params that are passed to
Soby Mathew97b1bff2018-09-27 16:46:41 +01001066next image. This function is invoked in BL2 to flush this information
1067to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001068
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001069Function : plat_log_get_prefix()
1070~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Soby Mathewaaf15f52017-09-04 11:49:29 +01001071
1072::
1073
1074 Argument : unsigned int
1075 Return : const char *
1076
1077This function defines the prefix string corresponding to the `log_level` to be
Dan Handley610e7e12018-03-01 18:44:00 +00001078prepended to all the log output from TF-A. The `log_level` (argument) will
1079correspond to one of the standard log levels defined in debug.h. The platform
1080can override the common implementation to define a different prefix string for
John Tsichritzis30f89642018-06-07 16:31:34 +01001081the log output. The implementation should be robust to future changes that
Dan Handley610e7e12018-03-01 18:44:00 +00001082increase the number of log levels.
Soby Mathewaaf15f52017-09-04 11:49:29 +01001083
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001084Modifications specific to a Boot Loader stage
1085---------------------------------------------
1086
1087Boot Loader Stage 1 (BL1)
1088-------------------------
1089
1090BL1 implements the reset vector where execution starts from after a cold or
1091warm boot. For each CPU, BL1 is responsible for the following tasks:
1092
1093#. Handling the reset as described in section 2.2
1094
1095#. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1096 only this CPU executes the remaining BL1 code, including loading and passing
1097 control to the BL2 stage.
1098
1099#. Identifying and starting the Firmware Update process (if required).
1100
1101#. Loading the BL2 image from non-volatile storage into secure memory at the
1102 address specified by the platform defined constant ``BL2_BASE``.
1103
1104#. Populating a ``meminfo`` structure with the following information in memory,
1105 accessible by BL2 immediately upon entry.
1106
1107 ::
1108
1109 meminfo.total_base = Base address of secure RAM visible to BL2
1110 meminfo.total_size = Size of secure RAM visible to BL2
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001111
Soby Mathew97b1bff2018-09-27 16:46:41 +01001112 By default, BL1 places this ``meminfo`` structure at the end of secure
1113 memory visible to BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001114
Soby Mathewb1bf0442018-02-16 14:52:52 +00001115 It is possible for the platform to decide where it wants to place the
1116 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1117 BL2 by overriding the weak default implementation of
1118 ``bl1_plat_handle_post_image_load`` API.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001119
1120The following functions need to be implemented by the platform port to enable
1121BL1 to perform the above tasks.
1122
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001123Function : bl1_early_platform_setup() [mandatory]
1124~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001125
1126::
1127
1128 Argument : void
1129 Return : void
1130
1131This function executes with the MMU and data caches disabled. It is only called
1132by the primary CPU.
1133
Dan Handley610e7e12018-03-01 18:44:00 +00001134On Arm standard platforms, this function:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001135
1136- Enables a secure instance of SP805 to act as the Trusted Watchdog.
1137
1138- Initializes a UART (PL011 console), which enables access to the ``printf``
1139 family of functions in BL1.
1140
1141- Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1142 the CCI slave interface corresponding to the cluster that includes the
1143 primary CPU.
1144
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001145Function : bl1_plat_arch_setup() [mandatory]
1146~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001147
1148::
1149
1150 Argument : void
1151 Return : void
1152
1153This function performs any platform-specific and architectural setup that the
1154platform requires. Platform-specific setup might include configuration of
1155memory controllers and the interconnect.
1156
Dan Handley610e7e12018-03-01 18:44:00 +00001157In Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001158
1159This function helps fulfill requirement 2 above.
1160
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001161Function : bl1_platform_setup() [mandatory]
1162~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001163
1164::
1165
1166 Argument : void
1167 Return : void
1168
1169This function executes with the MMU and data caches enabled. It is responsible
1170for performing any remaining platform-specific setup that can occur after the
1171MMU and data cache have been enabled.
1172
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001173if support for multiple boot sources is required, it initializes the boot
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001174sequence used by plat_try_next_boot_source().
Roberto Vargas0cd866c2017-12-12 10:39:44 +00001175
Dan Handley610e7e12018-03-01 18:44:00 +00001176In Arm standard platforms, this function initializes the storage abstraction
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001177layer used to load the next bootloader image.
1178
1179This function helps fulfill requirement 4 above.
1180
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001181Function : bl1_plat_sec_mem_layout() [mandatory]
1182~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001183
1184::
1185
1186 Argument : void
1187 Return : meminfo *
1188
1189This function should only be called on the cold boot path. It executes with the
1190MMU and data caches enabled. The pointer returned by this function must point to
1191a ``meminfo`` structure containing the extents and availability of secure RAM for
1192the BL1 stage.
1193
1194::
1195
1196 meminfo.total_base = Base address of secure RAM visible to BL1
1197 meminfo.total_size = Size of secure RAM visible to BL1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001198
1199This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1200populates a similar structure to tell BL2 the extents of memory available for
1201its own use.
1202
1203This function helps fulfill requirements 4 and 5 above.
1204
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001205Function : bl1_plat_prepare_exit() [optional]
1206~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001207
1208::
1209
1210 Argument : entry_point_info_t *
1211 Return : void
1212
1213This function is called prior to exiting BL1 in response to the
1214``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1215platform specific clean up or bookkeeping operations before transferring
1216control to the next image. It receives the address of the ``entry_point_info_t``
1217structure passed from BL2. This function runs with MMU disabled.
1218
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001219Function : bl1_plat_set_ep_info() [optional]
1220~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001221
1222::
1223
1224 Argument : unsigned int image_id, entry_point_info_t *ep_info
1225 Return : void
1226
1227This function allows platforms to override ``ep_info`` for the given ``image_id``.
1228
1229The default implementation just returns.
1230
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001231Function : bl1_plat_get_next_image_id() [optional]
1232~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001233
1234::
1235
1236 Argument : void
1237 Return : unsigned int
1238
1239This and the following function must be overridden to enable the FWU feature.
1240
1241BL1 calls this function after platform setup to identify the next image to be
1242loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1243with the normal boot sequence, which loads and executes BL2. If the platform
1244returns a different image id, BL1 assumes that Firmware Update is required.
1245
Dan Handley610e7e12018-03-01 18:44:00 +00001246The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001247platforms override this function to detect if firmware update is required, and
1248if so, return the first image in the firmware update process.
1249
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001250Function : bl1_plat_get_image_desc() [optional]
1251~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001252
1253::
1254
1255 Argument : unsigned int image_id
1256 Return : image_desc_t *
1257
1258BL1 calls this function to get the image descriptor information ``image_desc_t``
1259for the provided ``image_id`` from the platform.
1260
Dan Handley610e7e12018-03-01 18:44:00 +00001261The default implementation always returns a common BL2 image descriptor. Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001262standard platforms return an image descriptor corresponding to BL2 or one of
1263the firmware update images defined in the Trusted Board Boot Requirements
1264specification.
1265
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001266Function : bl1_plat_handle_pre_image_load() [optional]
1267~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001268
1269::
1270
Soby Mathew2f38ce32018-02-08 17:45:12 +00001271 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001272 Return : int
1273
1274This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001275corresponding to ``image_id``. This function is invoked in BL1, both in cold
1276boot and FWU code path, before loading the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001277
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001278Function : bl1_plat_handle_post_image_load() [optional]
1279~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001280
1281::
1282
Soby Mathew2f38ce32018-02-08 17:45:12 +00001283 Argument : unsigned int image_id
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001284 Return : int
1285
1286This function can be used by the platforms to update/use image information
Soby Mathew2f38ce32018-02-08 17:45:12 +00001287corresponding to ``image_id``. This function is invoked in BL1, both in cold
1288boot and FWU code path, after loading and authenticating the image.
Masahiro Yamada43d20b32018-02-01 16:46:18 +09001289
Soby Mathewb1bf0442018-02-16 14:52:52 +00001290The default weak implementation of this function calculates the amount of
1291Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1292structure at the beginning of this free memory and populates it. The address
1293of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1294information to BL2.
1295
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001296Function : bl1_plat_fwu_done() [optional]
1297~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001298
1299::
1300
1301 Argument : unsigned int image_id, uintptr_t image_src,
1302 unsigned int image_size
1303 Return : void
1304
1305BL1 calls this function when the FWU process is complete. It must not return.
1306The platform may override this function to take platform specific action, for
1307example to initiate the normal boot flow.
1308
1309The default implementation spins forever.
1310
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001311Function : bl1_plat_mem_check() [mandatory]
1312~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001313
1314::
1315
1316 Argument : uintptr_t mem_base, unsigned int mem_size,
1317 unsigned int flags
1318 Return : int
1319
1320BL1 calls this function while handling FWU related SMCs, more specifically when
1321copying or authenticating an image. Its responsibility is to ensure that the
1322region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1323that this memory corresponds to either a secure or non-secure memory region as
1324indicated by the security state of the ``flags`` argument.
1325
1326This function can safely assume that the value resulting from the addition of
1327``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1328overflow.
1329
1330This function must return 0 on success, a non-null error code otherwise.
1331
1332The default implementation of this function asserts therefore platforms must
1333override it when using the FWU feature.
1334
1335Boot Loader Stage 2 (BL2)
1336-------------------------
1337
1338The BL2 stage is executed only by the primary CPU, which is determined in BL1
1339using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
Soby Mathew97b1bff2018-09-27 16:46:41 +01001340``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1341``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1342non-volatile storage to secure/non-secure RAM. After all the images are loaded
1343then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1344images to be passed to the next BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001345
1346The following functions must be implemented by the platform port to enable BL2
1347to perform the above tasks.
1348
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001349Function : bl2_early_platform_setup2() [mandatory]
1350~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001351
1352::
1353
Soby Mathew97b1bff2018-09-27 16:46:41 +01001354 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001355 Return : void
1356
1357This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001358by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1359are platform specific.
1360
1361On Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001362
Soby Mathew97b1bff2018-09-27 16:46:41 +01001363 arg0 - Points to load address of HW_CONFIG if present
1364
1365 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1366 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001367
Dan Handley610e7e12018-03-01 18:44:00 +00001368On Arm standard platforms, this function also:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001369
1370- Initializes a UART (PL011 console), which enables access to the ``printf``
1371 family of functions in BL2.
1372
1373- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001374 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1375 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001376
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001377Function : bl2_plat_arch_setup() [mandatory]
1378~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001379
1380::
1381
1382 Argument : void
1383 Return : void
1384
1385This function executes with the MMU and data caches disabled. It is only called
1386by the primary CPU.
1387
1388The purpose of this function is to perform any architectural initialization
1389that varies across platforms.
1390
Dan Handley610e7e12018-03-01 18:44:00 +00001391On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001392
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001393Function : bl2_platform_setup() [mandatory]
1394~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001395
1396::
1397
1398 Argument : void
1399 Return : void
1400
1401This function may execute with the MMU and data caches enabled if the platform
1402port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1403called by the primary CPU.
1404
1405The purpose of this function is to perform any platform initialization
1406specific to BL2.
1407
Dan Handley610e7e12018-03-01 18:44:00 +00001408In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001409configuration of the TrustZone controller to allow non-secure masters access
1410to most of DRAM. Part of DRAM is reserved for secure world use.
1411
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001412Function : bl2_plat_handle_pre_image_load() [optional]
1413~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001414
1415::
1416
1417 Argument : unsigned int
1418 Return : int
1419
1420This function can be used by the platforms to update/use image information
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001421for given ``image_id``. This function is currently invoked in BL2 before
Soby Mathew97b1bff2018-09-27 16:46:41 +01001422loading each image.
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001423
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001424Function : bl2_plat_handle_post_image_load() [optional]
1425~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Masahiro Yamada02a0d3d2018-02-01 16:45:51 +09001426
1427::
1428
1429 Argument : unsigned int
1430 Return : int
1431
1432This function can be used by the platforms to update/use image information
1433for given ``image_id``. This function is currently invoked in BL2 after
Soby Mathew97b1bff2018-09-27 16:46:41 +01001434loading each image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001435
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001436Function : bl2_plat_preload_setup [optional]
1437~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001438
1439::
John Tsichritzisee10e792018-06-06 09:38:10 +01001440
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001441 Argument : void
1442 Return : void
1443
1444This optional function performs any BL2 platform initialization
1445required before image loading, that is not done later in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001446bl2_platform_setup(). Specifically, if support for multiple
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001447boot sources is required, it initializes the boot sequence used by
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001448plat_try_next_boot_source().
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001449
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001450Function : plat_try_next_boot_source() [optional]
1451~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001452
1453::
John Tsichritzisee10e792018-06-06 09:38:10 +01001454
Roberto Vargasbc1ae1f2017-09-26 12:53:01 +01001455 Argument : void
1456 Return : int
1457
1458This optional function passes to the next boot source in the redundancy
1459sequence.
1460
1461This function moves the current boot redundancy source to the next
1462element in the boot sequence. If there are no more boot sources then it
1463must return 0, otherwise it must return 1. The default implementation
1464of this always returns 0.
1465
Roberto Vargasb1584272017-11-20 13:36:10 +00001466Boot Loader Stage 2 (BL2) at EL3
1467--------------------------------
1468
Dan Handley610e7e12018-03-01 18:44:00 +00001469When the platform has a non-TF-A Boot ROM it is desirable to jump
1470directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
Roberto Vargasb1584272017-11-20 13:36:10 +00001471execute at EL3 instead of executing at EL1. Refer to the `Firmware
1472Design`_ for more information.
1473
1474All mandatory functions of BL2 must be implemented, except the functions
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001475bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1476their work is done now by bl2_el3_early_platform_setup and
1477bl2_el3_plat_arch_setup. These functions should generally implement
1478the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
Roberto Vargasb1584272017-11-20 13:36:10 +00001479
1480
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001481Function : bl2_el3_early_platform_setup() [mandatory]
1482~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001483
1484::
John Tsichritzisee10e792018-06-06 09:38:10 +01001485
Roberto Vargasb1584272017-11-20 13:36:10 +00001486 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1487 Return : void
1488
1489This function executes with the MMU and data caches disabled. It is only called
1490by the primary CPU. This function receives four parameters which can be used
1491by the platform to pass any needed information from the Boot ROM to BL2.
1492
Dan Handley610e7e12018-03-01 18:44:00 +00001493On Arm standard platforms, this function does the following:
Roberto Vargasb1584272017-11-20 13:36:10 +00001494
1495- Initializes a UART (PL011 console), which enables access to the ``printf``
1496 family of functions in BL2.
1497
1498- Initializes the storage abstraction layer used to load further bootloader
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001499 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1500 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
Roberto Vargasb1584272017-11-20 13:36:10 +00001501
1502- Initializes the private variables that define the memory layout used.
1503
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001504Function : bl2_el3_plat_arch_setup() [mandatory]
1505~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001506
1507::
John Tsichritzisee10e792018-06-06 09:38:10 +01001508
Roberto Vargasb1584272017-11-20 13:36:10 +00001509 Argument : void
1510 Return : void
1511
1512This function executes with the MMU and data caches disabled. It is only called
1513by the primary CPU.
1514
1515The purpose of this function is to perform any architectural initialization
1516that varies across platforms.
1517
Dan Handley610e7e12018-03-01 18:44:00 +00001518On Arm standard platforms, this function enables the MMU.
Roberto Vargasb1584272017-11-20 13:36:10 +00001519
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001520Function : bl2_el3_plat_prepare_exit() [optional]
1521~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Roberto Vargasb1584272017-11-20 13:36:10 +00001522
1523::
John Tsichritzisee10e792018-06-06 09:38:10 +01001524
Roberto Vargasb1584272017-11-20 13:36:10 +00001525 Argument : void
1526 Return : void
1527
1528This function is called prior to exiting BL2 and run the next image.
1529It should be used to perform platform specific clean up or bookkeeping
1530operations before transferring control to the next image. This function
1531runs with MMU disabled.
1532
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001533FWU Boot Loader Stage 2 (BL2U)
1534------------------------------
1535
1536The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1537process and is executed only by the primary CPU. BL1 passes control to BL2U at
1538``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1539
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001540#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
1541 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
1542 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
1543 should be copied from. Subsequent handling of the SCP_BL2U image is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001544 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1545 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
1546
1547#. Any platform specific setup required to perform the FWU process. For
Dan Handley610e7e12018-03-01 18:44:00 +00001548 example, Arm standard platforms initialize the TZC controller so that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001549 normal world can access DDR memory.
1550
1551The following functions must be implemented by the platform port to enable
1552BL2U to perform the tasks mentioned above.
1553
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001554Function : bl2u_early_platform_setup() [mandatory]
1555~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001556
1557::
1558
1559 Argument : meminfo *mem_info, void *plat_info
1560 Return : void
1561
1562This function executes with the MMU and data caches disabled. It is only
1563called by the primary CPU. The arguments to this function is the address
1564of the ``meminfo`` structure and platform specific info provided by BL1.
1565
1566The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
1567private storage as the original memory may be subsequently overwritten by BL2U.
1568
Dan Handley610e7e12018-03-01 18:44:00 +00001569On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001570to extract SCP_BL2U image information, which is then copied into a private
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001571variable.
1572
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001573Function : bl2u_plat_arch_setup() [mandatory]
1574~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001575
1576::
1577
1578 Argument : void
1579 Return : void
1580
1581This function executes with the MMU and data caches disabled. It is only
1582called by the primary CPU.
1583
1584The purpose of this function is to perform any architectural initialization
1585that varies across platforms, for example enabling the MMU (since the memory
1586map differs across platforms).
1587
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001588Function : bl2u_platform_setup() [mandatory]
1589~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001590
1591::
1592
1593 Argument : void
1594 Return : void
1595
1596This function may execute with the MMU and data caches enabled if the platform
1597port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
1598called by the primary CPU.
1599
1600The purpose of this function is to perform any platform initialization
1601specific to BL2U.
1602
Dan Handley610e7e12018-03-01 18:44:00 +00001603In Arm standard platforms, this function performs security setup, including
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001604configuration of the TrustZone controller to allow non-secure masters access
1605to most of DRAM. Part of DRAM is reserved for secure world use.
1606
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001607Function : bl2u_plat_handle_scp_bl2u() [optional]
1608~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001609
1610::
1611
1612 Argument : void
1613 Return : int
1614
1615This function is used to perform any platform-specific actions required to
1616handle the SCP firmware. Typically it transfers the image into SCP memory using
1617a platform-specific protocol and waits until SCP executes it and signals to the
1618Application Processor (AP) for BL2U execution to continue.
1619
1620This function returns 0 on success, a negative error code otherwise.
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001621This function is included if SCP_BL2U_BASE is defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001622
1623Boot Loader Stage 3-1 (BL31)
1624----------------------------
1625
1626During cold boot, the BL31 stage is executed only by the primary CPU. This is
1627determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
1628control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
1629CPUs. BL31 executes at EL3 and is responsible for:
1630
1631#. Re-initializing all architectural and platform state. Although BL1 performs
1632 some of this initialization, BL31 remains resident in EL3 and must ensure
1633 that EL3 architectural and platform state is completely initialized. It
1634 should make no assumptions about the system state when it receives control.
1635
1636#. Passing control to a normal world BL image, pre-loaded at a platform-
Soby Mathew97b1bff2018-09-27 16:46:41 +01001637 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
1638 populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001639
1640#. Providing runtime firmware services. Currently, BL31 only implements a
1641 subset of the Power State Coordination Interface (PSCI) API as a runtime
1642 service. See Section 3.3 below for details of porting the PSCI
1643 implementation.
1644
1645#. Optionally passing control to the BL32 image, pre-loaded at a platform-
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001646 specific address by BL2. BL31 exports a set of APIs that allow runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001647 services to specify the security state in which the next image should be
Soby Mathew97b1bff2018-09-27 16:46:41 +01001648 executed and run the corresponding image. On ARM platforms, BL31 uses the
1649 ``bl_params`` list populated by BL2 in memory to do this.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001650
1651If BL31 is a reset vector, It also needs to handle the reset as specified in
1652section 2.2 before the tasks described above.
1653
1654The following functions must be implemented by the platform port to enable BL31
1655to perform the above tasks.
1656
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001657Function : bl31_early_platform_setup2() [mandatory]
1658~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001659
1660::
1661
Soby Mathew97b1bff2018-09-27 16:46:41 +01001662 Argument : u_register_t, u_register_t, u_register_t, u_register_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001663 Return : void
1664
1665This function executes with the MMU and data caches disabled. It is only called
Soby Mathew97b1bff2018-09-27 16:46:41 +01001666by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
1667platform specific.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001668
Soby Mathew97b1bff2018-09-27 16:46:41 +01001669In Arm standard platforms, the arguments received are :
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001670
Soby Mathew97b1bff2018-09-27 16:46:41 +01001671 arg0 - The pointer to the head of `bl_params_t` list
1672 which is list of executable images following BL31,
1673
1674 arg1 - Points to load address of SOC_FW_CONFIG if present
1675
1676 arg2 - Points to load address of HW_CONFIG if present
1677
1678 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
1679 used in release builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001680
Soby Mathew97b1bff2018-09-27 16:46:41 +01001681The function runs through the `bl_param_t` list and extracts the entry point
1682information for BL32 and BL33. It also performs the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001683
1684- Initialize a UART (PL011 console), which enables access to the ``printf``
1685 family of functions in BL31.
1686
1687- Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
1688 CCI slave interface corresponding to the cluster that includes the primary
1689 CPU.
1690
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001691Function : bl31_plat_arch_setup() [mandatory]
1692~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001693
1694::
1695
1696 Argument : void
1697 Return : void
1698
1699This function executes with the MMU and data caches disabled. It is only called
1700by the primary CPU.
1701
1702The purpose of this function is to perform any architectural initialization
1703that varies across platforms.
1704
Dan Handley610e7e12018-03-01 18:44:00 +00001705On Arm standard platforms, this function enables the MMU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001706
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001707Function : bl31_platform_setup() [mandatory]
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001708~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1709
1710::
1711
1712 Argument : void
1713 Return : void
1714
1715This function may execute with the MMU and data caches enabled if the platform
1716port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
1717called by the primary CPU.
1718
1719The purpose of this function is to complete platform initialization so that both
1720BL31 runtime services and normal world software can function correctly.
1721
Dan Handley610e7e12018-03-01 18:44:00 +00001722On Arm standard platforms, this function does the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001723
1724- Initialize the generic interrupt controller.
1725
1726 Depending on the GIC driver selected by the platform, the appropriate GICv2
1727 or GICv3 initialization will be done, which mainly consists of:
1728
1729 - Enable secure interrupts in the GIC CPU interface.
1730 - Disable the legacy interrupt bypass mechanism.
1731 - Configure the priority mask register to allow interrupts of all priorities
1732 to be signaled to the CPU interface.
1733 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
1734 - Target all secure SPIs to CPU0.
1735 - Enable these secure interrupts in the GIC distributor.
1736 - Configure all other interrupts as non-secure.
1737 - Enable signaling of secure interrupts in the GIC distributor.
1738
1739- Enable system-level implementation of the generic timer counter through the
1740 memory mapped interface.
1741
1742- Grant access to the system counter timer module
1743
1744- Initialize the power controller device.
1745
1746 In particular, initialise the locks that prevent concurrent accesses to the
1747 power controller device.
1748
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001749Function : bl31_plat_runtime_setup() [optional]
1750~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001751
1752::
1753
1754 Argument : void
1755 Return : void
1756
1757The purpose of this function is allow the platform to perform any BL31 runtime
1758setup just prior to BL31 exit during cold boot. The default weak
Julius Werneraae9bb12017-09-18 16:49:48 -07001759implementation of this function will invoke ``console_switch_state()`` to switch
1760console output to consoles marked for use in the ``runtime`` state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001761
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001762Function : bl31_plat_get_next_image_ep_info() [mandatory]
1763~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001764
1765::
1766
Sandrine Bailleux842117d2018-05-14 14:25:47 +02001767 Argument : uint32_t
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001768 Return : entry_point_info *
1769
1770This function may execute with the MMU and data caches enabled if the platform
1771port does the necessary initializations in ``bl31_plat_arch_setup()``.
1772
1773This function is called by ``bl31_main()`` to retrieve information provided by
1774BL2 for the next image in the security state specified by the argument. BL31
1775uses this information to pass control to that image in the specified security
1776state. This function must return a pointer to the ``entry_point_info`` structure
1777(that was copied during ``bl31_early_platform_setup()``) if the image exists. It
1778should return NULL otherwise.
1779
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01001780Function : bl31_plat_enable_mmu [optional]
1781~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1782
1783::
1784
1785 Argument : uint32_t
1786 Return : void
1787
1788This function enables the MMU. The boot code calls this function with MMU and
1789caches disabled. This function should program necessary registers to enable
1790translation, and upon return, the MMU on the calling PE must be enabled.
1791
1792The function must honor flags passed in the first argument. These flags are
1793defined by the translation library, and can be found in the file
1794``include/lib/xlat_tables/xlat_mmu_helpers.h``.
1795
1796On DynamIQ systems, this function must not use stack while enabling MMU, which
Paul Beesley1fbc97b2019-01-11 18:26:51 +00001797is how the function in xlat table library version 2 is implemented.
Jeenu Viswambharane834ee12018-04-27 15:17:03 +01001798
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00001799Function : plat_init_apiakey [optional]
1800~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1801
1802::
1803
1804 Argument : void
1805 Return : uint64_t *
1806
1807This function populates the ``plat_apiakey`` array that contains the values used
1808to set the ``APIAKey{Hi,Lo}_EL1`` registers. It returns a pointer to this array.
1809
1810The value should be obtained from a reliable source of randomness.
1811
1812This function is only needed if ARMv8.3 pointer authentication is used in the
1813Trusted Firmware by building with ``ENABLE_PAUTH=1``.
1814
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001815Function : plat_get_syscnt_freq2() [mandatory]
1816~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001817
1818::
1819
1820 Argument : void
1821 Return : unsigned int
1822
1823This function is used by the architecture setup code to retrieve the counter
1824frequency for the CPU's generic timer. This value will be programmed into the
Dan Handley610e7e12018-03-01 18:44:00 +00001825``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001826of the system counter, which is retrieved from the first entry in the frequency
1827modes table.
1828
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001829#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
1830~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001831
1832When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
1833bytes) aligned to the cache line boundary that should be allocated per-cpu to
1834accommodate all the bakery locks.
1835
1836If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
1837calculates the size of the ``bakery_lock`` input section, aligns it to the
1838nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
1839and stores the result in a linker symbol. This constant prevents a platform
1840from relying on the linker and provide a more efficient mechanism for
1841accessing per-cpu bakery lock information.
1842
1843If this constant is defined and its value is not equal to the value
1844calculated by the linker then a link time assertion is raised. A compile time
1845assertion is raised if the value of the constant is not aligned to the cache
1846line boundary.
1847
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001848SDEI porting requirements
1849~~~~~~~~~~~~~~~~~~~~~~~~~
1850
Paul Beesley606d8072019-03-13 13:58:02 +00001851The |SDEI| dispatcher requires the platform to provide the following macros
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001852and functions, of which some are optional, and some others mandatory.
1853
1854Macros
1855......
1856
1857Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
1858^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1859
1860This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00001861Normal |SDEI| events on the platform. This must have a higher value
1862(therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001863
1864Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
1865^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1866
1867This macro must be defined to the EL3 exception priority level associated with
Paul Beesley606d8072019-03-13 13:58:02 +00001868Critical |SDEI| events on the platform. This must have a lower value
1869(therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001870
Paul Beesley606d8072019-03-13 13:58:02 +00001871**Note**: |SDEI| exception priorities must be the lowest among Secure
1872priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
1873be higher than Normal |SDEI| priority.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001874
1875Functions
1876.........
1877
1878Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional]
1879^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1880
1881::
1882
1883 Argument: uintptr_t
1884 Return: int
1885
1886This function validates the address of client entry points provided for both
Paul Beesley606d8072019-03-13 13:58:02 +00001887event registration and *Complete and Resume* |SDEI| calls. The function
1888takes one argument, which is the address of the handler the |SDEI| client
1889requested to register. The function must return ``0`` for successful validation,
1890or ``-1`` upon failure.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001891
Dan Handley610e7e12018-03-01 18:44:00 +00001892The default implementation always returns ``0``. On Arm platforms, this function
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001893is implemented to translate the entry point to physical address, and further to
1894ensure that the address is located in Non-secure DRAM.
1895
1896Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
1897^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1898
1899::
1900
1901 Argument: uint64_t
1902 Argument: unsigned int
1903 Return: void
1904
Paul Beesley606d8072019-03-13 13:58:02 +00001905|SDEI| specification requires that a PE comes out of reset with the events
1906masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
1907|SDEI| events on the PE. No |SDEI| events can be dispatched until such
1908time.
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001909
Paul Beesley606d8072019-03-13 13:58:02 +00001910Should a PE receive an interrupt that was bound to an |SDEI| event while the
Jeenu Viswambharan04e3a7f2017-10-16 08:43:14 +01001911events are masked on the PE, the dispatcher implementation invokes the function
1912``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
1913interrupt and the interrupt ID are passed as parameters.
1914
1915The default implementation only prints out a warning message.
1916
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001917Power State Coordination Interface (in BL31)
1918--------------------------------------------
1919
Dan Handley610e7e12018-03-01 18:44:00 +00001920The TF-A implementation of the PSCI API is based around the concept of a
1921*power domain*. A *power domain* is a CPU or a logical group of CPUs which
1922share some state on which power management operations can be performed as
1923specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
1924a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
1925*power domains* are arranged in a hierarchical tree structure and each
1926*power domain* can be identified in a system by the cpu index of any CPU that
1927is part of that domain and a *power domain level*. A processing element (for
1928example, a CPU) is at level 0. If the *power domain* node above a CPU is a
1929logical grouping of CPUs that share some state, then level 1 is that group of
1930CPUs (for example, a cluster), and level 2 is a group of clusters (for
1931example, the system). More details on the power domain topology and its
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001932organization can be found in `Power Domain Topology Design`_.
1933
1934BL31's platform initialization code exports a pointer to the platform-specific
1935power management operations required for the PSCI implementation to function
1936correctly. This information is populated in the ``plat_psci_ops`` structure. The
1937PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
1938power management operations on the power domains. For example, the target
1939CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
1940handler (if present) is called for the CPU power domain.
1941
1942The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
1943describe composite power states specific to a platform. The PSCI implementation
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001944defines a generic representation of the power-state parameter, which is an
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001945array of local power states where each index corresponds to a power domain
1946level. Each entry contains the local power state the power domain at that power
1947level could enter. It depends on the ``validate_power_state()`` handler to
1948convert the power-state parameter (possibly encoding a composite power state)
1949passed in a PSCI ``CPU_SUSPEND`` call to this representation.
1950
1951The following functions form part of platform port of PSCI functionality.
1952
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001953Function : plat_psci_stat_accounting_start() [optional]
1954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001955
1956::
1957
1958 Argument : const psci_power_state_t *
1959 Return : void
1960
1961This is an optional hook that platforms can implement for residency statistics
1962accounting before entering a low power state. The ``pwr_domain_state`` field of
1963``state_info`` (first argument) can be inspected if stat accounting is done
1964differently at CPU level versus higher levels. As an example, if the element at
1965index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
1966state, special hardware logic may be programmed in order to keep track of the
1967residency statistics. For higher levels (array indices > 0), the residency
1968statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
1969default implementation will use PMF to capture timestamps.
1970
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001971Function : plat_psci_stat_accounting_stop() [optional]
1972~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001973
1974::
1975
1976 Argument : const psci_power_state_t *
1977 Return : void
1978
1979This is an optional hook that platforms can implement for residency statistics
1980accounting after exiting from a low power state. The ``pwr_domain_state`` field
1981of ``state_info`` (first argument) can be inspected if stat accounting is done
1982differently at CPU level versus higher levels. As an example, if the element at
1983index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
1984state, special hardware logic may be programmed in order to keep track of the
1985residency statistics. For higher levels (array indices > 0), the residency
1986statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
1987default implementation will use PMF to capture timestamps.
1988
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01001989Function : plat_psci_stat_get_residency() [optional]
1990~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001991
1992::
1993
1994 Argument : unsigned int, const psci_power_state_t *, int
1995 Return : u_register_t
1996
1997This is an optional interface that is is invoked after resuming from a low power
1998state and provides the time spent resident in that low power state by the power
1999domain at a particular power domain level. When a CPU wakes up from suspend,
2000all its parent power domain levels are also woken up. The generic PSCI code
2001invokes this function for each parent power domain that is resumed and it
2002identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2003argument) describes the low power state that the power domain has resumed from.
2004The current CPU is the first CPU in the power domain to resume from the low
2005power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2006CPU in the power domain to suspend and may be needed to calculate the residency
2007for that power domain.
2008
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002009Function : plat_get_target_pwr_state() [optional]
2010~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002011
2012::
2013
2014 Argument : unsigned int, const plat_local_state_t *, unsigned int
2015 Return : plat_local_state_t
2016
2017The PSCI generic code uses this function to let the platform participate in
2018state coordination during a power management operation. The function is passed
2019a pointer to an array of platform specific local power state ``states`` (second
2020argument) which contains the requested power state for each CPU at a particular
2021power domain level ``lvl`` (first argument) within the power domain. The function
2022is expected to traverse this array of upto ``ncpus`` (third argument) and return
2023a coordinated target power state by the comparing all the requested power
2024states. The target power state should not be deeper than any of the requested
2025power states.
2026
2027A weak definition of this API is provided by default wherein it assumes
2028that the platform assigns a local state value in order of increasing depth
2029of the power state i.e. for two power states X & Y, if X < Y
2030then X represents a shallower power state than Y. As a result, the
2031coordinated target local power state for a power domain will be the minimum
2032of the requested local power state values.
2033
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002034Function : plat_get_power_domain_tree_desc() [mandatory]
2035~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002036
2037::
2038
2039 Argument : void
2040 Return : const unsigned char *
2041
2042This function returns a pointer to the byte array containing the power domain
2043topology tree description. The format and method to construct this array are
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002044described in `Power Domain Topology Design`_. The BL31 PSCI initialization code
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002045requires this array to be described by the platform, either statically or
2046dynamically, to initialize the power domain topology tree. In case the array
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002047is populated dynamically, then plat_core_pos_by_mpidr() and
2048plat_my_core_pos() should also be implemented suitably so that the topology
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002049tree description matches the CPU indices returned by these APIs. These APIs
2050together form the platform interface for the PSCI topology framework.
2051
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002052Function : plat_setup_psci_ops() [mandatory]
2053~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002054
2055::
2056
2057 Argument : uintptr_t, const plat_psci_ops **
2058 Return : int
2059
2060This function may execute with the MMU and data caches enabled if the platform
2061port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2062called by the primary CPU.
2063
2064This function is called by PSCI initialization code. Its purpose is to let
2065the platform layer know about the warm boot entrypoint through the
2066``sec_entrypoint`` (first argument) and to export handler routines for
2067platform-specific psci power management actions by populating the passed
2068pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2069
2070A description of each member of this structure is given below. Please refer to
Dan Handley610e7e12018-03-01 18:44:00 +00002071the Arm FVP specific implementation of these handlers in
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002072`plat/arm/board/fvp/fvp_pm.c`_ as an example. For each PSCI function that the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002073platform wants to support, the associated operation or operations in this
2074structure must be provided and implemented (Refer section 4 of
Dan Handley610e7e12018-03-01 18:44:00 +00002075`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI
2076function in a platform port, the operation should be removed from this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002077structure instead of providing an empty implementation.
2078
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002079plat_psci_ops.cpu_standby()
2080...........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002081
2082Perform the platform-specific actions to enter the standby state for a cpu
2083indicated by the passed argument. This provides a fast path for CPU standby
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002084wherein overheads of PSCI state management and lock acquisition is avoided.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002085For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2086the suspend state type specified in the ``power-state`` parameter should be
2087STANDBY and the target power domain level specified should be the CPU. The
2088handler should put the CPU into a low power retention state (usually by
2089issuing a wfi instruction) and ensure that it can be woken up from that
2090state by a normal interrupt. The generic code expects the handler to succeed.
2091
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002092plat_psci_ops.pwr_domain_on()
2093.............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002094
2095Perform the platform specific actions to power on a CPU, specified
2096by the ``MPIDR`` (first argument). The generic code expects the platform to
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002097return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002098
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002099plat_psci_ops.pwr_domain_off()
2100..............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002101
2102Perform the platform specific actions to prepare to power off the calling CPU
2103and its higher parent power domain levels as indicated by the ``target_state``
2104(first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2105
2106The ``target_state`` encodes the platform coordinated target local power states
2107for the CPU power domain and its parent power domain levels. The handler
2108needs to perform power management operation corresponding to the local state
2109at each power level.
2110
2111For this handler, the local power state for the CPU power domain will be a
2112power down state where as it could be either power down, retention or run state
2113for the higher power domain levels depending on the result of state
2114coordination. The generic code expects the handler to succeed.
2115
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002116plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2117...........................................................
Varun Wadekarae87f4b2017-07-10 16:02:05 -07002118
2119This optional function may be used as a performance optimization to replace
2120or complement pwr_domain_suspend() on some platforms. Its calling semantics
2121are identical to pwr_domain_suspend(), except the PSCI implementation only
2122calls this function when suspending to a power down state, and it guarantees
2123that data caches are enabled.
2124
2125When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2126before calling pwr_domain_suspend(). If the target_state corresponds to a
2127power down state and it is safe to perform some or all of the platform
2128specific actions in that function with data caches enabled, it may be more
2129efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2130= 1, data caches remain enabled throughout, and so there is no advantage to
2131moving platform specific actions to this function.
2132
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002133plat_psci_ops.pwr_domain_suspend()
2134..................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002135
2136Perform the platform specific actions to prepare to suspend the calling
2137CPU and its higher parent power domain levels as indicated by the
2138``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2139API implementation.
2140
2141The ``target_state`` has a similar meaning as described in
2142the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2143target local power states for the CPU power domain and its parent
2144power domain levels. The handler needs to perform power management operation
2145corresponding to the local state at each power level. The generic code
2146expects the handler to succeed.
2147
Douglas Raillarda84996b2017-08-02 16:57:32 +01002148The difference between turning a power domain off versus suspending it is that
2149in the former case, the power domain is expected to re-initialize its state
2150when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2151case, the power domain is expected to save enough state so that it can resume
2152execution by restoring this state when its powered on (see
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002153``pwr_domain_suspend_finish()``).
2154
Douglas Raillarda84996b2017-08-02 16:57:32 +01002155When suspending a core, the platform can also choose to power off the GICv3
2156Redistributor and ITS through an implementation-defined sequence. To achieve
2157this safely, the ITS context must be saved first. The architectural part is
2158implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2159sequence is implementation defined and it is therefore the responsibility of
2160the platform code to implement the necessary sequence. Then the GIC
2161Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2162Powering off the Redistributor requires the implementation to support it and it
2163is the responsibility of the platform code to execute the right implementation
2164defined sequence.
2165
2166When a system suspend is requested, the platform can also make use of the
2167``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2168it has saved the context of the Redistributors and ITS of all the cores in the
2169system. The context of the Distributor can be large and may require it to be
2170allocated in a special area if it cannot fit in the platform's global static
2171data, for example in DRAM. The Distributor can then be powered down using an
2172implementation-defined sequence.
2173
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002174plat_psci_ops.pwr_domain_pwr_down_wfi()
2175.......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002176
2177This is an optional function and, if implemented, is expected to perform
2178platform specific actions including the ``wfi`` invocation which allows the
2179CPU to powerdown. Since this function is invoked outside the PSCI locks,
2180the actions performed in this hook must be local to the CPU or the platform
2181must ensure that races between multiple CPUs cannot occur.
2182
2183The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2184operation and it encodes the platform coordinated target local power states for
2185the CPU power domain and its parent power domain levels. This function must
2186not return back to the caller.
2187
2188If this function is not implemented by the platform, PSCI generic
2189implementation invokes ``psci_power_down_wfi()`` for power down.
2190
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002191plat_psci_ops.pwr_domain_on_finish()
2192....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002193
2194This function is called by the PSCI implementation after the calling CPU is
2195powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2196It performs the platform-specific setup required to initialize enough state for
2197this CPU to enter the normal world and also provide secure runtime firmware
2198services.
2199
2200The ``target_state`` (first argument) is the prior state of the power domains
2201immediately before the CPU was turned on. It indicates which power domains
2202above the CPU might require initialization due to having previously been in
2203low power states. The generic code expects the handler to succeed.
2204
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002205plat_psci_ops.pwr_domain_suspend_finish()
2206.........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002207
2208This function is called by the PSCI implementation after the calling CPU is
2209powered on and released from reset in response to an asynchronous wakeup
2210event, for example a timer interrupt that was programmed by the CPU during the
2211``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2212setup required to restore the saved state for this CPU to resume execution
2213in the normal world and also provide secure runtime firmware services.
2214
2215The ``target_state`` (first argument) has a similar meaning as described in
2216the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2217to succeed.
2218
Douglas Raillarda84996b2017-08-02 16:57:32 +01002219If the Distributor, Redistributors or ITS have been powered off as part of a
2220suspend, their context must be restored in this function in the reverse order
2221to how they were saved during suspend sequence.
2222
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002223plat_psci_ops.system_off()
2224..........................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002225
2226This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2227call. It performs the platform-specific system poweroff sequence after
2228notifying the Secure Payload Dispatcher.
2229
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002230plat_psci_ops.system_reset()
2231............................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002232
2233This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2234call. It performs the platform-specific system reset sequence after
2235notifying the Secure Payload Dispatcher.
2236
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002237plat_psci_ops.validate_power_state()
2238....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002239
2240This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2241call to validate the ``power_state`` parameter of the PSCI API and if valid,
2242populate it in ``req_state`` (second argument) array as power domain level
2243specific local states. If the ``power_state`` is invalid, the platform must
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002244return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002245normal world PSCI client.
2246
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002247plat_psci_ops.validate_ns_entrypoint()
2248......................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002249
2250This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2251``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2252parameter passed by the normal world. If the ``entry_point`` is invalid,
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002253the platform must return PSCI_E_INVALID_ADDRESS as error, which is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002254propagated back to the normal world PSCI client.
2255
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002256plat_psci_ops.get_sys_suspend_power_state()
2257...........................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002258
2259This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2260call to get the ``req_state`` parameter from platform which encodes the power
2261domain level specific local states to suspend to system affinity level. The
2262``req_state`` will be utilized to do the PSCI state coordination and
2263``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2264enter system suspend.
2265
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002266plat_psci_ops.get_pwr_lvl_state_idx()
2267.....................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002268
2269This is an optional function and, if implemented, is invoked by the PSCI
2270implementation to convert the ``local_state`` (first argument) at a specified
2271``pwr_lvl`` (second argument) to an index between 0 and
2272``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2273supports more than two local power states at each power domain level, that is
2274``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2275local power states.
2276
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002277plat_psci_ops.translate_power_state_by_mpidr()
2278..............................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002279
2280This is an optional function and, if implemented, verifies the ``power_state``
2281(second argument) parameter of the PSCI API corresponding to a target power
2282domain. The target power domain is identified by using both ``MPIDR`` (first
2283argument) and the power domain level encoded in ``power_state``. The power domain
2284level specific local states are to be extracted from ``power_state`` and be
2285populated in the ``output_state`` (third argument) array. The functionality
2286is similar to the ``validate_power_state`` function described above and is
2287envisaged to be used in case the validity of ``power_state`` depend on the
2288targeted power domain. If the ``power_state`` is invalid for the targeted power
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002289domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002290function is not implemented, then the generic implementation relies on
2291``validate_power_state`` function to translate the ``power_state``.
2292
2293This function can also be used in case the platform wants to support local
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002294power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002295APIs as described in Section 5.18 of `PSCI`_.
2296
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002297plat_psci_ops.get_node_hw_state()
2298.................................
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002299
2300This is an optional function. If implemented this function is intended to return
2301the power state of a node (identified by the first parameter, the ``MPIDR``) in
2302the power domain topology (identified by the second parameter, ``power_level``),
2303as retrieved from a power controller or equivalent component on the platform.
2304Upon successful completion, the implementation must map and return the final
2305status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2306must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2307appropriate.
2308
2309Implementations are not expected to handle ``power_levels`` greater than
2310``PLAT_MAX_PWR_LVL``.
2311
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002312plat_psci_ops.system_reset2()
2313.............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002314
2315This is an optional function. If implemented this function is
2316called during the ``SYSTEM_RESET2`` call to perform a reset
2317based on the first parameter ``reset_type`` as specified in
2318`PSCI`_. The parameter ``cookie`` can be used to pass additional
2319reset information. If the ``reset_type`` is not supported, the
2320function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2321resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2322and vendor reset can return other PSCI error codes as defined
2323in `PSCI`_. On success this function will not return.
2324
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002325plat_psci_ops.write_mem_protect()
2326.................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002327
2328This is an optional function. If implemented it enables or disables the
2329``MEM_PROTECT`` functionality based on the value of ``val``.
2330A non-zero value enables ``MEM_PROTECT`` and a value of zero
2331disables it. Upon encountering failures it must return a negative value
2332and on success it must return 0.
2333
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002334plat_psci_ops.read_mem_protect()
2335................................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002336
2337This is an optional function. If implemented it returns the current
2338state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2339failures it must return a negative value and on success it must
2340return 0.
2341
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002342plat_psci_ops.mem_protect_chk()
2343...............................
Roberto Vargasd963e3e2017-09-12 10:28:35 +01002344
2345This is an optional function. If implemented it checks if a memory
2346region defined by a base address ``base`` and with a size of ``length``
2347bytes is protected by ``MEM_PROTECT``. If the region is protected
2348then it must return 0, otherwise it must return a negative number.
2349
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002350Interrupt Management framework (in BL31)
2351----------------------------------------
2352
2353BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
2354generated in either security state and targeted to EL1 or EL2 in the non-secure
2355state or EL3/S-EL1 in the secure state. The design of this framework is
2356described in the `IMF Design Guide`_
2357
2358A platform should export the following APIs to support the IMF. The following
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002359text briefly describes each API and its implementation in Arm standard
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002360platforms. The API implementation depends upon the type of interrupt controller
Dan Handley610e7e12018-03-01 18:44:00 +00002361present in the platform. Arm standard platform layer supports both
2362`Arm Generic Interrupt Controller version 2.0 (GICv2)`_
2363and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
2364FVP can be configured to use either GICv2 or GICv3 depending on the build flag
2365``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in
2366`User Guide`_ for more details).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002367
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002368See also: `Interrupt Controller Abstraction APIs`__.
2369
Paul Beesleyea225122019-02-11 17:54:45 +00002370.. __: ../design/platform-interrupt-controller-API.rst
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002371
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002372Function : plat_interrupt_type_to_line() [mandatory]
2373~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002374
2375::
2376
2377 Argument : uint32_t, uint32_t
2378 Return : uint32_t
2379
Dan Handley610e7e12018-03-01 18:44:00 +00002380The Arm processor signals an interrupt exception either through the IRQ or FIQ
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002381interrupt line. The specific line that is signaled depends on how the interrupt
2382controller (IC) reports different interrupt types from an execution context in
2383either security state. The IMF uses this API to determine which interrupt line
2384the platform IC uses to signal each type of interrupt supported by the framework
2385from a given security state. This API must be invoked at EL3.
2386
2387The first parameter will be one of the ``INTR_TYPE_*`` values (see
2388`IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the
2389security state of the originating execution context. The return result is the
2390bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1,
2391FIQ=2.
2392
Dan Handley610e7e12018-03-01 18:44:00 +00002393In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002394configured as FIQs and Non-secure interrupts as IRQs from either security
2395state.
2396
Dan Handley610e7e12018-03-01 18:44:00 +00002397In the case of Arm standard platforms using GICv3, the interrupt line to be
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002398configured depends on the security state of the execution context when the
2399interrupt is signalled and are as follows:
2400
2401- The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
2402 NS-EL0/1/2 context.
2403- The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
2404 in the NS-EL0/1/2 context.
2405- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
2406 context.
2407
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002408Function : plat_ic_get_pending_interrupt_type() [mandatory]
2409~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002410
2411::
2412
2413 Argument : void
2414 Return : uint32_t
2415
2416This API returns the type of the highest priority pending interrupt at the
2417platform IC. The IMF uses the interrupt type to retrieve the corresponding
2418handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
2419pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
2420``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
2421
Dan Handley610e7e12018-03-01 18:44:00 +00002422In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002423Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
2424the pending interrupt. The type of interrupt depends upon the id value as
2425follows.
2426
2427#. id < 1022 is reported as a S-EL1 interrupt
2428#. id = 1022 is reported as a Non-secure interrupt.
2429#. id = 1023 is reported as an invalid interrupt type.
2430
Dan Handley610e7e12018-03-01 18:44:00 +00002431In the case of Arm standard platforms using GICv3, the system register
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002432``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
2433is read to determine the id of the pending interrupt. The type of interrupt
2434depends upon the id value as follows.
2435
2436#. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
2437#. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
2438#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
2439#. All other interrupt id's are reported as EL3 interrupt.
2440
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002441Function : plat_ic_get_pending_interrupt_id() [mandatory]
2442~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002443
2444::
2445
2446 Argument : void
2447 Return : uint32_t
2448
2449This API returns the id of the highest priority pending interrupt at the
2450platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
2451pending.
2452
Dan Handley610e7e12018-03-01 18:44:00 +00002453In the case of Arm standard platforms using GICv2, the *Highest Priority
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002454Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
2455pending interrupt. The id that is returned by API depends upon the value of
2456the id read from the interrupt controller as follows.
2457
2458#. id < 1022. id is returned as is.
2459#. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
2460 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
2461 This id is returned by the API.
2462#. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
2463
Dan Handley610e7e12018-03-01 18:44:00 +00002464In the case of Arm standard platforms using GICv3, if the API is invoked from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002465EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
2466group 0 Register*, is read to determine the id of the pending interrupt. The id
2467that is returned by API depends upon the value of the id read from the
2468interrupt controller as follows.
2469
2470#. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
2471#. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
2472 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
2473 Register* is read to determine the id of the group 1 interrupt. This id
2474 is returned by the API as long as it is a valid interrupt id
2475#. If the id is any of the special interrupt identifiers,
2476 ``INTR_ID_UNAVAILABLE`` is returned.
2477
2478When the API invoked from S-EL1 for GICv3 systems, the id read from system
2479register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002480Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002481``INTR_ID_UNAVAILABLE`` is returned.
2482
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002483Function : plat_ic_acknowledge_interrupt() [mandatory]
2484~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002485
2486::
2487
2488 Argument : void
2489 Return : uint32_t
2490
2491This API is used by the CPU to indicate to the platform IC that processing of
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002492the highest pending interrupt has begun. It should return the raw, unmodified
2493value obtained from the interrupt controller when acknowledging an interrupt.
2494The actual interrupt number shall be extracted from this raw value using the API
2495`plat_ic_get_interrupt_id()`__.
2496
Paul Beesleyea225122019-02-11 17:54:45 +00002497.. __: ../design/platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002498
Dan Handley610e7e12018-03-01 18:44:00 +00002499This function in Arm standard platforms using GICv2, reads the *Interrupt
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002500Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
2501priority pending interrupt from pending to active in the interrupt controller.
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002502It returns the value read from the ``GICC_IAR``, unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002503
Dan Handley610e7e12018-03-01 18:44:00 +00002504In the case of Arm standard platforms using GICv3, if the API is invoked
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002505from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
2506Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
2507reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
2508group 1*. The read changes the state of the highest pending interrupt from
2509pending to active in the interrupt controller. The value read is returned
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +01002510unmodified.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002511
2512The TSP uses this API to start processing of the secure physical timer
2513interrupt.
2514
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002515Function : plat_ic_end_of_interrupt() [mandatory]
2516~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002517
2518::
2519
2520 Argument : uint32_t
2521 Return : void
2522
2523This API is used by the CPU to indicate to the platform IC that processing of
2524the interrupt corresponding to the id (passed as the parameter) has
2525finished. The id should be the same as the id returned by the
2526``plat_ic_acknowledge_interrupt()`` API.
2527
Dan Handley610e7e12018-03-01 18:44:00 +00002528Arm standard platforms write the id to the *End of Interrupt Register*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002529(``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
2530system register in case of GICv3 depending on where the API is invoked from,
2531EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
2532controller.
2533
2534The TSP uses this API to finish processing of the secure physical timer
2535interrupt.
2536
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002537Function : plat_ic_get_interrupt_type() [mandatory]
2538~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002539
2540::
2541
2542 Argument : uint32_t
2543 Return : uint32_t
2544
2545This API returns the type of the interrupt id passed as the parameter.
2546``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
2547interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
2548returned depending upon how the interrupt has been configured by the platform
2549IC. This API must be invoked at EL3.
2550
Dan Handley610e7e12018-03-01 18:44:00 +00002551Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002552and Non-secure interrupts as Group1 interrupts. It reads the group value
2553corresponding to the interrupt id from the relevant *Interrupt Group Register*
2554(``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
2555
Dan Handley610e7e12018-03-01 18:44:00 +00002556In the case of Arm standard platforms using GICv3, both the *Interrupt Group
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002557Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
2558(``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
2559as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
2560
2561Crash Reporting mechanism (in BL31)
2562-----------------------------------
2563
2564BL31 implements a crash reporting mechanism which prints the various registers
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002565of the CPU to enable quick crash analysis and debugging. This mechanism relies
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002566on the platform implementing ``plat_crash_console_init``,
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002567``plat_crash_console_putc`` and ``plat_crash_console_flush``.
2568
2569The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
2570implementation of all of them. Platforms may include this file to their
2571makefiles in order to benefit from them. By default, they will cause the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002572output to be routed over the normal console infrastructure and get printed on
2573consoles configured to output in crash state. ``console_set_scope()`` can be
2574used to control whether a console is used for crash output.
Paul Beesleyba3ed402019-03-13 16:20:44 +00002575
2576.. note::
2577 Platforms are responsible for making sure that they only mark consoles for
2578 use in the crash scope that are able to support this, i.e. that are written
2579 in assembly and conform with the register clobber rules for putc()
2580 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002581
Julius Werneraae9bb12017-09-18 16:49:48 -07002582In some cases (such as debugging very early crashes that happen before the
2583normal boot console can be set up), platforms may want to control crash output
Julius Werner1338c9c2018-11-19 14:25:55 -08002584more explicitly. These platforms may instead provide custom implementations for
2585these. They are executed outside of a C environment and without a stack. Many
2586console drivers provide functions named ``console_xxx_core_init/putc/flush``
2587that are designed to be used by these functions. See Arm platforms (like juno)
2588for an example of this.
Antonio Nino Diaz4bac0452018-10-16 14:32:34 +01002589
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002590Function : plat_crash_console_init [mandatory]
2591~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002592
2593::
2594
2595 Argument : void
2596 Return : int
2597
2598This API is used by the crash reporting mechanism to initialize the crash
Julius Werneraae9bb12017-09-18 16:49:48 -07002599console. It must only use the general purpose registers x0 through x7 to do the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002600initialization and returns 1 on success.
2601
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002602Function : plat_crash_console_putc [mandatory]
2603~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002604
2605::
2606
2607 Argument : int
2608 Return : int
2609
2610This API is used by the crash reporting mechanism to print a character on the
2611designated crash console. It must only use general purpose registers x1 and
2612x2 to do its work. The parameter and the return value are in general purpose
2613register x0.
2614
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002615Function : plat_crash_console_flush [mandatory]
2616~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002617
2618::
2619
2620 Argument : void
2621 Return : int
2622
2623This API is used by the crash reporting mechanism to force write of all buffered
2624data on the designated crash console. It should only use general purpose
Julius Werneraae9bb12017-09-18 16:49:48 -07002625registers x0 through x5 to do its work. The return value is 0 on successful
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002626completion; otherwise the return value is -1.
2627
Jeenu Viswambharane34bf582018-10-12 08:48:36 +01002628External Abort handling and RAS Support
2629---------------------------------------
Jeenu Viswambharanbf235bc2018-07-12 10:00:01 +01002630
2631Function : plat_ea_handler
2632~~~~~~~~~~~~~~~~~~~~~~~~~~
2633
2634::
2635
2636 Argument : int
2637 Argument : uint64_t
2638 Argument : void *
2639 Argument : void *
2640 Argument : uint64_t
2641 Return : void
2642
2643This function is invoked by the RAS framework for the platform to handle an
2644External Abort received at EL3. The intention of the function is to attempt to
2645resolve the cause of External Abort and return; if that's not possible, to
2646initiate orderly shutdown of the system.
2647
2648The first parameter (``int ea_reason``) indicates the reason for External Abort.
2649Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
2650
2651The second parameter (``uint64_t syndrome``) is the respective syndrome
2652presented to EL3 after having received the External Abort. Depending on the
2653nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
2654can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
2655
2656The third parameter (``void *cookie``) is unused for now. The fourth parameter
2657(``void *handle``) is a pointer to the preempted context. The fifth parameter
2658(``uint64_t flags``) indicates the preempted security state. These parameters
2659are received from the top-level exception handler.
2660
2661If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
2662function iterates through RAS handlers registered by the platform. If any of the
2663RAS handlers resolve the External Abort, no further action is taken.
2664
2665If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
2666could resolve the External Abort, the default implementation prints an error
2667message, and panics.
2668
2669Function : plat_handle_uncontainable_ea
2670~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2671
2672::
2673
2674 Argument : int
2675 Argument : uint64_t
2676 Return : void
2677
2678This function is invoked by the RAS framework when an External Abort of
2679Uncontainable type is received at EL3. Due to the critical nature of
2680Uncontainable errors, the intention of this function is to initiate orderly
2681shutdown of the system, and is not expected to return.
2682
2683This function must be implemented in assembly.
2684
2685The first and second parameters are the same as that of ``plat_ea_handler``.
2686
2687The default implementation of this function calls
2688``report_unhandled_exception``.
2689
2690Function : plat_handle_double_fault
2691~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2692
2693::
2694
2695 Argument : int
2696 Argument : uint64_t
2697 Return : void
2698
2699This function is invoked by the RAS framework when another External Abort is
2700received at EL3 while one is already being handled. I.e., a call to
2701``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
2702this function is to initiate orderly shutdown of the system, and is not expected
2703recover or return.
2704
2705This function must be implemented in assembly.
2706
2707The first and second parameters are the same as that of ``plat_ea_handler``.
2708
2709The default implementation of this function calls
2710``report_unhandled_exception``.
2711
2712Function : plat_handle_el3_ea
2713~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2714
2715::
2716
2717 Return : void
2718
2719This function is invoked when an External Abort is received while executing in
2720EL3. Due to its critical nature, the intention of this function is to initiate
2721orderly shutdown of the system, and is not expected recover or return.
2722
2723This function must be implemented in assembly.
2724
2725The default implementation of this function calls
2726``report_unhandled_exception``.
2727
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002728Build flags
2729-----------
2730
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002731There are some build flags which can be defined by the platform to control
2732inclusion or exclusion of certain BL stages from the FIP image. These flags
2733need to be defined in the platform makefile which will get included by the
2734build system.
2735
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002736- **NEED_BL33**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002737 By default, this flag is defined ``yes`` by the build system and ``BL33``
2738 build option should be supplied as a build option. The platform has the
2739 option of excluding the BL33 image in the ``fip`` image by defining this flag
2740 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
2741 are used, this flag will be set to ``no`` automatically.
2742
2743C Library
2744---------
2745
2746To avoid subtle toolchain behavioral dependencies, the header files provided
2747by the compiler are not used. The software is built with the ``-nostdinc`` flag
2748to ensure no headers are included from the toolchain inadvertently. Instead the
Dan Handley610e7e12018-03-01 18:44:00 +00002749required headers are included in the TF-A source tree. The library only
2750contains those C library definitions required by the local implementation. If
2751more functionality is required, the needed library functions will need to be
2752added to the local implementation.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002753
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01002754Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
2755been written specifically for TF-A. Fome implementation files have been obtained
2756from `FreeBSD`_, others have been written specifically for TF-A as well. The
2757files can be found in ``include/lib/libc`` and ``lib/libc``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002758
Sandrine Bailleux6f0ecd72019-02-08 14:46:42 +01002759SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
2760can be obtained from http://github.com/freebsd/freebsd.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002761
2762Storage abstraction layer
2763-------------------------
2764
2765In order to improve platform independence and portability an storage abstraction
2766layer is used to load data from non-volatile platform storage.
2767
2768Each platform should register devices and their drivers via the Storage layer.
2769These drivers then need to be initialized by bootloader phases as
2770required in their respective ``blx_platform_setup()`` functions. Currently
2771storage access is only required by BL1 and BL2 phases. The ``load_image()``
2772function uses the storage layer to access non-volatile platform storage.
2773
Dan Handley610e7e12018-03-01 18:44:00 +00002774It is mandatory to implement at least one storage driver. For the Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002775development platforms the Firmware Image Package (FIP) driver is provided as
2776the default means to load data from storage (see the "Firmware Image Package"
2777section in the `User Guide`_). The storage layer is described in the header file
2778``include/drivers/io/io_storage.h``. The implementation of the common library
2779is in ``drivers/io/io_storage.c`` and the driver files are located in
2780``drivers/io/``.
2781
2782Each IO driver must provide ``io_dev_*`` structures, as described in
2783``drivers/io/io_driver.h``. These are returned via a mandatory registration
2784function that is called on platform initialization. The semi-hosting driver
2785implementation in ``io_semihosting.c`` can be used as an example.
2786
2787The Storage layer provides mechanisms to initialize storage devices before
2788IO operations are called. The basic operations supported by the layer
2789include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
2790Drivers do not have to implement all operations, but each platform must
2791provide at least one driver for a device capable of supporting generic
2792operations such as loading a bootloader image.
2793
2794The current implementation only allows for known images to be loaded by the
2795firmware. These images are specified by using their identifiers, as defined in
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00002796``include/plat/common/common_def.h`` (or a separate header file included from
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002797there). The platform layer (``plat_get_image_source()``) then returns a reference
2798to a device and a driver-specific ``spec`` which will be understood by the driver
2799to allow access to the image data.
2800
2801The layer is designed in such a way that is it possible to chain drivers with
2802other drivers. For example, file-system drivers may be implemented on top of
2803physical block devices, both represented by IO devices with corresponding
2804drivers. In such a case, the file-system "binding" with the block device may
2805be deferred until the file-system device is initialised.
2806
2807The abstraction currently depends on structures being statically allocated
2808by the drivers and callers, as the system does not yet provide a means of
2809dynamically allocating memory. This may also have the affect of limiting the
2810amount of open resources per driver.
2811
2812--------------
2813
Antonio Nino Diaz645feb42019-02-13 14:07:38 +00002814*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002815
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002816.. _include/plat/common/platform.h: ../include/plat/common/platform.h
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002817.. _include/plat/arm/common/plat_arm.h: ../include/plat/arm/common/plat_arm.h%5D
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002818.. _User Guide: user-guide.rst
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002819.. _include/plat/common/common_def.h: ../include/plat/common/common_def.h
2820.. _include/plat/arm/common/arm_def.h: ../include/plat/arm/common/arm_def.h
2821.. _plat/common/aarch64/platform_mp_stack.S: ../plat/common/aarch64/platform_mp_stack.S
2822.. _plat/common/aarch64/platform_up_stack.S: ../plat/common/aarch64/platform_up_stack.S
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002823.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002824.. _Power Domain Topology Design: ../design/psci-pd-tree.rst
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002825.. _include/common/bl_common.h: ../include/common/bl_common.h
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002826.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002827.. _Firmware Design: ../design/firmware-design.rst
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002828.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
Sandrine Bailleux8d1a0552019-02-08 14:44:53 +01002829.. _plat/arm/board/fvp/fvp_pm.c: ../plat/arm/board/fvp/fvp_pm.c
John Tsichritzis2fd3d922019-05-28 13:13:39 +01002830.. _Platform compatibility policy: ../process/platform-compatibility-policy.rst
2831.. _IMF Design Guide: ../design/interrupt-framework-design.rst
Dan Handley610e7e12018-03-01 18:44:00 +00002832.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002833.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
Paul Beesley2437ddc2019-02-08 16:43:05 +00002834.. _FreeBSD: https://www.freebsd.org
Antonio Nino Diazcf0f8052018-08-17 10:45:47 +01002835.. _SCC: http://www.simple-cc.org/