fdts/morello-soc.dts

/*
 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/dts-v1/;
#include "morello.dtsi"
#include "morello-coresight.dtsi"

/ {
	model = "Arm Morello System Development Platform";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure-firmware@ff000000 {
			reg = <0 0xff000000 0 0x01000000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;
		cpu0: cpu0@0 {
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_dvfs 0>;
		};
		cpu1: cpu1@100 {
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_dvfs 0>;
		};
		cpu2: cpu2@10000 {
			compatible = "arm,armv8";
			reg = <0x0 0x10000>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_dvfs 1>;
		};
		cpu3: cpu3@10100 {
			compatible = "arm,armv8";
			reg = <0x0 0x10100>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_dvfs 1>;
		};
	};

	/* The first bank of memory, memory map is actually provided by UEFI. */
	memory@80000000 {
		device_type = "memory";
		/* [0x80000000-0xffffffff] */
		reg = <0x00000000 0x80000000 0x0 0x7F000000>;
	};

	memory@8080000000 {
		device_type = "memory";
		/* [0x8080000000-0x83f7ffffff] */
		reg = <0x00000080 0x80000000 0x3 0x78000000>;
	};

	smmu_pcie: iommu@4f400000 {
		compatible = "arm,smmu-v3";
		reg = <0 0x4f400000 0 0x40000>;
		interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
		msi-parent = <&its2 0>;
		#iommu-cells = <1>;
		dma-coherent;
	};

	pcie_ctlr: pcie@28c0000000 {
		compatible = "pci-host-ecam-generic";
		device_type = "pci";
		reg = <0x28 0xC0000000 0 0x10000000>;
		bus-range = <0 255>;
		linux,pci-domain = <0>;
		#address-cells = <3>;
		#size-cells = <2>;
		dma-coherent;
		ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>,
		     <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>,
			 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
			<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
			<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
			<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
		msi-map = <0 &its_pcie 0 0x10000>;
		iommu-map = <0 &smmu_pcie 0 0x10000>;
		status = "okay";
	};

	smmu_ccix: iommu@4f000000 {
		compatible = "arm,smmu-v3";
		reg = <0 0x4f000000 0 0x40000>;
		interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
		msi-parent = <&its1 0>;
		#iommu-cells = <1>;
		dma-coherent;
	};

	ccix_pcie_ctlr: pcie@4fc0000000 {
		compatible = "pci-host-ecam-generic";
		device_type = "pci";
		reg = <0x4F 0xC0000000 0 0x10000000>;
		bus-range = <0 255>;
		linux,pci-domain = <1>;
		#address-cells = <3>;
		#size-cells = <2>;
		dma-coherent;
		ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>,
		     <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>,
			 <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
			<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
			<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
			<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
		msi-map = <0 &its_ccix 0 0x10000>;
		iommu-map = <0 &smmu_ccix 0 0x10000>;
		status = "okay";
	};

	smmu_dp: iommu@2ce00000 {
		compatible = "arm,smmu-v3";
		reg = <0 0x2ce00000 0 0x40000>;
		interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "eventq", "gerror", "cmdq-sync";
		#iommu-cells = <1>;
	};

	dp0: display@2cc00000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "arm,mali-d32", "arm,mali-d71";
		reg = <0 0x2cc00000 0 0x20000>;
		interrupts = <0 69 4>;
		interrupt-names = "DPU";
		clocks = <&dpu_aclk>;
		clock-names = "aclk";
		iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
			<&smmu_dp 8>;

		pl0: pipeline@0 {
			reg = <0>;
			clocks = <&scmi_clk 1>;
			clock-names = "pxclk";
			pl_id = <0>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				port@0 {
					reg = <0>;
					dp_pl0_out0: endpoint {
						remote-endpoint = <&tda998x_0_input>;
					};
				};
			};
		};
	};

	i2c@1c0f0000 {
		compatible = "cdns,i2c-r1p14";
		reg = <0x0 0x1c0f0000 0x0 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-frequency = <100000>;
		i2c-sda-hold-time-ns = <500>;
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dpu_aclk>;

		hdmi-transmitter@70 {
			compatible = "nxp,tda998x";
			reg = <0x70>;
			video-ports = <0x234501>;
			port {
				tda998x_0_input: endpoint {
					remote-endpoint = <&dp_pl0_out0>;
				};
			};
		};
	};

	dpu_aclk: dpu_aclk {
		/* 77.1 MHz derived from 24 MHz reference clock */
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <350000000>;
		clock-output-names = "aclk";
	};

	gpu@2d000000 {
		compatible = "arm,mali-bifrost";
		reg = <0x0 0x2d000000 0x0 0x4000>;
		interrupts =
			<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names =
			"gpu",
			"job",
			"mmu";
		clocks = <&clk_gpu>;
		clock-names = "clk_mali";
		status = "okay";
	};

	clk_gpu: clk_gpu {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <650000000>;
		clock-output-names = "clk_mali";
	};

	firmware {
		scmi {
			compatible = "arm,scmi";
			mbox-names = "tx", "rx";
			mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
			shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
			#address-cells = <1>;
			#size-cells = <0>;
			scmi_dvfs: protocol@13 {
				reg = <0x13>;
				#clock-cells = <1>;
			};
			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};
		};
	};
};

&gic {
	reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

	its1: msi-controller@30040000 {
		compatible = "arm,gic-v3-its";
		msi-controller;
		#msi-cells = <1>;
		reg = <0x0 0x30040000 0x0 0x20000>;
	};

	its2: msi-controller@30060000 {
		compatible = "arm,gic-v3-its";
		msi-controller;
		#msi-cells = <1>;
		reg = <0x0 0x30060000 0x0 0x20000>;
	};

	its_ccix: msi-controller@30080000 {
		compatible = "arm,gic-v3-its";
		msi-controller;
		#msi-cells = <1>;
		reg = <0x0 0x30080000 0x0 0x20000>;
	};

	its_pcie: msi-controller@300a0000 {
		compatible = "arm,gic-v3-its";
		msi-controller;
		#msi-cells = <1>;
		reg = <0x0 0x300a0000 0x0 0x20000>;
	};
};