fix(morello): dts: fix DP SMMU IRQ ordering
The official SMMUv3 DT bindings require a certain order of the
interrupts, Linux' "make dtbs_check" reports:
============
.../morello-soc.dt.yaml: iommu@2ce00000: interrupt-names: 'oneOf' conditional failed, one must be fixed:
['eventq', 'cmdq-sync', 'gerror'] is too long
'combined' was expected
'gerror' was expected
'priq' was expected
'cmdq-sync' was expected
From schema: Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
============
Swap the order of the interrupts to improve bindings compliance.
Actually in this case the binding needs to be extended, since PRI is not
implemented in the SMMU in this case, so the PRI IRQ should be optional,
but we still want to describe the CMDQ sync IRQ. A patch for the binding
is pending.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I3978f1c087136cd4c2e8f7fd4d1bba5b95f72726
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index 64742f1..d80ee41 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -151,9 +151,9 @@
compatible = "arm,smmu-v3";
reg = <0 0x2ce00000 0 0x40000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "eventq", "cmdq-sync", "gerror";
+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror", "cmdq-sync";
#iommu-cells = <1>;
};