blob: 846463412b53f28d028f5294b90dbb4376ea17a4 [file] [log] [blame]
Manoj Kumar99529702021-09-15 12:42:49 +05301/*
2 * Copyright (c) 2021, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8#include "morello.dtsi"
9
10/ {
11
12 chosen {
13 stdout-path = "soc_uart0:115200n8";
14 };
15
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges;
20
21 secure-firmware@ff000000 {
22 reg = <0 0xff000000 0 0x01000000>;
23 no-map;
24 };
25 };
26
27 cpus {
28 #address-cells = <2>;
29 #size-cells = <0>;
30 cpu0@0 {
31 compatible = "arm,armv8";
32 reg = <0x0 0x0>;
33 device_type = "cpu";
34 enable-method = "psci";
Anurag Koulb7682b42021-12-03 10:16:47 +000035 clocks = <&scmi_dvfs 0>;
Manoj Kumar99529702021-09-15 12:42:49 +053036 };
37 cpu1@100 {
38 compatible = "arm,armv8";
39 reg = <0x0 0x100>;
40 device_type = "cpu";
41 enable-method = "psci";
Anurag Koulb7682b42021-12-03 10:16:47 +000042 clocks = <&scmi_dvfs 0>;
Manoj Kumar99529702021-09-15 12:42:49 +053043 };
44 cpu2@10000 {
45 compatible = "arm,armv8";
46 reg = <0x0 0x10000>;
47 device_type = "cpu";
48 enable-method = "psci";
Anurag Koulb7682b42021-12-03 10:16:47 +000049 clocks = <&scmi_dvfs 1>;
Manoj Kumar99529702021-09-15 12:42:49 +053050 };
51 cpu3@10100 {
52 compatible = "arm,armv8";
53 reg = <0x0 0x10100>;
54 device_type = "cpu";
55 enable-method = "psci";
Anurag Koulb7682b42021-12-03 10:16:47 +000056 clocks = <&scmi_dvfs 1>;
Manoj Kumar99529702021-09-15 12:42:49 +053057 };
58 };
59
60 /* The first bank of memory, memory map is actually provided by UEFI. */
61 memory@80000000 {
62 #address-cells = <2>;
63 #size-cells = <2>;
64 device_type = "memory";
65 /* [0x80000000-0xffffffff] */
66 reg = <0x00000000 0x80000000 0x0 0x7F000000>;
67 };
68
69 memory@8080000000 {
70 #address-cells = <2>;
71 #size-cells = <2>;
72 device_type = "memory";
73 /* [0x8080000000-0x83f7ffffff] */
74 reg = <0x00000080 0x80000000 0x3 0x78000000>;
75 };
76
77 smmu_pcie: iommu@4f400000 {
78 compatible = "arm,smmu-v3";
79 reg = <0 0x4f400000 0 0x40000>;
80 interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
81 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
82 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
83 <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>;
84 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
85 msi-parent = <&its2 0>;
86 #iommu-cells = <1>;
87 dma-coherent;
88 };
89
90 pcie_ctlr: pcie@28c0000000 {
91 compatible = "pci-host-ecam-generic";
92 device_type = "pci";
93 reg = <0x28 0xC0000000 0 0x10000000>;
94 bus-range = <0 255>;
95 linux,pci-domain = <0>;
96 #address-cells = <3>;
97 #size-cells = <2>;
98 dma-coherent;
99 ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>,
100 <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>,
101 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>;
102 #interrupt-cells = <1>;
103 interrupt-map-mask = <0 0 0 7>;
104 interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
105 <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
106 <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
107 <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
108 msi-map = <0 &its_pcie 0 0x10000>;
109 iommu-map = <0 &smmu_pcie 0 0x10000>;
110 status = "okay";
111 };
112
113 smmu_ccix: iommu@4f000000 {
114 compatible = "arm,smmu-v3";
115 reg = <0 0x4f000000 0 0x40000>;
116 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
117 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
118 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
119 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
120 interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
121 msi-parent = <&its1 0>;
122 #iommu-cells = <1>;
123 dma-coherent;
124 };
125
126 ccix_pcie_ctlr: pcie@4fc0000000 {
127 compatible = "pci-host-ecam-generic";
128 device_type = "pci";
129 reg = <0x4F 0xC0000000 0 0x10000000>;
130 bus-range = <0 255>;
131 linux,pci-domain = <1>;
132 #address-cells = <3>;
133 #size-cells = <2>;
134 dma-coherent;
135 ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>,
136 <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>,
137 <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>;
138 #interrupt-cells = <1>;
139 interrupt-map-mask = <0 0 0 7>;
140 interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
144 msi-map = <0 &its_ccix 0 0x10000>;
145 iommu-map = <0 &smmu_ccix 0 0x10000>;
146 status = "okay";
147 };
148
149 smmu_dp: iommu@2ce00000 {
150 compatible = "arm,smmu-v3";
151 reg = <0 0x2ce00000 0 0x40000>;
152 interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
153 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
154 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
155 interrupt-names = "eventq", "cmdq-sync", "gerror";
156 #iommu-cells = <1>;
157 };
158
159 dp0: display@2cc00000 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "arm,mali-d32";
163 reg = <0 0x2cc00000 0 0x20000>;
164 interrupts = <0 69 4>;
165 interrupt-names = "DPU";
166 clocks = <&dpu_aclk>;
167 clock-names = "aclk";
168 iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
169 <&smmu_dp 8>;
170
171 pl0: pipeline@0 {
172 reg = <0>;
Anurag Koulb7682b42021-12-03 10:16:47 +0000173 clocks = <&scmi_clk 1>;
Manoj Kumar99529702021-09-15 12:42:49 +0530174 clock-names = "pxclk";
175 pl_id = <0>;
176 ports {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 port@0 {
180 reg = <0>;
181 dp_pl0_out0: endpoint {
182 remote-endpoint = <&tda998x_0_input>;
183 };
184 };
185 };
186 };
187 };
188
189 i2c@1c0f0000 {
190 compatible = "cdns,i2c-r1p14";
191 reg = <0x0 0x1c0f0000 0x0 0x1000>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 clock-frequency = <100000>;
195 i2c-sda-hold-time-ns = <500>;
196 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&dpu_aclk>;
198
199 hdmi-transmitter@70 {
200 compatible = "nxp,tda998x";
201 reg = <0x70>;
202 video-ports = <0x234501>;
203 port {
204 tda998x_0_input: endpoint {
205 remote-endpoint = <&dp_pl0_out0>;
206 };
207 };
208 };
209 };
210
211 dpu_aclk: dpu_aclk {
212 /* 77.1 MHz derived from 24 MHz reference clock */
213 compatible = "fixed-clock";
214 #clock-cells = <0>;
215 clock-frequency = <350000000>;
216 clock-output-names = "aclk";
217 };
218
Anurag Koulb7682b42021-12-03 10:16:47 +0000219 firmware {
220 scmi {
221 compatible = "arm,scmi";
222 mbox-names = "tx", "rx";
223 mboxes = <&mailbox 1 0 &mailbox 1 1>;
224 shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227 scmi_dvfs: protocol@13 {
228 reg = <0x13>;
229 #clock-cells = <1>;
230 };
231 scmi_clk: protocol@14 {
232 reg = <0x14>;
233 #clock-cells = <1>;
234 };
235 };
Manoj Kumar99529702021-09-15 12:42:49 +0530236 };
237};
238
239&gic {
240 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
241 <0x0 0x300c0000 0 0x80000>; /* GICR */
242 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
243
244 its1: its@30040000 {
245 compatible = "arm,gic-v3-its";
246 msi-controller;
247 #msi-cells = <1>;
248 reg = <0x0 0x30040000 0x0 0x20000>;
249 };
250
251 its2: its@30060000 {
252 compatible = "arm,gic-v3-its";
253 msi-controller;
254 #msi-cells = <1>;
255 reg = <0x0 0x30060000 0x0 0x20000>;
256 };
257
258 its_ccix: its@30080000 {
259 compatible = "arm,gic-v3-its";
260 msi-controller;
261 #msi-cells = <1>;
262 reg = <0x0 0x30080000 0x0 0x20000>;
263 };
264
265 its_pcie: its@300a0000 {
266 compatible = "arm,gic-v3-its";
267 msi-controller;
268 #msi-cells = <1>;
269 reg = <0x0 0x300a0000 0x0 0x20000>;
270 };
271};