blob: 61b57638251fcbd48022e38ea82f057b995eacd9 [file] [log] [blame]
Manoj Kumar99529702021-09-15 12:42:49 +05301/*
Patrik Berglund785c7bc2023-02-20 11:52:39 +00002 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
Manoj Kumar99529702021-09-15 12:42:49 +05303 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/dts-v1/;
8#include "morello.dtsi"
Werner Lewis0d48a312023-04-25 11:29:17 +01009#include "morello-coresight.dtsi"
Manoj Kumar99529702021-09-15 12:42:49 +053010
11/ {
Andre Przywara60b126a2022-03-24 11:55:57 +000012 model = "Arm Morello System Development Platform";
Manoj Kumar99529702021-09-15 12:42:49 +053013
14 chosen {
Andre Przywara48eee8f2022-03-24 16:14:28 +000015 stdout-path = "serial0:115200n8";
Manoj Kumar99529702021-09-15 12:42:49 +053016 };
17
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
21 ranges;
22
23 secure-firmware@ff000000 {
24 reg = <0 0xff000000 0 0x01000000>;
25 no-map;
26 };
27 };
28
29 cpus {
30 #address-cells = <2>;
31 #size-cells = <0>;
Werner Lewis0d48a312023-04-25 11:29:17 +010032 cpu0: cpu0@0 {
Manoj Kumar99529702021-09-15 12:42:49 +053033 compatible = "arm,armv8";
34 reg = <0x0 0x0>;
35 device_type = "cpu";
36 enable-method = "psci";
Anurag Koulb7682b42021-12-03 10:16:47 +000037 clocks = <&scmi_dvfs 0>;
Manoj Kumar99529702021-09-15 12:42:49 +053038 };
Werner Lewis0d48a312023-04-25 11:29:17 +010039 cpu1: cpu1@100 {
Manoj Kumar99529702021-09-15 12:42:49 +053040 compatible = "arm,armv8";
41 reg = <0x0 0x100>;
42 device_type = "cpu";
43 enable-method = "psci";
Anurag Koulb7682b42021-12-03 10:16:47 +000044 clocks = <&scmi_dvfs 0>;
Manoj Kumar99529702021-09-15 12:42:49 +053045 };
Werner Lewis0d48a312023-04-25 11:29:17 +010046 cpu2: cpu2@10000 {
Manoj Kumar99529702021-09-15 12:42:49 +053047 compatible = "arm,armv8";
48 reg = <0x0 0x10000>;
49 device_type = "cpu";
50 enable-method = "psci";
Anurag Koulb7682b42021-12-03 10:16:47 +000051 clocks = <&scmi_dvfs 1>;
Manoj Kumar99529702021-09-15 12:42:49 +053052 };
Werner Lewis0d48a312023-04-25 11:29:17 +010053 cpu3: cpu3@10100 {
Manoj Kumar99529702021-09-15 12:42:49 +053054 compatible = "arm,armv8";
55 reg = <0x0 0x10100>;
56 device_type = "cpu";
57 enable-method = "psci";
Anurag Koulb7682b42021-12-03 10:16:47 +000058 clocks = <&scmi_dvfs 1>;
Manoj Kumar99529702021-09-15 12:42:49 +053059 };
60 };
61
62 /* The first bank of memory, memory map is actually provided by UEFI. */
63 memory@80000000 {
Manoj Kumar99529702021-09-15 12:42:49 +053064 device_type = "memory";
65 /* [0x80000000-0xffffffff] */
66 reg = <0x00000000 0x80000000 0x0 0x7F000000>;
67 };
68
69 memory@8080000000 {
Manoj Kumar99529702021-09-15 12:42:49 +053070 device_type = "memory";
71 /* [0x8080000000-0x83f7ffffff] */
72 reg = <0x00000080 0x80000000 0x3 0x78000000>;
73 };
74
75 smmu_pcie: iommu@4f400000 {
76 compatible = "arm,smmu-v3";
77 reg = <0 0x4f400000 0 0x40000>;
78 interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
Andre Przywara89d45382022-03-24 11:56:30 +000079 <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
Manoj Kumar99529702021-09-15 12:42:49 +053080 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
Andre Przywara89d45382022-03-24 11:56:30 +000081 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
82 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
Manoj Kumar99529702021-09-15 12:42:49 +053083 msi-parent = <&its2 0>;
84 #iommu-cells = <1>;
85 dma-coherent;
86 };
87
88 pcie_ctlr: pcie@28c0000000 {
89 compatible = "pci-host-ecam-generic";
90 device_type = "pci";
91 reg = <0x28 0xC0000000 0 0x10000000>;
92 bus-range = <0 255>;
93 linux,pci-domain = <0>;
94 #address-cells = <3>;
95 #size-cells = <2>;
96 dma-coherent;
97 ranges = <0x01000000 0x00 0x00000000 0x00 0x6F000000 0x00 0x00800000>,
98 <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0F000000>,
99 <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1F 0xC0000000>;
100 #interrupt-cells = <1>;
101 interrupt-map-mask = <0 0 0 7>;
102 interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
103 <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
104 <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
105 <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
106 msi-map = <0 &its_pcie 0 0x10000>;
107 iommu-map = <0 &smmu_pcie 0 0x10000>;
108 status = "okay";
109 };
110
111 smmu_ccix: iommu@4f000000 {
112 compatible = "arm,smmu-v3";
113 reg = <0 0x4f000000 0 0x40000>;
114 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
Andre Przywara89d45382022-03-24 11:56:30 +0000115 <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
Manoj Kumar99529702021-09-15 12:42:49 +0530116 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
Andre Przywara89d45382022-03-24 11:56:30 +0000117 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
118 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
Manoj Kumar99529702021-09-15 12:42:49 +0530119 msi-parent = <&its1 0>;
120 #iommu-cells = <1>;
121 dma-coherent;
122 };
123
124 ccix_pcie_ctlr: pcie@4fc0000000 {
125 compatible = "pci-host-ecam-generic";
126 device_type = "pci";
127 reg = <0x4F 0xC0000000 0 0x10000000>;
128 bus-range = <0 255>;
129 linux,pci-domain = <1>;
130 #address-cells = <3>;
131 #size-cells = <2>;
132 dma-coherent;
133 ranges = <0x01000000 0x00 0x00000000 0x00 0x7F000000 0x00 0x00800000>,
134 <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0F000000>,
135 <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1F 0xC0000000>;
136 #interrupt-cells = <1>;
137 interrupt-map-mask = <0 0 0 7>;
138 interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
139 <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
142 msi-map = <0 &its_ccix 0 0x10000>;
143 iommu-map = <0 &smmu_ccix 0 0x10000>;
144 status = "okay";
145 };
146
147 smmu_dp: iommu@2ce00000 {
148 compatible = "arm,smmu-v3";
149 reg = <0 0x2ce00000 0 0x40000>;
150 interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
Andre Przywarabe8d7fb2022-03-24 11:57:17 +0000151 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
152 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
153 interrupt-names = "eventq", "gerror", "cmdq-sync";
Manoj Kumar99529702021-09-15 12:42:49 +0530154 #iommu-cells = <1>;
155 };
156
157 dp0: display@2cc00000 {
158 #address-cells = <1>;
159 #size-cells = <0>;
Andre Przywarab473d8c2022-03-24 11:57:37 +0000160 compatible = "arm,mali-d32", "arm,mali-d71";
Manoj Kumar99529702021-09-15 12:42:49 +0530161 reg = <0 0x2cc00000 0 0x20000>;
162 interrupts = <0 69 4>;
163 interrupt-names = "DPU";
164 clocks = <&dpu_aclk>;
165 clock-names = "aclk";
166 iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
167 <&smmu_dp 8>;
168
169 pl0: pipeline@0 {
170 reg = <0>;
Anurag Koulb7682b42021-12-03 10:16:47 +0000171 clocks = <&scmi_clk 1>;
Manoj Kumar99529702021-09-15 12:42:49 +0530172 clock-names = "pxclk";
173 pl_id = <0>;
174 ports {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 port@0 {
178 reg = <0>;
179 dp_pl0_out0: endpoint {
180 remote-endpoint = <&tda998x_0_input>;
181 };
182 };
183 };
184 };
185 };
186
187 i2c@1c0f0000 {
188 compatible = "cdns,i2c-r1p14";
189 reg = <0x0 0x1c0f0000 0x0 0x1000>;
190 #address-cells = <1>;
191 #size-cells = <0>;
192 clock-frequency = <100000>;
193 i2c-sda-hold-time-ns = <500>;
194 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&dpu_aclk>;
196
197 hdmi-transmitter@70 {
198 compatible = "nxp,tda998x";
199 reg = <0x70>;
200 video-ports = <0x234501>;
201 port {
202 tda998x_0_input: endpoint {
203 remote-endpoint = <&dp_pl0_out0>;
204 };
205 };
206 };
207 };
208
209 dpu_aclk: dpu_aclk {
210 /* 77.1 MHz derived from 24 MHz reference clock */
211 compatible = "fixed-clock";
212 #clock-cells = <0>;
213 clock-frequency = <350000000>;
214 clock-output-names = "aclk";
215 };
216
Patrik Berglund785c7bc2023-02-20 11:52:39 +0000217 gpu@2d000000 {
218 compatible = "arm,mali-bifrost";
219 reg = <0x0 0x2d000000 0x0 0x4000>;
220 interrupts =
221 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
224 interrupt-names =
225 "gpu",
226 "job",
227 "mmu";
228 clocks = <&clk_gpu>;
229 clock-names = "clk_mali";
230 status = "okay";
231 };
232
233 clk_gpu: clk_gpu {
234 compatible = "fixed-clock";
235 #clock-cells = <0>;
236 clock-frequency = <650000000>;
237 clock-output-names = "clk_mali";
238 };
239
Anurag Koulb7682b42021-12-03 10:16:47 +0000240 firmware {
241 scmi {
242 compatible = "arm,scmi";
243 mbox-names = "tx", "rx";
Andre Przywara28a21962022-03-24 11:58:10 +0000244 mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
245 shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
Anurag Koulb7682b42021-12-03 10:16:47 +0000246 #address-cells = <1>;
247 #size-cells = <0>;
248 scmi_dvfs: protocol@13 {
249 reg = <0x13>;
250 #clock-cells = <1>;
251 };
252 scmi_clk: protocol@14 {
253 reg = <0x14>;
254 #clock-cells = <1>;
255 };
256 };
Manoj Kumar99529702021-09-15 12:42:49 +0530257 };
258};
259
260&gic {
261 reg = <0x0 0x30000000 0 0x10000>, /* GICD */
262 <0x0 0x300c0000 0 0x80000>; /* GICR */
263 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
264
Andre Przywaraac167722022-03-24 11:58:46 +0000265 its1: msi-controller@30040000 {
Manoj Kumar99529702021-09-15 12:42:49 +0530266 compatible = "arm,gic-v3-its";
267 msi-controller;
268 #msi-cells = <1>;
269 reg = <0x0 0x30040000 0x0 0x20000>;
270 };
271
Andre Przywaraac167722022-03-24 11:58:46 +0000272 its2: msi-controller@30060000 {
Manoj Kumar99529702021-09-15 12:42:49 +0530273 compatible = "arm,gic-v3-its";
274 msi-controller;
275 #msi-cells = <1>;
276 reg = <0x0 0x30060000 0x0 0x20000>;
277 };
278
Andre Przywaraac167722022-03-24 11:58:46 +0000279 its_ccix: msi-controller@30080000 {
Manoj Kumar99529702021-09-15 12:42:49 +0530280 compatible = "arm,gic-v3-its";
281 msi-controller;
282 #msi-cells = <1>;
283 reg = <0x0 0x30080000 0x0 0x20000>;
284 };
285
Andre Przywaraac167722022-03-24 11:58:46 +0000286 its_pcie: msi-controller@300a0000 {
Manoj Kumar99529702021-09-15 12:42:49 +0530287 compatible = "arm,gic-v3-its";
288 msi-controller;
289 #msi-cells = <1>;
290 reg = <0x0 0x300a0000 0x0 0x20000>;
291 };
292};