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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Madhukar Pappireddyfba25722020-07-24 03:27:12 -05002 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Achin Gupta4f6ad662013-10-25 09:08:21 +01009#include <arch.h>
Dan Handley714a0d22014-04-09 13:13:04 +010010#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <bl31/ea_handle.h>
12#include <bl31/interrupt_mgmt.h>
13#include <common/runtime_svc.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <context.h>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010015#include <el3_common_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <lib/el3_runtime/cpu_data.h>
17#include <lib/smccc.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
19 .globl runtime_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
Dimitris Papastamos446f7f12017-11-30 14:53:53 +000021 .globl sync_exception_sp_el0
22 .globl irq_sp_el0
23 .globl fiq_sp_el0
24 .globl serror_sp_el0
25
26 .globl sync_exception_sp_elx
27 .globl irq_sp_elx
28 .globl fiq_sp_elx
29 .globl serror_sp_elx
30
31 .globl sync_exception_aarch64
32 .globl irq_aarch64
33 .globl fiq_aarch64
34 .globl serror_aarch64
35
36 .globl sync_exception_aarch32
37 .globl irq_aarch32
38 .globl fiq_aarch32
39 .globl serror_aarch32
40
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +000041 /*
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010042 * Macro that prepares entry to EL3 upon taking an exception.
43 *
44 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB
45 * instruction. When an error is thus synchronized, the handling is
46 * delegated to platform EA handler.
47 *
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050048 * Without RAS_EXTENSION, this macro synchronizes pending errors using
49 * a DSB, unmasks Asynchronous External Aborts and saves X30 before
50 * setting the flag CTX_IS_IN_EL3.
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010051 */
52 .macro check_and_unmask_ea
53#if RAS_EXTENSION
54 /* Synchronize pending External Aborts */
55 esb
56
57 /* Unmask the SError interrupt */
58 msr daifclr, #DAIF_ABT_BIT
59
60 /*
61 * Explicitly save x30 so as to free up a register and to enable
62 * branching
63 */
64 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
65
66 /* Check for SErrors synchronized by the ESB instruction */
67 mrs x30, DISR_EL1
68 tbz x30, #DISR_A_BIT, 1f
69
Alexei Fedorov503bbf32019-08-13 15:17:53 +010070 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +010071 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
72 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
73 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Alexei Fedorov503bbf32019-08-13 15:17:53 +010074 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +010075 bl save_gp_pmcr_pauth_regs
Alexei Fedorov503bbf32019-08-13 15:17:53 +010076
Jeenu Viswambharane86a2472018-07-05 15:24:45 +010077 bl handle_lower_el_ea_esb
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010078
Alexei Fedorovf41355c2019-09-13 14:11:59 +010079 /* Restore general purpose, PMCR_EL0 and ARMv8.3-PAuth registers */
80 bl restore_gp_pmcr_pauth_regs
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100811:
82#else
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050083 /*
84 * For SoCs which do not implement RAS, use DSB as a barrier to
85 * synchronize pending external aborts.
86 */
87 dsb sy
88
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +010089 /* Unmask the SError interrupt */
90 msr daifclr, #DAIF_ABT_BIT
91
Madhukar Pappireddyfba25722020-07-24 03:27:12 -050092 /* Use ISB for the above unmask operation to take effect immediately */
93 isb
94
95 /*
96 * Refer Note 1. No need to restore X30 as both handle_sync_exception
97 * and handle_interrupt_exception macro which follow this macro modify
98 * X30 anyway.
99 */
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100100 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500101 mov x30, #1
102 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
103 dmb sy
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100104#endif
105 .endm
106
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500107#if !RAS_EXTENSION
108 /*
109 * Note 1: The explicit DSB at the entry of various exception vectors
110 * for handling exceptions from lower ELs can inadvertently trigger an
111 * SError exception in EL3 due to pending asynchronous aborts in lower
112 * ELs. This will end up being handled by serror_sp_elx which will
113 * ultimately panic and die.
114 * The way to workaround is to update a flag to indicate if the exception
115 * truly came from EL3. This flag is allocated in the cpu_context
116 * structure and located at offset "CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3"
117 * This is not a bullet proof solution to the problem at hand because
118 * we assume the instructions following "isb" that help to update the
119 * flag execute without causing further exceptions.
120 */
121
122 /* ---------------------------------------------------------------------
123 * This macro handles Asynchronous External Aborts.
124 * ---------------------------------------------------------------------
125 */
126 .macro handle_async_ea
127 /*
128 * Use a barrier to synchronize pending external aborts.
129 */
130 dsb sy
131
132 /* Unmask the SError interrupt */
133 msr daifclr, #DAIF_ABT_BIT
134
135 /* Use ISB for the above unmask operation to take effect immediately */
136 isb
137
138 /* Refer Note 1 */
139 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
140 mov x30, #1
141 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
142 dmb sy
143
144 b handle_lower_el_async_ea
145 .endm
146
147 /*
148 * This macro checks if the exception was taken due to SError in EL3 or
149 * because of pending asynchronous external aborts from lower EL that got
150 * triggered due to explicit synchronization in EL3. Refer Note 1.
151 */
152 .macro check_if_serror_from_EL3
153 /* Assumes SP_EL3 on entry */
154 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
155 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
156 cbnz x30, exp_from_EL3
157
158 /* Handle asynchronous external abort from lower EL */
159 b handle_lower_el_async_ea
160
161exp_from_EL3:
162 /* Jump to plat_handle_el3_ea which does not return */
163 .endm
164#endif
165
Douglas Raillard0980eed2016-11-09 17:48:27 +0000166 /* ---------------------------------------------------------------------
167 * This macro handles Synchronous exceptions.
168 * Only SMC exceptions are supported.
169 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100170 */
171 .macro handle_sync_exception
dp-arm3cac7862016-09-19 11:18:44 +0100172#if ENABLE_RUNTIME_INSTRUMENTATION
dp-arm3cac7862016-09-19 11:18:44 +0100173 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000174 * Read the timestamp value and store it in per-cpu data. The value
175 * will be extracted from per-cpu data by the C level SMC handler and
176 * saved to the PMF timestamp region.
dp-arm3cac7862016-09-19 11:18:44 +0100177 */
178 mrs x30, cntpct_el0
179 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
180 mrs x29, tpidr_el3
181 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET]
182 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
183#endif
184
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100185 mrs x30, esr_el3
186 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
187
Douglas Raillard0980eed2016-11-09 17:48:27 +0000188 /* Handle SMC exceptions separately from other synchronous exceptions */
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100189 cmp x30, #EC_AARCH32_SMC
190 b.eq smc_handler32
191
192 cmp x30, #EC_AARCH64_SMC
193 b.eq smc_handler64
194
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100195 /* Synchronous exceptions other than the above are assumed to be EA */
Julius Werner67ebde72017-07-27 14:59:34 -0700196 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100197 b enter_lower_el_sync_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100198 .endm
199
200
Douglas Raillard0980eed2016-11-09 17:48:27 +0000201 /* ---------------------------------------------------------------------
202 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS
203 * interrupts.
204 * ---------------------------------------------------------------------
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100205 */
206 .macro handle_interrupt_exception label
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000207
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100208 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100209 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
210 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
211 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100212 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100213 bl save_gp_pmcr_pauth_regs
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100214
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000215#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100216 /* Load and program APIAKey firmware key */
217 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000218#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000219
Douglas Raillard0980eed2016-11-09 17:48:27 +0000220 /* Save the EL3 system registers needed to return from this exception */
Achin Gupta979992e2015-05-13 17:57:18 +0100221 mrs x0, spsr_el3
222 mrs x1, elr_el3
223 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
224
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100225 /* Switch to the runtime stack i.e. SP_EL0 */
226 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
227 mov x20, sp
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100228 msr spsel, #MODE_SP_EL0
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100229 mov sp, x2
230
231 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000232 * Find out whether this is a valid interrupt type.
233 * If the interrupt controller reports a spurious interrupt then return
234 * to where we came from.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100235 */
Dan Handley701fea72014-05-27 16:17:21 +0100236 bl plat_ic_get_pending_interrupt_type
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100237 cmp x0, #INTR_TYPE_INVAL
238 b.eq interrupt_exit_\label
239
240 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000241 * Get the registered handler for this interrupt type.
242 * A NULL return value could be 'cause of the following conditions:
Achin Gupta979992e2015-05-13 17:57:18 +0100243 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000244 * a. An interrupt of a type was routed correctly but a handler for its
245 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100246 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000247 * b. An interrupt of a type was not routed correctly so a handler for
248 * its type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100249 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000250 * c. An interrupt of a type was routed correctly to EL3, but was
251 * deasserted before its pending state could be read. Another
252 * interrupt of a different type pended at the same time and its
253 * type was reported as pending instead. However, a handler for this
254 * type was not registered.
Achin Gupta979992e2015-05-13 17:57:18 +0100255 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000256 * a. and b. can only happen due to a programming error. The
257 * occurrence of c. could be beyond the control of Trusted Firmware.
258 * It makes sense to return from this exception instead of reporting an
259 * error.
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100260 */
261 bl get_interrupt_type_handler
Achin Gupta979992e2015-05-13 17:57:18 +0100262 cbz x0, interrupt_exit_\label
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100263 mov x21, x0
264
265 mov x0, #INTR_ID_UNAVAILABLE
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100266
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100267 /* Set the current security state in the 'flags' parameter */
268 mrs x2, scr_el3
269 ubfx x1, x2, #0, #1
270
271 /* Restore the reference to the 'handle' i.e. SP_EL3 */
272 mov x2, x20
273
Douglas Raillard0980eed2016-11-09 17:48:27 +0000274 /* x3 will point to a cookie (not used now) */
Soby Mathew799f0ab2014-05-27 16:54:31 +0100275 mov x3, xzr
276
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100277 /* Call the interrupt type handler */
278 blr x21
279
280interrupt_exit_\label:
281 /* Return from exception, possibly in a different security state */
282 b el3_exit
283
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100284 .endm
285
286
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100287vector_base runtime_exceptions
288
Douglas Raillard0980eed2016-11-09 17:48:27 +0000289 /* ---------------------------------------------------------------------
290 * Current EL with SP_EL0 : 0x0 - 0x200
291 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100292 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100293vector_entry sync_exception_sp_el0
Justin Chadwell83e04882019-08-20 11:01:52 +0100294#ifdef MONITOR_TRAPS
295 stp x29, x30, [sp, #-16]!
296
297 mrs x30, esr_el3
298 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
299
300 /* Check for BRK */
301 cmp x30, #EC_BRK
302 b.eq brk_handler
303
304 ldp x29, x30, [sp], #16
305#endif /* MONITOR_TRAPS */
306
Douglas Raillard0980eed2016-11-09 17:48:27 +0000307 /* We don't expect any synchronous exceptions from EL3 */
Julius Werner67ebde72017-07-27 14:59:34 -0700308 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100309end_vector_entry sync_exception_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100310
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100311vector_entry irq_sp_el0
Douglas Raillard0980eed2016-11-09 17:48:27 +0000312 /*
313 * EL3 code is non-reentrant. Any asynchronous exception is a serious
314 * error. Loop infinitely.
315 */
Julius Werner67ebde72017-07-27 14:59:34 -0700316 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100317end_vector_entry irq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100318
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100319
320vector_entry fiq_sp_el0
Julius Werner67ebde72017-07-27 14:59:34 -0700321 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100322end_vector_entry fiq_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100323
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100324
325vector_entry serror_sp_el0
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100326 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100327end_vector_entry serror_sp_el0
Achin Gupta4f6ad662013-10-25 09:08:21 +0100328
Douglas Raillard0980eed2016-11-09 17:48:27 +0000329 /* ---------------------------------------------------------------------
330 * Current EL with SP_ELx: 0x200 - 0x400
331 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100332 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100333vector_entry sync_exception_sp_elx
Douglas Raillard0980eed2016-11-09 17:48:27 +0000334 /*
335 * This exception will trigger if anything went wrong during a previous
336 * exception entry or exit or while handling an earlier unexpected
337 * synchronous exception. There is a high probability that SP_EL3 is
338 * corrupted.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000339 */
Julius Werner67ebde72017-07-27 14:59:34 -0700340 b report_unhandled_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100341end_vector_entry sync_exception_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100342
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100343vector_entry irq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700344 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100345end_vector_entry irq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000346
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100347vector_entry fiq_sp_elx
Julius Werner67ebde72017-07-27 14:59:34 -0700348 b report_unhandled_interrupt
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100349end_vector_entry fiq_sp_elx
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000350
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100351vector_entry serror_sp_elx
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500352#if !RAS_EXTENSION
353 check_if_serror_from_EL3
354#endif
Jeenu Viswambharan911fcc92018-07-06 16:50:06 +0100355 no_ret plat_handle_el3_ea
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100356end_vector_entry serror_sp_elx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100357
Douglas Raillard0980eed2016-11-09 17:48:27 +0000358 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100359 * Lower EL using AArch64 : 0x400 - 0x600
Douglas Raillard0980eed2016-11-09 17:48:27 +0000360 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100361 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100362vector_entry sync_exception_aarch64
Douglas Raillard0980eed2016-11-09 17:48:27 +0000363 /*
364 * This exception vector will be the entry point for SMCs and traps
365 * that are unhandled at lower ELs most commonly. SP_EL3 should point
366 * to a valid cpu context where the general purpose and system register
367 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000368 */
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100369 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100370 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000371 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100372end_vector_entry sync_exception_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100373
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100374vector_entry irq_aarch64
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100375 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100376 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100377 handle_interrupt_exception irq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100378end_vector_entry irq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100379
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100380vector_entry fiq_aarch64
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100381 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100382 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100383 handle_interrupt_exception fiq_aarch64
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100384end_vector_entry fiq_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100385
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100386vector_entry serror_aarch64
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100387 apply_at_speculative_wa
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500388#if RAS_EXTENSION
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000389 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100390 b enter_lower_el_async_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500391#else
392 handle_async_ea
393#endif
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100394end_vector_entry serror_aarch64
Achin Gupta4f6ad662013-10-25 09:08:21 +0100395
Douglas Raillard0980eed2016-11-09 17:48:27 +0000396 /* ---------------------------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100397 * Lower EL using AArch32 : 0x600 - 0x800
Douglas Raillard0980eed2016-11-09 17:48:27 +0000398 * ---------------------------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100399 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100400vector_entry sync_exception_aarch32
Douglas Raillard0980eed2016-11-09 17:48:27 +0000401 /*
402 * This exception vector will be the entry point for SMCs and traps
403 * that are unhandled at lower ELs most commonly. SP_EL3 should point
404 * to a valid cpu context where the general purpose and system register
405 * state can be saved.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000406 */
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100407 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100408 check_and_unmask_ea
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000409 handle_sync_exception
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100410end_vector_entry sync_exception_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100411
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100412vector_entry irq_aarch32
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100413 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100414 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100415 handle_interrupt_exception irq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100416end_vector_entry irq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100417
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100418vector_entry fiq_aarch32
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100419 apply_at_speculative_wa
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100420 check_and_unmask_ea
Achin Gupta9cf2bb72014-05-09 11:07:09 +0100421 handle_interrupt_exception fiq_aarch32
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100422end_vector_entry fiq_aarch32
Achin Gupta4f6ad662013-10-25 09:08:21 +0100423
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100424vector_entry serror_aarch32
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100425 apply_at_speculative_wa
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500426#if RAS_EXTENSION
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000427 msr daifclr, #DAIF_ABT_BIT
Jeenu Viswambharane86a2472018-07-05 15:24:45 +0100428 b enter_lower_el_async_ea
Madhukar Pappireddyfba25722020-07-24 03:27:12 -0500429#else
430 handle_async_ea
431#endif
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100432end_vector_entry serror_aarch32
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000433
Justin Chadwell83e04882019-08-20 11:01:52 +0100434#ifdef MONITOR_TRAPS
435 .section .rodata.brk_string, "aS"
436brk_location:
437 .asciz "Error at instruction 0x"
438brk_message:
439 .asciz "Unexpected BRK instruction with value 0x"
440#endif /* MONITOR_TRAPS */
441
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100442 /* ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000443 * The following code handles secure monitor calls.
Douglas Raillard0980eed2016-11-09 17:48:27 +0000444 * Depending upon the execution state from where the SMC has been
445 * invoked, it frees some general purpose registers to perform the
446 * remaining tasks. They involve finding the runtime service handler
447 * that is the target of the SMC & switching to runtime stacks (SP_EL0)
448 * before calling the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000449 *
Douglas Raillard0980eed2016-11-09 17:48:27 +0000450 * Note that x30 has been explicitly saved and can be used here
451 * ---------------------------------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000452 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000453func smc_handler
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000454smc_handler32:
455 /* Check whether aarch32 issued an SMC64 */
456 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited
457
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000458smc_handler64:
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000459 /* NOTE: The code below must preserve x0-x4 */
460
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100461 /*
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100462 * Save general purpose and ARMv8.3-PAuth registers (if enabled).
463 * If Secure Cycle Counter is not disabled in MDCR_EL3 when
464 * ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100465 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100466 bl save_gp_pmcr_pauth_regs
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100467
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000468#if ENABLE_PAUTH
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100469 /* Load and program APIAKey firmware key */
470 bl pauth_load_bl31_apiakey
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000471#endif
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000472
Douglas Raillard0980eed2016-11-09 17:48:27 +0000473 /*
474 * Populate the parameters for the SMC handler.
475 * We already have x0-x4 in place. x5 will point to a cookie (not used
476 * now). x6 will point to the context structure (SP_EL3) and x7 will
Dimitris Papastamos04159512018-01-22 11:53:04 +0000477 * contain flags we need to pass to the handler.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000478 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000479 mov x5, xzr
480 mov x6, sp
481
Douglas Raillard0980eed2016-11-09 17:48:27 +0000482 /*
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100483 * Restore the saved C runtime stack value which will become the new
484 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context'
485 * structure prior to the last ERET from EL3.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000486 */
Antonio Nino Diaz35c8cfc2018-04-23 15:43:29 +0100487 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
488
489 /* Switch to SP_EL0 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100490 msr spsel, #MODE_SP_EL0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000491
Douglas Raillard0980eed2016-11-09 17:48:27 +0000492 /*
493 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world
494 * switch during SMC handling.
495 * TODO: Revisit if all system registers can be saved later.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000496 */
497 mrs x16, spsr_el3
498 mrs x17, elr_el3
499 mrs x18, scr_el3
500 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
Achin Guptae1aa5162014-06-26 09:58:52 +0100501 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000502
503 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
504 bfi x7, x18, #0, #1
505
506 mov sp, x12
507
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500508 /* Get the unique owning entity number */
509 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH
510 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH
511 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH
512
513 /* Load descriptor index from array of indices */
Madhukar Pappireddyf4e6ea62020-01-27 15:32:15 -0600514 adrp x14, rt_svc_descs_indices
515 add x14, x14, :lo12:rt_svc_descs_indices
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500516 ldrb w15, [x14, x16]
517
518 /* Any index greater than 127 is invalid. Check bit 7. */
519 tbnz w15, 7, smc_unknown
520
Douglas Raillard0980eed2016-11-09 17:48:27 +0000521 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500522 * Get the descriptor using the index
523 * x11 = (base + off), w15 = index
524 *
525 * handler = (base + off) + (index << log2(size))
526 */
527 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE)
528 lsl w10, w15, #RT_SVC_SIZE_LOG2
529 ldr x15, [x11, w10, uxtw]
530
531 /*
Douglas Raillard0980eed2016-11-09 17:48:27 +0000532 * Call the Secure Monitor Call handler and then drop directly into
533 * el3_exit() which will program any remaining architectural state
534 * prior to issuing the ERET to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000535 */
536#if DEBUG
537 cbz x15, rt_svc_fw_critical_error
538#endif
539 blr x15
540
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100541 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100542
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000543smc_unknown:
544 /*
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500545 * Unknown SMC call. Populate return value with SMC_UNK and call
546 * el3_exit() which will restore the remaining architectural state
547 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET
548 * to the desired lower EL.
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000549 */
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000550 mov x0, #SMC_UNK
Madhukar Pappireddyd87233a2019-05-08 15:41:41 -0500551 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
552 b el3_exit
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000553
554smc_prohibited:
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100555 restore_ptw_el1_sys_regs
556 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
Soby Mathew6c5192a2014-04-30 15:36:37 +0100557 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Antonio Nino Diaze4794b72018-02-14 14:22:29 +0000558 mov x0, #SMC_UNK
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -0800559 exception_return
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000560
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100561#if DEBUG
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000562rt_svc_fw_critical_error:
Douglas Raillard0980eed2016-11-09 17:48:27 +0000563 /* Switch to SP_ELx */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100564 msr spsel, #MODE_SP_ELX
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000565 no_ret report_unhandled_exception
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100566#endif
Kévin Petita877c252015-03-24 14:03:57 +0000567endfunc smc_handler
Justin Chadwell83e04882019-08-20 11:01:52 +0100568
569 /* ---------------------------------------------------------------------
570 * The following code handles exceptions caused by BRK instructions.
571 * Following a BRK instruction, the only real valid cause of action is
572 * to print some information and panic, as the code that caused it is
573 * likely in an inconsistent internal state.
574 *
575 * This is initially intended to be used in conjunction with
576 * __builtin_trap.
577 * ---------------------------------------------------------------------
578 */
579#ifdef MONITOR_TRAPS
580func brk_handler
581 /* Extract the ISS */
582 mrs x10, esr_el3
583 ubfx x10, x10, #ESR_ISS_SHIFT, #ESR_ISS_LENGTH
584
585 /* Ensure the console is initialized */
586 bl plat_crash_console_init
587
588 adr x4, brk_location
589 bl asm_print_str
590 mrs x4, elr_el3
591 bl asm_print_hex
592 bl asm_print_newline
593
594 adr x4, brk_message
595 bl asm_print_str
596 mov x4, x10
597 mov x5, #28
598 bl asm_print_hex_bits
599 bl asm_print_newline
600
601 no_ret plat_panic_handler
602endfunc brk_handler
603#endif /* MONITOR_TRAPS */