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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Roberto Vargas2ca18d92018-02-12 12:36:17 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
7#ifndef __GICV3_PRIVATE_H__
8#define __GICV3_PRIVATE_H__
9
Soby Mathew327548c2017-07-13 15:19:51 +010010#include <assert.h>
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000011#include <gic_common.h>
Achin Gupta92712a52015-09-03 14:18:02 +010012#include <gicv3.h>
13#include <mmio.h>
14#include <stdint.h>
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000015#include "../common/gic_common_private.h"
Achin Gupta92712a52015-09-03 14:18:02 +010016
17/*******************************************************************************
18 * GICv3 private macro definitions
19 ******************************************************************************/
20
21/* Constants to indicate the status of the RWP bit */
22#define RWP_TRUE 1
23#define RWP_FALSE 0
24
25/*
Achin Gupta92712a52015-09-03 14:18:02 +010026 * Macro to convert an mpidr to a value suitable for programming into a
27 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
28 * to GICv3.
29 */
Daniel Boulbyfef5d2d2018-05-04 14:04:07 +010030#define gicd_irouter_val_from_mpidr(_mpidr, _irm) \
31 ((_mpidr & ~(0xff << 24)) | \
32 (_irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT)
Achin Gupta92712a52015-09-03 14:18:02 +010033
34/*
Achin Gupta92712a52015-09-03 14:18:02 +010035 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
36 * are zeroes.
37 */
Soby Mathewd6452322016-05-05 13:59:07 +010038#ifdef AARCH32
Daniel Boulbyfef5d2d2018-05-04 14:04:07 +010039#define mpidr_from_gicr_typer(_typer_val) (((_typer_val) >> 32) & 0xffffff)
Soby Mathewd6452322016-05-05 13:59:07 +010040#else
Daniel Boulbyfef5d2d2018-05-04 14:04:07 +010041#define mpidr_from_gicr_typer(_typer_val) \
42 (((((_typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
43 (((_typer_val) >> 32) & 0xffffff))
Soby Mathewd6452322016-05-05 13:59:07 +010044#endif
Achin Gupta92712a52015-09-03 14:18:02 +010045
46/*******************************************************************************
Soby Mathew327548c2017-07-13 15:19:51 +010047 * GICv3 private global variables declarations
48 ******************************************************************************/
49extern const gicv3_driver_data_t *gicv3_driver_data;
50
51/*******************************************************************************
Soby Mathew50f6fe42016-02-01 17:59:22 +000052 * Private GICv3 function prototypes for accessing entire registers.
53 * Note: The raw register values correspond to multiple interrupt IDs and
54 * the number of interrupt IDs involved depends on the register accessed.
Achin Gupta92712a52015-09-03 14:18:02 +010055 ******************************************************************************/
56unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id);
57unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id);
Soby Mathew50f6fe42016-02-01 17:59:22 +000058void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val);
59void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
60
61/*******************************************************************************
62 * Private GICv3 function prototypes for accessing the GIC registers
63 * corresponding to a single interrupt ID. These functions use bitwise
64 * operations or appropriate register accesses to modify or return
65 * the bit-field corresponding the single interrupt ID.
66 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +010067unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id);
68unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id);
69unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +010070unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id);
Achin Gupta92712a52015-09-03 14:18:02 +010071void gicd_set_igrpmodr(uintptr_t base, unsigned int id);
72void gicr_set_igrpmodr0(uintptr_t base, unsigned int id);
73void gicr_set_isenabler0(uintptr_t base, unsigned int id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +010074void gicr_set_icenabler0(uintptr_t base, unsigned int id);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +010075void gicr_set_ispendr0(uintptr_t base, unsigned int id);
76void gicr_set_icpendr0(uintptr_t base, unsigned int id);
Achin Gupta92712a52015-09-03 14:18:02 +010077void gicr_set_igroupr0(uintptr_t base, unsigned int id);
78void gicd_clr_igrpmodr(uintptr_t base, unsigned int id);
79void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id);
80void gicr_clr_igroupr0(uintptr_t base, unsigned int id);
Soby Mathew50f6fe42016-02-01 17:59:22 +000081void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri);
Roberto Vargas2ca18d92018-02-12 12:36:17 +000082void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg);
83void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg);
Soby Mathew50f6fe42016-02-01 17:59:22 +000084
85/*******************************************************************************
86 * Private GICv3 helper function prototypes
87 ******************************************************************************/
Daniel Boulby4e83abb2018-05-01 15:15:34 +010088void gicv3_spis_config_defaults(uintptr_t gicd_base);
89void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010090#if !ERROR_DEPRECATED
Daniel Boulby4e83abb2018-05-01 15:15:34 +010091void gicv3_secure_spis_config(uintptr_t gicd_base,
Achin Gupta92712a52015-09-03 14:18:02 +010092 unsigned int num_ints,
93 const unsigned int *sec_intr_list,
94 unsigned int int_grp);
Daniel Boulby4e83abb2018-05-01 15:15:34 +010095void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
Achin Gupta92712a52015-09-03 14:18:02 +010096 unsigned int num_ints,
97 const unsigned int *sec_intr_list,
98 unsigned int int_grp);
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010099#endif
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100100unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100101 const interrupt_prop_t *interrupt_props,
102 unsigned int interrupt_props_num);
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100103unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100104 const interrupt_prop_t *interrupt_props,
105 unsigned int interrupt_props_num);
Achin Gupta92712a52015-09-03 14:18:02 +0100106void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
107 unsigned int rdistif_num,
108 uintptr_t gicr_base,
109 mpidr_hash_fn mpidr_to_core_pos);
110void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
111void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
112
113/*******************************************************************************
114 * GIC Distributor interface accessors
115 ******************************************************************************/
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100116/*
117 * Wait for updates to :
118 * GICD_CTLR[2:0] - the Group Enables
119 * GICD_CTLR[5:4] - the ARE bits
120 * GICD_ICENABLERn - the clearing of enable state for SPIs
121 */
122static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
123{
124 while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT)
125 ;
126}
127
Achin Gupta92712a52015-09-03 14:18:02 +0100128static inline unsigned int gicd_read_pidr2(uintptr_t base)
129{
130 return mmio_read_32(base + GICD_PIDR2_GICV3);
131}
132
133static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id)
134{
Soby Mathewaaf71c82016-07-26 17:46:56 +0100135 assert(id >= MIN_SPI_ID);
Achin Gupta92712a52015-09-03 14:18:02 +0100136 return mmio_read_64(base + GICD_IROUTER + (id << 3));
137}
138
139static inline void gicd_write_irouter(uintptr_t base,
140 unsigned int id,
141 unsigned long long affinity)
142{
Soby Mathewaaf71c82016-07-26 17:46:56 +0100143 assert(id >= MIN_SPI_ID);
Achin Gupta92712a52015-09-03 14:18:02 +0100144 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity);
145}
146
147static inline void gicd_clr_ctlr(uintptr_t base,
148 unsigned int bitmap,
149 unsigned int rwp)
150{
151 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
152 if (rwp)
153 gicd_wait_for_pending_write(base);
154}
155
156static inline void gicd_set_ctlr(uintptr_t base,
157 unsigned int bitmap,
158 unsigned int rwp)
159{
160 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
161 if (rwp)
162 gicd_wait_for_pending_write(base);
163}
164
165/*******************************************************************************
166 * GIC Redistributor interface accessors
167 ******************************************************************************/
168static inline unsigned long long gicr_read_ctlr(uintptr_t base)
169{
170 return mmio_read_64(base + GICR_CTLR);
171}
172
Soby Mathew327548c2017-07-13 15:19:51 +0100173static inline void gicr_write_ctlr(uintptr_t base, uint64_t val)
174{
175 mmio_write_64(base + GICR_CTLR, val);
176}
177
Achin Gupta92712a52015-09-03 14:18:02 +0100178static inline unsigned long long gicr_read_typer(uintptr_t base)
179{
180 return mmio_read_64(base + GICR_TYPER);
181}
182
183static inline unsigned int gicr_read_waker(uintptr_t base)
184{
185 return mmio_read_32(base + GICR_WAKER);
186}
187
188static inline void gicr_write_waker(uintptr_t base, unsigned int val)
189{
190 mmio_write_32(base + GICR_WAKER, val);
191}
192
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100193/*
194 * Wait for updates to :
195 * GICR_ICENABLER0
196 * GICR_CTLR.DPG1S
197 * GICR_CTLR.DPG1NS
198 * GICR_CTLR.DPG0
199 */
200static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
201{
202 while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT)
203 ;
204}
205
Soby Mathew327548c2017-07-13 15:19:51 +0100206static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)
207{
208 while (gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT)
209 ;
210}
211
212/* Private implementation of Distributor power control hooks */
213void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num);
214void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num);
215
Soby Mathew50f6fe42016-02-01 17:59:22 +0000216/*******************************************************************************
217 * GIC Re-distributor functions for accessing entire registers.
218 * Note: The raw register values correspond to multiple interrupt IDs and
219 * the number of interrupt IDs involved depends on the register accessed.
220 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +0100221static inline unsigned int gicr_read_icenabler0(uintptr_t base)
222{
223 return mmio_read_32(base + GICR_ICENABLER0);
224}
225
226static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val)
227{
228 mmio_write_32(base + GICR_ICENABLER0, val);
229}
230
231static inline unsigned int gicr_read_isenabler0(uintptr_t base)
232{
233 return mmio_read_32(base + GICR_ISENABLER0);
234}
235
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100236static inline void gicr_write_icpendr0(uintptr_t base, unsigned int val)
237{
238 mmio_write_32(base + GICR_ICPENDR0, val);
239}
240
Achin Gupta92712a52015-09-03 14:18:02 +0100241static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val)
242{
243 mmio_write_32(base + GICR_ISENABLER0, val);
244}
245
246static inline unsigned int gicr_read_igroupr0(uintptr_t base)
247{
248 return mmio_read_32(base + GICR_IGROUPR0);
249}
250
Soby Mathew327548c2017-07-13 15:19:51 +0100251static inline unsigned int gicr_read_ispendr0(uintptr_t base)
252{
253 return mmio_read_32(base + GICR_ISPENDR0);
254}
255
256static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val)
257{
258 mmio_write_32(base + GICR_ISPENDR0, val);
259}
260
Achin Gupta92712a52015-09-03 14:18:02 +0100261static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val)
262{
263 mmio_write_32(base + GICR_IGROUPR0, val);
264}
265
266static inline unsigned int gicr_read_igrpmodr0(uintptr_t base)
267{
268 return mmio_read_32(base + GICR_IGRPMODR0);
269}
270
271static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val)
272{
273 mmio_write_32(base + GICR_IGRPMODR0, val);
274}
275
Soby Mathew327548c2017-07-13 15:19:51 +0100276static inline unsigned int gicr_read_nsacr(uintptr_t base)
277{
278 return mmio_read_32(base + GICR_NSACR);
279}
280
281static inline void gicr_write_nsacr(uintptr_t base, unsigned int val)
282{
283 mmio_write_32(base + GICR_NSACR, val);
284}
285
286static inline unsigned int gicr_read_isactiver0(uintptr_t base)
287{
288 return mmio_read_32(base + GICR_ISACTIVER0);
289}
290
291static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val)
292{
293 mmio_write_32(base + GICR_ISACTIVER0, val);
294}
295
296static inline unsigned int gicr_read_icfgr0(uintptr_t base)
297{
298 return mmio_read_32(base + GICR_ICFGR0);
299}
300
Achin Gupta92712a52015-09-03 14:18:02 +0100301static inline unsigned int gicr_read_icfgr1(uintptr_t base)
302{
303 return mmio_read_32(base + GICR_ICFGR1);
304}
305
Soby Mathew327548c2017-07-13 15:19:51 +0100306static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val)
307{
308 mmio_write_32(base + GICR_ICFGR0, val);
309}
310
Achin Gupta92712a52015-09-03 14:18:02 +0100311static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val)
312{
313 mmio_write_32(base + GICR_ICFGR1, val);
314}
315
Soby Mathew327548c2017-07-13 15:19:51 +0100316static inline unsigned int gicr_read_propbaser(uintptr_t base)
317{
318 return mmio_read_32(base + GICR_PROPBASER);
319}
320
321static inline void gicr_write_propbaser(uintptr_t base, unsigned int val)
322{
323 mmio_write_32(base + GICR_PROPBASER, val);
324}
325
326static inline unsigned int gicr_read_pendbaser(uintptr_t base)
327{
328 return mmio_read_32(base + GICR_PENDBASER);
329}
330
331static inline void gicr_write_pendbaser(uintptr_t base, unsigned int val)
332{
333 mmio_write_32(base + GICR_PENDBASER, val);
334}
335
Soby Mathewf6f1a322017-07-18 16:12:45 +0100336/*******************************************************************************
337 * GIC ITS functions to read and write entire ITS registers.
338 ******************************************************************************/
339static inline uint32_t gits_read_ctlr(uintptr_t base)
340{
341 return mmio_read_32(base + GITS_CTLR);
342}
343
344static inline void gits_write_ctlr(uintptr_t base, unsigned int val)
345{
346 mmio_write_32(base + GITS_CTLR, val);
347}
348
349static inline uint64_t gits_read_cbaser(uintptr_t base)
350{
351 return mmio_read_64(base + GITS_CBASER);
352}
353
354static inline void gits_write_cbaser(uintptr_t base, uint64_t val)
355{
356 mmio_write_32(base + GITS_CBASER, val);
357}
358
359static inline uint64_t gits_read_cwriter(uintptr_t base)
360{
361 return mmio_read_64(base + GITS_CWRITER);
362}
363
364static inline void gits_write_cwriter(uintptr_t base, uint64_t val)
365{
366 mmio_write_32(base + GITS_CWRITER, val);
367}
368
369static inline uint64_t gits_read_baser(uintptr_t base, unsigned int its_table_id)
370{
371 assert(its_table_id < 8);
372 return mmio_read_64(base + GITS_BASER + (8 * its_table_id));
373}
374
375static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, uint64_t val)
376{
377 assert(its_table_id < 8);
378 mmio_write_64(base + GITS_BASER + (8 * its_table_id), val);
379}
380
381/*
382 * Wait for Quiescent bit when GIC ITS is disabled
383 */
384static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base)
385{
386 assert(!(gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT));
387 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0)
388 ;
389}
390
391
Achin Gupta92712a52015-09-03 14:18:02 +0100392#endif /* __GICV3_PRIVATE_H__ */