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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
7#ifndef __GICV3_PRIVATE_H__
8#define __GICV3_PRIVATE_H__
9
Soby Mathew327548c2017-07-13 15:19:51 +010010#include <assert.h>
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000011#include <gic_common.h>
Achin Gupta92712a52015-09-03 14:18:02 +010012#include <gicv3.h>
13#include <mmio.h>
14#include <stdint.h>
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000015#include "../common/gic_common_private.h"
Achin Gupta92712a52015-09-03 14:18:02 +010016
17/*******************************************************************************
18 * GICv3 private macro definitions
19 ******************************************************************************/
20
21/* Constants to indicate the status of the RWP bit */
22#define RWP_TRUE 1
23#define RWP_FALSE 0
24
25/*
Achin Gupta92712a52015-09-03 14:18:02 +010026 * Macro to convert an mpidr to a value suitable for programming into a
27 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
28 * to GICv3.
29 */
30#define gicd_irouter_val_from_mpidr(mpidr, irm) \
31 ((mpidr & ~(0xff << 24)) | \
32 (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT)
33
34/*
Achin Gupta92712a52015-09-03 14:18:02 +010035 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
36 * are zeroes.
37 */
Soby Mathewd6452322016-05-05 13:59:07 +010038#ifdef AARCH32
39#define mpidr_from_gicr_typer(typer_val) (((typer_val) >> 32) & 0xffffff)
40#else
Achin Gupta92712a52015-09-03 14:18:02 +010041#define mpidr_from_gicr_typer(typer_val) \
Soby Mathewd6452322016-05-05 13:59:07 +010042 (((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
43 (((typer_val) >> 32) & 0xffffff))
44#endif
Achin Gupta92712a52015-09-03 14:18:02 +010045
46/*******************************************************************************
Soby Mathew327548c2017-07-13 15:19:51 +010047 * GICv3 private global variables declarations
48 ******************************************************************************/
49extern const gicv3_driver_data_t *gicv3_driver_data;
50
51/*******************************************************************************
Soby Mathew50f6fe42016-02-01 17:59:22 +000052 * Private GICv3 function prototypes for accessing entire registers.
53 * Note: The raw register values correspond to multiple interrupt IDs and
54 * the number of interrupt IDs involved depends on the register accessed.
Achin Gupta92712a52015-09-03 14:18:02 +010055 ******************************************************************************/
56unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id);
57unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id);
Soby Mathew50f6fe42016-02-01 17:59:22 +000058void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val);
59void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val);
60
61/*******************************************************************************
62 * Private GICv3 function prototypes for accessing the GIC registers
63 * corresponding to a single interrupt ID. These functions use bitwise
64 * operations or appropriate register accesses to modify or return
65 * the bit-field corresponding the single interrupt ID.
66 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +010067unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id);
68unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id);
69unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +010070unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id);
Achin Gupta92712a52015-09-03 14:18:02 +010071void gicd_set_igrpmodr(uintptr_t base, unsigned int id);
72void gicr_set_igrpmodr0(uintptr_t base, unsigned int id);
73void gicr_set_isenabler0(uintptr_t base, unsigned int id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +010074void gicr_set_icenabler0(uintptr_t base, unsigned int id);
Achin Gupta92712a52015-09-03 14:18:02 +010075void gicr_set_igroupr0(uintptr_t base, unsigned int id);
76void gicd_clr_igrpmodr(uintptr_t base, unsigned int id);
77void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id);
78void gicr_clr_igroupr0(uintptr_t base, unsigned int id);
Soby Mathew50f6fe42016-02-01 17:59:22 +000079void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri);
80
81/*******************************************************************************
82 * Private GICv3 helper function prototypes
83 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +010084void gicv3_spis_configure_defaults(uintptr_t gicd_base);
85void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base);
86void gicv3_secure_spis_configure(uintptr_t gicd_base,
87 unsigned int num_ints,
88 const unsigned int *sec_intr_list,
89 unsigned int int_grp);
90void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base,
91 unsigned int num_ints,
92 const unsigned int *sec_intr_list,
93 unsigned int int_grp);
94void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
95 unsigned int rdistif_num,
96 uintptr_t gicr_base,
97 mpidr_hash_fn mpidr_to_core_pos);
98void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base);
99void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base);
100
101/*******************************************************************************
102 * GIC Distributor interface accessors
103 ******************************************************************************/
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100104/*
105 * Wait for updates to :
106 * GICD_CTLR[2:0] - the Group Enables
107 * GICD_CTLR[5:4] - the ARE bits
108 * GICD_ICENABLERn - the clearing of enable state for SPIs
109 */
110static inline void gicd_wait_for_pending_write(uintptr_t gicd_base)
111{
112 while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT)
113 ;
114}
115
Achin Gupta92712a52015-09-03 14:18:02 +0100116static inline unsigned int gicd_read_pidr2(uintptr_t base)
117{
118 return mmio_read_32(base + GICD_PIDR2_GICV3);
119}
120
121static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id)
122{
Soby Mathewaaf71c82016-07-26 17:46:56 +0100123 assert(id >= MIN_SPI_ID);
Achin Gupta92712a52015-09-03 14:18:02 +0100124 return mmio_read_64(base + GICD_IROUTER + (id << 3));
125}
126
127static inline void gicd_write_irouter(uintptr_t base,
128 unsigned int id,
129 unsigned long long affinity)
130{
Soby Mathewaaf71c82016-07-26 17:46:56 +0100131 assert(id >= MIN_SPI_ID);
Achin Gupta92712a52015-09-03 14:18:02 +0100132 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity);
133}
134
135static inline void gicd_clr_ctlr(uintptr_t base,
136 unsigned int bitmap,
137 unsigned int rwp)
138{
139 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap);
140 if (rwp)
141 gicd_wait_for_pending_write(base);
142}
143
144static inline void gicd_set_ctlr(uintptr_t base,
145 unsigned int bitmap,
146 unsigned int rwp)
147{
148 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap);
149 if (rwp)
150 gicd_wait_for_pending_write(base);
151}
152
153/*******************************************************************************
154 * GIC Redistributor interface accessors
155 ******************************************************************************/
156static inline unsigned long long gicr_read_ctlr(uintptr_t base)
157{
158 return mmio_read_64(base + GICR_CTLR);
159}
160
Soby Mathew327548c2017-07-13 15:19:51 +0100161static inline void gicr_write_ctlr(uintptr_t base, uint64_t val)
162{
163 mmio_write_64(base + GICR_CTLR, val);
164}
165
Achin Gupta92712a52015-09-03 14:18:02 +0100166static inline unsigned long long gicr_read_typer(uintptr_t base)
167{
168 return mmio_read_64(base + GICR_TYPER);
169}
170
171static inline unsigned int gicr_read_waker(uintptr_t base)
172{
173 return mmio_read_32(base + GICR_WAKER);
174}
175
176static inline void gicr_write_waker(uintptr_t base, unsigned int val)
177{
178 mmio_write_32(base + GICR_WAKER, val);
179}
180
Douglas Raillarda1b1da82017-07-26 13:51:00 +0100181/*
182 * Wait for updates to :
183 * GICR_ICENABLER0
184 * GICR_CTLR.DPG1S
185 * GICR_CTLR.DPG1NS
186 * GICR_CTLR.DPG0
187 */
188static inline void gicr_wait_for_pending_write(uintptr_t gicr_base)
189{
190 while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT)
191 ;
192}
193
Soby Mathew327548c2017-07-13 15:19:51 +0100194static inline void gicr_wait_for_upstream_pending_write(uintptr_t gicr_base)
195{
196 while (gicr_read_ctlr(gicr_base) & GICR_CTLR_UWP_BIT)
197 ;
198}
199
200/* Private implementation of Distributor power control hooks */
201void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num);
202void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num);
203
Soby Mathew50f6fe42016-02-01 17:59:22 +0000204/*******************************************************************************
205 * GIC Re-distributor functions for accessing entire registers.
206 * Note: The raw register values correspond to multiple interrupt IDs and
207 * the number of interrupt IDs involved depends on the register accessed.
208 ******************************************************************************/
Achin Gupta92712a52015-09-03 14:18:02 +0100209static inline unsigned int gicr_read_icenabler0(uintptr_t base)
210{
211 return mmio_read_32(base + GICR_ICENABLER0);
212}
213
214static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val)
215{
216 mmio_write_32(base + GICR_ICENABLER0, val);
217}
218
219static inline unsigned int gicr_read_isenabler0(uintptr_t base)
220{
221 return mmio_read_32(base + GICR_ISENABLER0);
222}
223
224static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val)
225{
226 mmio_write_32(base + GICR_ISENABLER0, val);
227}
228
229static inline unsigned int gicr_read_igroupr0(uintptr_t base)
230{
231 return mmio_read_32(base + GICR_IGROUPR0);
232}
233
Soby Mathew327548c2017-07-13 15:19:51 +0100234static inline unsigned int gicr_read_ispendr0(uintptr_t base)
235{
236 return mmio_read_32(base + GICR_ISPENDR0);
237}
238
239static inline void gicr_write_ispendr0(uintptr_t base, unsigned int val)
240{
241 mmio_write_32(base + GICR_ISPENDR0, val);
242}
243
Achin Gupta92712a52015-09-03 14:18:02 +0100244static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val)
245{
246 mmio_write_32(base + GICR_IGROUPR0, val);
247}
248
249static inline unsigned int gicr_read_igrpmodr0(uintptr_t base)
250{
251 return mmio_read_32(base + GICR_IGRPMODR0);
252}
253
254static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val)
255{
256 mmio_write_32(base + GICR_IGRPMODR0, val);
257}
258
Soby Mathew327548c2017-07-13 15:19:51 +0100259static inline unsigned int gicr_read_nsacr(uintptr_t base)
260{
261 return mmio_read_32(base + GICR_NSACR);
262}
263
264static inline void gicr_write_nsacr(uintptr_t base, unsigned int val)
265{
266 mmio_write_32(base + GICR_NSACR, val);
267}
268
269static inline unsigned int gicr_read_isactiver0(uintptr_t base)
270{
271 return mmio_read_32(base + GICR_ISACTIVER0);
272}
273
274static inline void gicr_write_isactiver0(uintptr_t base, unsigned int val)
275{
276 mmio_write_32(base + GICR_ISACTIVER0, val);
277}
278
279static inline unsigned int gicr_read_icfgr0(uintptr_t base)
280{
281 return mmio_read_32(base + GICR_ICFGR0);
282}
283
Achin Gupta92712a52015-09-03 14:18:02 +0100284static inline unsigned int gicr_read_icfgr1(uintptr_t base)
285{
286 return mmio_read_32(base + GICR_ICFGR1);
287}
288
Soby Mathew327548c2017-07-13 15:19:51 +0100289static inline void gicr_write_icfgr0(uintptr_t base, unsigned int val)
290{
291 mmio_write_32(base + GICR_ICFGR0, val);
292}
293
Achin Gupta92712a52015-09-03 14:18:02 +0100294static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val)
295{
296 mmio_write_32(base + GICR_ICFGR1, val);
297}
298
Soby Mathew327548c2017-07-13 15:19:51 +0100299static inline unsigned int gicr_read_propbaser(uintptr_t base)
300{
301 return mmio_read_32(base + GICR_PROPBASER);
302}
303
304static inline void gicr_write_propbaser(uintptr_t base, unsigned int val)
305{
306 mmio_write_32(base + GICR_PROPBASER, val);
307}
308
309static inline unsigned int gicr_read_pendbaser(uintptr_t base)
310{
311 return mmio_read_32(base + GICR_PENDBASER);
312}
313
314static inline void gicr_write_pendbaser(uintptr_t base, unsigned int val)
315{
316 mmio_write_32(base + GICR_PENDBASER, val);
317}
318
Soby Mathewf6f1a322017-07-18 16:12:45 +0100319/*******************************************************************************
320 * GIC ITS functions to read and write entire ITS registers.
321 ******************************************************************************/
322static inline uint32_t gits_read_ctlr(uintptr_t base)
323{
324 return mmio_read_32(base + GITS_CTLR);
325}
326
327static inline void gits_write_ctlr(uintptr_t base, unsigned int val)
328{
329 mmio_write_32(base + GITS_CTLR, val);
330}
331
332static inline uint64_t gits_read_cbaser(uintptr_t base)
333{
334 return mmio_read_64(base + GITS_CBASER);
335}
336
337static inline void gits_write_cbaser(uintptr_t base, uint64_t val)
338{
339 mmio_write_32(base + GITS_CBASER, val);
340}
341
342static inline uint64_t gits_read_cwriter(uintptr_t base)
343{
344 return mmio_read_64(base + GITS_CWRITER);
345}
346
347static inline void gits_write_cwriter(uintptr_t base, uint64_t val)
348{
349 mmio_write_32(base + GITS_CWRITER, val);
350}
351
352static inline uint64_t gits_read_baser(uintptr_t base, unsigned int its_table_id)
353{
354 assert(its_table_id < 8);
355 return mmio_read_64(base + GITS_BASER + (8 * its_table_id));
356}
357
358static inline void gits_write_baser(uintptr_t base, unsigned int its_table_id, uint64_t val)
359{
360 assert(its_table_id < 8);
361 mmio_write_64(base + GITS_BASER + (8 * its_table_id), val);
362}
363
364/*
365 * Wait for Quiescent bit when GIC ITS is disabled
366 */
367static inline void gits_wait_for_quiescent_bit(uintptr_t gits_base)
368{
369 assert(!(gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT));
370 while ((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) == 0)
371 ;
372}
373
374
Achin Gupta92712a52015-09-03 14:18:02 +0100375#endif /* __GICV3_PRIVATE_H__ */