Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 37f97a5 | 2019-03-27 11:10:31 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | #include <string.h> |
| 9 | |
| 10 | #include <platform_def.h> |
| 11 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 12 | #include <arch.h> |
| 13 | #include <arch_helpers.h> |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 14 | #include <context.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <common/debug.h> |
| 16 | #include <lib/el3_runtime/context_mgmt.h> |
| 17 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 18 | #include <plat/common/common_def.h> |
| 19 | #include <plat/common/platform.h> |
| 20 | #include <services/sp_res_desc.h> |
Antonio Nino Diaz | 8c83ad8 | 2018-11-08 14:21:19 +0000 | [diff] [blame] | 21 | #include <sprt_host.h> |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 22 | |
| 23 | #include "spm_private.h" |
| 24 | #include "spm_shim_private.h" |
| 25 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 26 | /* Setup context of the Secure Partition */ |
Antonio Nino Diaz | 2875931 | 2018-05-22 16:26:48 +0100 | [diff] [blame] | 27 | void spm_sp_setup(sp_context_t *sp_ctx) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 28 | { |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 29 | cpu_context_t *ctx = &(sp_ctx->cpu_ctx); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 30 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 31 | /* |
| 32 | * Initialize CPU context |
| 33 | * ---------------------- |
| 34 | */ |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 35 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 36 | entry_point_info_t ep_info = {0}; |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 37 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 38 | SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); |
Antonio Nino Diaz | 268eb5d | 2018-06-11 11:01:54 +0100 | [diff] [blame] | 39 | |
| 40 | /* Setup entrypoint and SPSR */ |
Antonio Nino Diaz | fa5dd1a | 2018-06-26 10:34:25 +0100 | [diff] [blame] | 41 | ep_info.pc = sp_ctx->rd.attribute.entrypoint; |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 42 | ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 43 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 44 | /* |
Antonio Nino Diaz | fe7b2be | 2018-10-30 11:54:20 +0000 | [diff] [blame] | 45 | * X0: Unused (MBZ). |
| 46 | * X1: Unused (MBZ). |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 47 | * X2: cookie value (Implementation Defined) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 48 | * X3: cookie value (Implementation Defined) |
Antonio Nino Diaz | 268eb5d | 2018-06-11 11:01:54 +0100 | [diff] [blame] | 49 | * X4 to X7 = 0 |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 50 | */ |
Antonio Nino Diaz | fe7b2be | 2018-10-30 11:54:20 +0000 | [diff] [blame] | 51 | ep_info.args.arg0 = 0; |
| 52 | ep_info.args.arg1 = 0; |
Antonio Nino Diaz | 268eb5d | 2018-06-11 11:01:54 +0100 | [diff] [blame] | 53 | ep_info.args.arg2 = PLAT_SPM_COOKIE_0; |
| 54 | ep_info.args.arg3 = PLAT_SPM_COOKIE_1; |
| 55 | |
| 56 | cm_setup_context(ctx, &ep_info); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 57 | |
| 58 | /* |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 59 | * Setup translation tables |
| 60 | * ------------------------ |
| 61 | */ |
| 62 | |
Antonio Nino Diaz | bb7d1cd | 2018-10-30 11:34:23 +0000 | [diff] [blame] | 63 | sp_map_memory_regions(sp_ctx); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 64 | |
| 65 | /* |
| 66 | * MMU-related registers |
| 67 | * --------------------- |
| 68 | */ |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 69 | xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle; |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 70 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 71 | uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 72 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 73 | setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table, |
| 74 | xlat_ctx->pa_max_address, xlat_ctx->va_max_address, |
| 75 | EL1_EL0_REGIME); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 76 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 77 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, |
| 78 | mmu_cfg_params[MMU_CFG_MAIR]); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 79 | |
Antonio Nino Diaz | 37f97a5 | 2019-03-27 11:10:31 +0000 | [diff] [blame^] | 80 | /* Enable translations using TTBR1_EL1 */ |
| 81 | int t1sz = 64 - __builtin_ctzll(SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE); |
| 82 | mmu_cfg_params[MMU_CFG_TCR] &= ~TCR_EPD1_BIT; |
| 83 | mmu_cfg_params[MMU_CFG_TCR] |= |
| 84 | ((uint64_t)t1sz << TCR_T1SZ_SHIFT) | |
| 85 | TCR_SH1_INNER_SHAREABLE | |
| 86 | TCR_RGN1_OUTER_WBA | TCR_RGN1_INNER_WBA | |
| 87 | TCR_TG1_4K; |
| 88 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 89 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, |
| 90 | mmu_cfg_params[MMU_CFG_TCR]); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 91 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 92 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, |
| 93 | mmu_cfg_params[MMU_CFG_TTBR0]); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 94 | |
Antonio Nino Diaz | 37f97a5 | 2019-03-27 11:10:31 +0000 | [diff] [blame^] | 95 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR1_EL1, |
| 96 | (uint64_t)spm_exceptions_xlat_get_base_table()); |
| 97 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 98 | /* Setup SCTLR_EL1 */ |
| 99 | u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); |
| 100 | |
| 101 | sctlr_el1 |= |
| 102 | /*SCTLR_EL1_RES1 |*/ |
| 103 | /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */ |
| 104 | SCTLR_UCI_BIT | |
| 105 | /* RW regions at xlat regime EL1&0 are forced to be XN. */ |
| 106 | SCTLR_WXN_BIT | |
| 107 | /* Don't trap to EL1 execution of WFI or WFE at EL0. */ |
| 108 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT | |
| 109 | /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */ |
| 110 | SCTLR_UCT_BIT | |
| 111 | /* Don't trap to EL1 execution of DZ ZVA at EL0. */ |
| 112 | SCTLR_DZE_BIT | |
| 113 | /* Enable SP Alignment check for EL0 */ |
| 114 | SCTLR_SA0_BIT | |
| 115 | /* Allow cacheable data and instr. accesses to normal memory. */ |
| 116 | SCTLR_C_BIT | SCTLR_I_BIT | |
| 117 | /* Alignment fault checking enabled when at EL1 and EL0. */ |
| 118 | SCTLR_A_BIT | |
| 119 | /* Enable MMU. */ |
| 120 | SCTLR_M_BIT |
| 121 | ; |
| 122 | |
| 123 | sctlr_el1 &= ~( |
| 124 | /* Explicit data accesses at EL0 are little-endian. */ |
| 125 | SCTLR_E0E_BIT | |
| 126 | /* Accesses to DAIF from EL0 are trapped to EL1. */ |
| 127 | SCTLR_UMA_BIT |
| 128 | ); |
| 129 | |
| 130 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); |
| 131 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 132 | /* |
| 133 | * Setup other system registers |
| 134 | * ---------------------------- |
| 135 | */ |
| 136 | |
Antonio Nino Diaz | 37f97a5 | 2019-03-27 11:10:31 +0000 | [diff] [blame^] | 137 | /* |
| 138 | * Shim exception vector base address. It is mapped at the start of the |
| 139 | * address space accessed by TTBR1_EL1, which means that the base |
| 140 | * address of the exception vectors depends on the size of the address |
| 141 | * space specified in TCR_EL1.T1SZ. |
| 142 | */ |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 143 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1, |
Antonio Nino Diaz | 37f97a5 | 2019-03-27 11:10:31 +0000 | [diff] [blame^] | 144 | UINT64_MAX - (SPM_SHIM_XLAT_VIRT_ADDR_SPACE_SIZE - 1ULL)); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 145 | |
| 146 | /* |
Sandrine Bailleux | 811934e | 2018-05-09 14:45:34 +0200 | [diff] [blame] | 147 | * FPEN: Allow the Secure Partition to access FP/SIMD registers. |
| 148 | * Note that SPM will not do any saving/restoring of these registers on |
| 149 | * behalf of the SP. This falls under the SP's responsibility. |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 150 | * TTA: Enable access to trace registers. |
| 151 | * ZEN (v8.2): Trap SVE instructions and access to SVE registers. |
| 152 | */ |
| 153 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1, |
Sandrine Bailleux | 811934e | 2018-05-09 14:45:34 +0200 | [diff] [blame] | 154 | CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE)); |
Antonio Nino Diaz | 8c83ad8 | 2018-11-08 14:21:19 +0000 | [diff] [blame] | 155 | |
| 156 | /* |
| 157 | * Prepare shared buffers |
| 158 | * ---------------------- |
| 159 | */ |
| 160 | |
| 161 | /* Initialize SPRT queues */ |
| 162 | sprt_initialize_queues((void *)sp_ctx->spm_sp_buffer_base, |
| 163 | sp_ctx->spm_sp_buffer_size); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 164 | } |