Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 9 | #include <assert.h> |
| 10 | #include <common_def.h> |
| 11 | #include <context.h> |
| 12 | #include <context_mgmt.h> |
| 13 | #include <debug.h> |
| 14 | #include <platform_def.h> |
| 15 | #include <platform.h> |
Antonio Nino Diaz | fa5dd1a | 2018-06-26 10:34:25 +0100 | [diff] [blame] | 16 | #include <sp_res_desc.h> |
Antonio Nino Diaz | 8c83ad8 | 2018-11-08 14:21:19 +0000 | [diff] [blame^] | 17 | #include <sprt_host.h> |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 18 | #include <string.h> |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 19 | #include <xlat_tables_v2.h> |
| 20 | |
| 21 | #include "spm_private.h" |
| 22 | #include "spm_shim_private.h" |
| 23 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 24 | /* Setup context of the Secure Partition */ |
Antonio Nino Diaz | 2875931 | 2018-05-22 16:26:48 +0100 | [diff] [blame] | 25 | void spm_sp_setup(sp_context_t *sp_ctx) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 26 | { |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 27 | cpu_context_t *ctx = &(sp_ctx->cpu_ctx); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 28 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 29 | /* |
| 30 | * Initialize CPU context |
| 31 | * ---------------------- |
| 32 | */ |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 33 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 34 | entry_point_info_t ep_info = {0}; |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 35 | |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 36 | SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); |
Antonio Nino Diaz | 268eb5d | 2018-06-11 11:01:54 +0100 | [diff] [blame] | 37 | |
| 38 | /* Setup entrypoint and SPSR */ |
Antonio Nino Diaz | fa5dd1a | 2018-06-26 10:34:25 +0100 | [diff] [blame] | 39 | ep_info.pc = sp_ctx->rd.attribute.entrypoint; |
Antonio Nino Diaz | 2ac9a44 | 2018-05-23 11:40:46 +0100 | [diff] [blame] | 40 | ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 41 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 42 | /* |
Antonio Nino Diaz | fe7b2be | 2018-10-30 11:54:20 +0000 | [diff] [blame] | 43 | * X0: Unused (MBZ). |
| 44 | * X1: Unused (MBZ). |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 45 | * X2: cookie value (Implementation Defined) |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 46 | * X3: cookie value (Implementation Defined) |
Antonio Nino Diaz | 268eb5d | 2018-06-11 11:01:54 +0100 | [diff] [blame] | 47 | * X4 to X7 = 0 |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 48 | */ |
Antonio Nino Diaz | fe7b2be | 2018-10-30 11:54:20 +0000 | [diff] [blame] | 49 | ep_info.args.arg0 = 0; |
| 50 | ep_info.args.arg1 = 0; |
Antonio Nino Diaz | 268eb5d | 2018-06-11 11:01:54 +0100 | [diff] [blame] | 51 | ep_info.args.arg2 = PLAT_SPM_COOKIE_0; |
| 52 | ep_info.args.arg3 = PLAT_SPM_COOKIE_1; |
| 53 | |
| 54 | cm_setup_context(ctx, &ep_info); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 55 | |
| 56 | /* |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 57 | * Setup translation tables |
| 58 | * ------------------------ |
| 59 | */ |
| 60 | |
Antonio Nino Diaz | bb7d1cd | 2018-10-30 11:34:23 +0000 | [diff] [blame] | 61 | sp_map_memory_regions(sp_ctx); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 62 | |
| 63 | /* |
| 64 | * MMU-related registers |
| 65 | * --------------------- |
| 66 | */ |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 67 | xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle; |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 68 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 69 | uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 70 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 71 | setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table, |
| 72 | xlat_ctx->pa_max_address, xlat_ctx->va_max_address, |
| 73 | EL1_EL0_REGIME); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 74 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 75 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, |
| 76 | mmu_cfg_params[MMU_CFG_MAIR]); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 77 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 78 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, |
| 79 | mmu_cfg_params[MMU_CFG_TCR]); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 80 | |
Antonio Nino Diaz | ea4c693 | 2018-07-11 13:07:06 +0100 | [diff] [blame] | 81 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, |
| 82 | mmu_cfg_params[MMU_CFG_TTBR0]); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 83 | |
| 84 | /* Setup SCTLR_EL1 */ |
| 85 | u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); |
| 86 | |
| 87 | sctlr_el1 |= |
| 88 | /*SCTLR_EL1_RES1 |*/ |
| 89 | /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */ |
| 90 | SCTLR_UCI_BIT | |
| 91 | /* RW regions at xlat regime EL1&0 are forced to be XN. */ |
| 92 | SCTLR_WXN_BIT | |
| 93 | /* Don't trap to EL1 execution of WFI or WFE at EL0. */ |
| 94 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT | |
| 95 | /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */ |
| 96 | SCTLR_UCT_BIT | |
| 97 | /* Don't trap to EL1 execution of DZ ZVA at EL0. */ |
| 98 | SCTLR_DZE_BIT | |
| 99 | /* Enable SP Alignment check for EL0 */ |
| 100 | SCTLR_SA0_BIT | |
| 101 | /* Allow cacheable data and instr. accesses to normal memory. */ |
| 102 | SCTLR_C_BIT | SCTLR_I_BIT | |
| 103 | /* Alignment fault checking enabled when at EL1 and EL0. */ |
| 104 | SCTLR_A_BIT | |
| 105 | /* Enable MMU. */ |
| 106 | SCTLR_M_BIT |
| 107 | ; |
| 108 | |
| 109 | sctlr_el1 &= ~( |
| 110 | /* Explicit data accesses at EL0 are little-endian. */ |
| 111 | SCTLR_E0E_BIT | |
| 112 | /* Accesses to DAIF from EL0 are trapped to EL1. */ |
| 113 | SCTLR_UMA_BIT |
| 114 | ); |
| 115 | |
| 116 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); |
| 117 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 118 | /* |
| 119 | * Setup other system registers |
| 120 | * ---------------------------- |
| 121 | */ |
| 122 | |
| 123 | /* Shim Exception Vector Base Address */ |
| 124 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1, |
| 125 | SPM_SHIM_EXCEPTIONS_PTR); |
| 126 | |
| 127 | /* |
Sandrine Bailleux | 811934e | 2018-05-09 14:45:34 +0200 | [diff] [blame] | 128 | * FPEN: Allow the Secure Partition to access FP/SIMD registers. |
| 129 | * Note that SPM will not do any saving/restoring of these registers on |
| 130 | * behalf of the SP. This falls under the SP's responsibility. |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 131 | * TTA: Enable access to trace registers. |
| 132 | * ZEN (v8.2): Trap SVE instructions and access to SVE registers. |
| 133 | */ |
| 134 | write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1, |
Sandrine Bailleux | 811934e | 2018-05-09 14:45:34 +0200 | [diff] [blame] | 135 | CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE)); |
Antonio Nino Diaz | 8c83ad8 | 2018-11-08 14:21:19 +0000 | [diff] [blame^] | 136 | |
| 137 | /* |
| 138 | * Prepare shared buffers |
| 139 | * ---------------------- |
| 140 | */ |
| 141 | |
| 142 | /* Initialize SPRT queues */ |
| 143 | sprt_initialize_queues((void *)sp_ctx->spm_sp_buffer_base, |
| 144 | sp_ctx->spm_sp_buffer_size); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 145 | } |