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Antonio Nino Diazc41f2062017-10-24 10:07:35 +01001/*
Antonio Nino Diaz2ac9a442018-05-23 11:40:46 +01002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diazc41f2062017-10-24 10:07:35 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <arch_helpers.h>
Antonio Nino Diazc41f2062017-10-24 10:07:35 +01009#include <assert.h>
10#include <common_def.h>
11#include <context.h>
12#include <context_mgmt.h>
13#include <debug.h>
14#include <platform_def.h>
15#include <platform.h>
16#include <secure_partition.h>
17#include <string.h>
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010018#include <xlat_tables_v2.h>
19
20#include "spm_private.h"
21#include "spm_shim_private.h"
22
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010023/* Setup context of the Secure Partition */
Antonio Nino Diaz28759312018-05-22 16:26:48 +010024void spm_sp_setup(sp_context_t *sp_ctx)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010025{
Antonio Nino Diaz2ac9a442018-05-23 11:40:46 +010026 cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010027
Antonio Nino Diaz2ac9a442018-05-23 11:40:46 +010028 /*
29 * Initialize CPU context
30 * ----------------------
31 */
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010032
Antonio Nino Diaz2ac9a442018-05-23 11:40:46 +010033 entry_point_info_t ep_info = {0};
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010034
Antonio Nino Diaz2ac9a442018-05-23 11:40:46 +010035 SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
Antonio Nino Diaz268eb5d2018-06-11 11:01:54 +010036
37 /* Setup entrypoint and SPSR */
Antonio Nino Diaz2ac9a442018-05-23 11:40:46 +010038 ep_info.pc = BL32_BASE;
39 ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010040
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010041 /*
42 * X0: Virtual address of a buffer shared between EL3 and Secure EL0.
43 * The buffer will be mapped in the Secure EL1 translation regime
44 * with Normal IS WBWA attributes and RO data and Execute Never
45 * instruction access permissions.
46 *
47 * X1: Size of the buffer in bytes
48 *
49 * X2: cookie value (Implementation Defined)
50 *
51 * X3: cookie value (Implementation Defined)
52 *
Antonio Nino Diaz268eb5d2018-06-11 11:01:54 +010053 * X4 to X7 = 0
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010054 */
Antonio Nino Diaz268eb5d2018-06-11 11:01:54 +010055 ep_info.args.arg0 = PLAT_SPM_BUF_BASE;
56 ep_info.args.arg1 = PLAT_SPM_BUF_SIZE;
57 ep_info.args.arg2 = PLAT_SPM_COOKIE_0;
58 ep_info.args.arg3 = PLAT_SPM_COOKIE_1;
59
60 cm_setup_context(ctx, &ep_info);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010061
62 /*
63 * SP_EL0: A non-zero value will indicate to the SP that the SPM has
64 * initialized the stack pointer for the current CPU through
65 * implementation defined means. The value will be 0 otherwise.
66 */
67 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0,
68 PLAT_SP_IMAGE_STACK_BASE + PLAT_SP_IMAGE_STACK_PCPU_SIZE);
69
70 /*
71 * Setup translation tables
72 * ------------------------
73 */
74
75#if ENABLE_ASSERTIONS
76
77 /* Get max granularity supported by the platform. */
Antonio Nino Diaz4413ad52018-06-11 13:40:32 +010078 unsigned int max_granule = xlat_arch_get_max_supported_granule_size();
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010079
Antonio Nino Diaz4413ad52018-06-11 13:40:32 +010080 VERBOSE("Max translation granule size supported: %u KiB\n",
81 max_granule / 1024U);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010082
Antonio Nino Diaz4413ad52018-06-11 13:40:32 +010083 unsigned int max_granule_mask = max_granule - 1U;
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010084
85 /* Base must be aligned to the max granularity */
Antonio Nino Diaz4413ad52018-06-11 13:40:32 +010086 assert((ARM_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010087
88 /* Size must be a multiple of the max granularity */
Antonio Nino Diaz4413ad52018-06-11 13:40:32 +010089 assert((ARM_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010090
91#endif /* ENABLE_ASSERTIONS */
92
93 /* This region contains the exception vectors used at S-EL1. */
94 const mmap_region_t sel1_exception_vectors =
95 MAP_REGION_FLAT(SPM_SHIM_EXCEPTIONS_START,
96 SPM_SHIM_EXCEPTIONS_SIZE,
97 MT_CODE | MT_SECURE | MT_PRIVILEGED);
Antonio Nino Diaz2ac9a442018-05-23 11:40:46 +010098 mmap_add_region_ctx(sp_ctx->xlat_ctx_handle,
Antonio Nino Diazc41f2062017-10-24 10:07:35 +010099 &sel1_exception_vectors);
100
Antonio Nino Diaz2ac9a442018-05-23 11:40:46 +0100101 mmap_add_ctx(sp_ctx->xlat_ctx_handle,
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100102 plat_get_secure_partition_mmap(NULL));
103
Antonio Nino Diaz2ac9a442018-05-23 11:40:46 +0100104 init_xlat_tables_ctx(sp_ctx->xlat_ctx_handle);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100105
106 /*
107 * MMU-related registers
108 * ---------------------
109 */
Antonio Nino Diazea4c6932018-07-11 13:07:06 +0100110 xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle;
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100111
Antonio Nino Diazea4c6932018-07-11 13:07:06 +0100112 uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100113
Antonio Nino Diazea4c6932018-07-11 13:07:06 +0100114 setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table,
115 xlat_ctx->pa_max_address, xlat_ctx->va_max_address,
116 EL1_EL0_REGIME);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100117
Antonio Nino Diazea4c6932018-07-11 13:07:06 +0100118 write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1,
119 mmu_cfg_params[MMU_CFG_MAIR]);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100120
Antonio Nino Diazea4c6932018-07-11 13:07:06 +0100121 write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1,
122 mmu_cfg_params[MMU_CFG_TCR]);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100123
Antonio Nino Diazea4c6932018-07-11 13:07:06 +0100124 write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1,
125 mmu_cfg_params[MMU_CFG_TTBR0]);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100126
127 /* Setup SCTLR_EL1 */
128 u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1);
129
130 sctlr_el1 |=
131 /*SCTLR_EL1_RES1 |*/
132 /* Don't trap DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU */
133 SCTLR_UCI_BIT |
134 /* RW regions at xlat regime EL1&0 are forced to be XN. */
135 SCTLR_WXN_BIT |
136 /* Don't trap to EL1 execution of WFI or WFE at EL0. */
137 SCTLR_NTWI_BIT | SCTLR_NTWE_BIT |
138 /* Don't trap to EL1 accesses to CTR_EL0 from EL0. */
139 SCTLR_UCT_BIT |
140 /* Don't trap to EL1 execution of DZ ZVA at EL0. */
141 SCTLR_DZE_BIT |
142 /* Enable SP Alignment check for EL0 */
143 SCTLR_SA0_BIT |
144 /* Allow cacheable data and instr. accesses to normal memory. */
145 SCTLR_C_BIT | SCTLR_I_BIT |
146 /* Alignment fault checking enabled when at EL1 and EL0. */
147 SCTLR_A_BIT |
148 /* Enable MMU. */
149 SCTLR_M_BIT
150 ;
151
152 sctlr_el1 &= ~(
153 /* Explicit data accesses at EL0 are little-endian. */
154 SCTLR_E0E_BIT |
155 /* Accesses to DAIF from EL0 are trapped to EL1. */
156 SCTLR_UMA_BIT
157 );
158
159 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
160
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100161 /*
162 * Setup other system registers
163 * ----------------------------
164 */
165
166 /* Shim Exception Vector Base Address */
167 write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1,
168 SPM_SHIM_EXCEPTIONS_PTR);
169
170 /*
Sandrine Bailleux811934e2018-05-09 14:45:34 +0200171 * FPEN: Allow the Secure Partition to access FP/SIMD registers.
172 * Note that SPM will not do any saving/restoring of these registers on
173 * behalf of the SP. This falls under the SP's responsibility.
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100174 * TTA: Enable access to trace registers.
175 * ZEN (v8.2): Trap SVE instructions and access to SVE registers.
176 */
177 write_ctx_reg(get_sysregs_ctx(ctx), CTX_CPACR_EL1,
Sandrine Bailleux811934e2018-05-09 14:45:34 +0200178 CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE));
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100179
180 /*
181 * Prepare information in buffer shared between EL3 and S-EL0
182 * ----------------------------------------------------------
183 */
184
185 void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE;
186
187 /* Copy the boot information into the shared buffer with the SP. */
188 assert((uintptr_t)shared_buf_ptr + sizeof(secure_partition_boot_info_t)
189 <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE));
190
191 assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1));
192
193 const secure_partition_boot_info_t *sp_boot_info =
194 plat_get_secure_partition_boot_info(NULL);
195
196 assert(sp_boot_info != NULL);
197
198 memcpy((void *) shared_buf_ptr, (const void *) sp_boot_info,
199 sizeof(secure_partition_boot_info_t));
200
201 /* Pointer to the MP information from the platform port. */
202 secure_partition_mp_info_t *sp_mp_info =
203 ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
204
205 assert(sp_mp_info != NULL);
206
207 /*
208 * Point the shared buffer MP information pointer to where the info will
209 * be populated, just after the boot info.
210 */
211 ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info =
Antonio Nino Diaz0dcebaf2017-11-10 12:25:49 +0000212 (secure_partition_mp_info_t *) ((uintptr_t)shared_buf_ptr
213 + sizeof(secure_partition_boot_info_t));
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100214
215 /*
216 * Update the shared buffer pointer to where the MP information for the
217 * payload will be populated
218 */
219 shared_buf_ptr = ((secure_partition_boot_info_t *) shared_buf_ptr)->mp_info;
220
221 /*
222 * Copy the cpu information into the shared buffer area after the boot
223 * information.
224 */
225 assert(sp_boot_info->num_cpus <= PLATFORM_CORE_COUNT);
226
227 assert((uintptr_t)shared_buf_ptr
228 <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE -
229 (sp_boot_info->num_cpus * sizeof(*sp_mp_info))));
230
231 memcpy(shared_buf_ptr, (const void *) sp_mp_info,
232 sp_boot_info->num_cpus * sizeof(*sp_mp_info));
233
234 /*
235 * Calculate the linear indices of cores in boot information for the
236 * secure partition and flag the primary CPU
237 */
238 sp_mp_info = (secure_partition_mp_info_t *) shared_buf_ptr;
239
240 for (unsigned int index = 0; index < sp_boot_info->num_cpus; index++) {
241 u_register_t mpidr = sp_mp_info[index].mpidr;
242
243 sp_mp_info[index].linear_id = plat_core_pos_by_mpidr(mpidr);
244 if (plat_my_core_pos() == sp_mp_info[index].linear_id)
245 sp_mp_info[index].flags |= MP_INFO_FLAG_PRIMARY_CPU;
246 }
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100247}