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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Sona Mathew4a3811f2024-01-01 21:00:44 -06002 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
Varun Wadekar61286d22023-03-08 16:47:38 +00003 * Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01006 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <assert.h>
9
Achin Gupta92712a52015-09-03 14:18:02 +010010#include <arch.h>
11#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <common/debug.h>
13#include <common/interrupt_props.h>
Varun Wadekar61286d22023-03-08 16:47:38 +000014#include <drivers/arm/gic600_multichip.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <drivers/arm/gicv3.h>
16#include <lib/spinlock.h>
Channagoud kadabia037d972022-11-29 16:03:47 -080017#include <plat/common/platform.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018
Achin Gupta92712a52015-09-03 14:18:02 +010019#include "gicv3_private.h"
20
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +000021const gicv3_driver_data_t *gicv3_driver_data;
Achin Gupta92712a52015-09-03 14:18:02 +010022
Jeenu Viswambharan76647d52016-12-09 11:03:15 +000023/*
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010024 * Spinlock to guard registers needing read-modify-write. APIs protected by this
25 * spinlock are used either at boot time (when only a single CPU is active), or
26 * when the system is fully coherent.
27 */
Roberto Vargas2ca18d92018-02-12 12:36:17 +000028static spinlock_t gic_lock;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010029
30/*
Jeenu Viswambharan76647d52016-12-09 11:03:15 +000031 * Redistributor power operations are weakly bound so that they can be
32 * overridden
33 */
34#pragma weak gicv3_rdistif_off
35#pragma weak gicv3_rdistif_on
36
Sona Mathew4a3811f2024-01-01 21:00:44 -060037/* Check for valid SGI/PPI or SPI interrupt ID */
38static bool is_valid_interrupt(unsigned int id);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010039
40/*
41 * Helper macros to save and restore GICR and GICD registers
42 * corresponding to their numbers to and from the context
43 */
44#define RESTORE_GICR_REG(base, ctx, name, i) \
45 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)])
46
47#define SAVE_GICR_REG(base, ctx, name, i) \
48 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i))
Soby Mathew327548c2017-07-13 15:19:51 +010049
50/* Helper macros to save and restore GICD registers to and from the context */
51#define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \
52 do { \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010053 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\
54 int_id += (1U << REG##R_SHIFT)) { \
55 gicd_write_##reg((base), int_id, \
56 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \
57 REG##R_SHIFT]); \
Soby Mathew327548c2017-07-13 15:19:51 +010058 } \
Antonio Nino Diazca994e72018-08-21 10:02:33 +010059 } while (false)
Soby Mathew327548c2017-07-13 15:19:51 +010060
61#define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \
62 do { \
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010063 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\
64 int_id += (1U << REG##R_SHIFT)) { \
65 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \
66 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \
67 } \
68 } while (false)
69
70#if GIC_EXT_INTID
71#define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \
72 do { \
73 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
74 int_id += (1U << REG##R_SHIFT)) { \
75 gicd_write_##reg((base), int_id, \
Heyi Guoefa21072021-01-14 22:16:18 +080076 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
77 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010078 >> REG##R_SHIFT]); \
Soby Mathew327548c2017-07-13 15:19:51 +010079 } \
Antonio Nino Diazca994e72018-08-21 10:02:33 +010080 } while (false)
Soby Mathew327548c2017-07-13 15:19:51 +010081
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010082#define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \
83 do { \
84 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
85 int_id += (1U << REG##R_SHIFT)) { \
Heyi Guoefa21072021-01-14 22:16:18 +080086 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
87 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
Alexei Fedorova6e6ae02020-04-06 16:27:54 +010088 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\
89 } \
90 } while (false)
91#else
92#define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG)
93#define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG)
94#endif /* GIC_EXT_INTID */
Soby Mathew327548c2017-07-13 15:19:51 +010095
Achin Gupta92712a52015-09-03 14:18:02 +010096/*******************************************************************************
97 * This function initialises the ARM GICv3 driver in EL3 with provided platform
98 * inputs.
99 ******************************************************************************/
Daniel Boulby844b4872018-09-18 13:36:39 +0100100void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
Achin Gupta92712a52015-09-03 14:18:02 +0100101{
102 unsigned int gic_version;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500103 unsigned int gicv2_compat;
Achin Gupta92712a52015-09-03 14:18:02 +0100104
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100105 assert(plat_driver_data != NULL);
106 assert(plat_driver_data->gicd_base != 0U);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100107 assert(plat_driver_data->rdistif_num != 0U);
108 assert(plat_driver_data->rdistif_base_addrs != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +0100109
110 assert(IS_IN_EL3());
111
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500112 assert((plat_driver_data->interrupt_props_num != 0U) ?
113 (plat_driver_data->interrupt_props != NULL) : 1);
Achin Gupta92712a52015-09-03 14:18:02 +0100114
115 /* Check for system register support */
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500116#ifndef __aarch64__
117 assert((read_id_pfr1() &
118 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
119#else
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100120 assert((read_id_aa64pfr0_el1() &
121 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500122#endif /* !__aarch64__ */
Achin Gupta92712a52015-09-03 14:18:02 +0100123
Achin Gupta92712a52015-09-03 14:18:02 +0100124 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500125 gic_version >>= PIDR2_ARCH_REV_SHIFT;
Achin Gupta92712a52015-09-03 14:18:02 +0100126 gic_version &= PIDR2_ARCH_REV_MASK;
Achin Gupta92712a52015-09-03 14:18:02 +0100127
Alexei Fedorov19705932020-04-06 19:00:35 +0100128 /* Check GIC version */
Andre Przywaraf70f4b92021-05-18 15:51:06 +0100129#if !GIC_ENABLE_V4_EXTN
Alexei Fedorov19705932020-04-06 19:00:35 +0100130 assert(gic_version == ARCH_REV_GICV3);
131#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100132 /*
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500133 * Find out whether the GIC supports the GICv2 compatibility mode.
134 * The ARE_S bit resets to 0 if supported
Achin Gupta92712a52015-09-03 14:18:02 +0100135 */
136 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base);
137 gicv2_compat >>= CTLR_ARE_S_SHIFT;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500138 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK;
Achin Gupta92712a52015-09-03 14:18:02 +0100139
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500140 if (plat_driver_data->gicr_base != 0U) {
141 /*
142 * Find the base address of each implemented Redistributor interface.
143 * The number of interfaces should be equal to the number of CPUs in the
144 * system. The memory for saving these addresses has to be allocated by
145 * the platform port
146 */
147 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
148 plat_driver_data->rdistif_num,
149 plat_driver_data->gicr_base,
150 plat_driver_data->mpidr_to_core_pos);
151#if !HW_ASSISTED_COHERENCY
152 /*
153 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
154 */
155 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs),
156 plat_driver_data->rdistif_num *
157 sizeof(*(plat_driver_data->rdistif_base_addrs)));
158#endif
159 }
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000160 gicv3_driver_data = plat_driver_data;
Achin Gupta92712a52015-09-03 14:18:02 +0100161
Soby Mathew72645132017-02-14 10:11:52 +0000162 /*
163 * The GIC driver data is initialized by the primary CPU with caches
164 * enabled. When the secondary CPU boots up, it initializes the
165 * GICC/GICR interface with the caches disabled. Hence flush the
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000166 * driver data to ensure coherency. This is not required if the
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500167 * platform has HW_ASSISTED_COHERENCY enabled.
Soby Mathew72645132017-02-14 10:11:52 +0000168 */
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500169#if !HW_ASSISTED_COHERENCY
170 flush_dcache_range((uintptr_t)&gicv3_driver_data,
171 sizeof(gicv3_driver_data));
172 flush_dcache_range((uintptr_t)gicv3_driver_data,
173 sizeof(*gicv3_driver_data));
Soby Mathew72645132017-02-14 10:11:52 +0000174#endif
Manish V Badarkhe173c2962022-05-09 21:55:19 +0100175 gicv3_check_erratas_applies(plat_driver_data->gicd_base);
176
Alexei Fedorov19705932020-04-06 19:00:35 +0100177 INFO("GICv%u with%s legacy support detected.\n", gic_version,
178 (gicv2_compat == 0U) ? "" : "out");
179 INFO("ARM GICv%u driver initialized in EL3\n", gic_version);
Achin Gupta92712a52015-09-03 14:18:02 +0100180}
181
182/*******************************************************************************
183 * This function initialises the GIC distributor interface based upon the data
184 * provided by the platform while initialising the driver.
185 ******************************************************************************/
Daniel Boulby844b4872018-09-18 13:36:39 +0100186void __init gicv3_distif_init(void)
Achin Gupta92712a52015-09-03 14:18:02 +0100187{
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100188 unsigned int bitmap;
Yatharth Kochar3f00a892016-09-06 11:48:05 +0100189
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100190 assert(gicv3_driver_data != NULL);
191 assert(gicv3_driver_data->gicd_base != 0U);
Achin Gupta92712a52015-09-03 14:18:02 +0100192
193 assert(IS_IN_EL3());
194
195 /*
196 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
197 * the ARE_S bit. The Distributor might generate a system error
198 * otherwise.
199 */
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000200 gicd_clr_ctlr(gicv3_driver_data->gicd_base,
Achin Gupta92712a52015-09-03 14:18:02 +0100201 CTLR_ENABLE_G0_BIT |
202 CTLR_ENABLE_G1S_BIT |
203 CTLR_ENABLE_G1NS_BIT,
204 RWP_TRUE);
205
206 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000207 gicd_set_ctlr(gicv3_driver_data->gicd_base,
Achin Gupta92712a52015-09-03 14:18:02 +0100208 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
209
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100210 /* Set the default attribute of all (E)SPIs */
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100211 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
Achin Gupta92712a52015-09-03 14:18:02 +0100212
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +0100213 bitmap = gicv3_secure_spis_config_props(
214 gicv3_driver_data->gicd_base,
215 gicv3_driver_data->interrupt_props,
216 gicv3_driver_data->interrupt_props_num);
Achin Gupta92712a52015-09-03 14:18:02 +0100217
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100218 /* Enable the secure (E)SPIs now that they have been configured */
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000219 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
Achin Gupta92712a52015-09-03 14:18:02 +0100220}
221
222/*******************************************************************************
223 * This function initialises the GIC Redistributor interface of the calling CPU
224 * (identified by the 'proc_num' parameter) based upon the data provided by the
225 * platform while initialising the driver.
226 ******************************************************************************/
227void gicv3_rdistif_init(unsigned int proc_num)
228{
229 uintptr_t gicr_base;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100230 unsigned int bitmap;
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000231 uint32_t ctlr;
Achin Gupta92712a52015-09-03 14:18:02 +0100232
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100233 assert(gicv3_driver_data != NULL);
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000234 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100235 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
236 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000237
238 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100239 assert((ctlr & CTLR_ARE_S_BIT) != 0U);
Achin Gupta92712a52015-09-03 14:18:02 +0100240
241 assert(IS_IN_EL3());
242
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000243 /* Power on redistributor */
244 gicv3_rdistif_on(proc_num);
245
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000246 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -0500247 assert(gicr_base != 0U);
Achin Gupta92712a52015-09-03 14:18:02 +0100248
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100249 /* Set the default attribute of all SGIs and (E)PPIs */
Daniel Boulby4e83abb2018-05-01 15:15:34 +0100250 gicv3_ppi_sgi_config_defaults(gicr_base);
Achin Gupta92712a52015-09-03 14:18:02 +0100251
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +0100252 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
253 gicv3_driver_data->interrupt_props,
254 gicv3_driver_data->interrupt_props_num);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000255
256 /* Enable interrupt groups as required, if not already */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100257 if ((ctlr & bitmap) != bitmap) {
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000258 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100259 }
Achin Gupta92712a52015-09-03 14:18:02 +0100260}
261
262/*******************************************************************************
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000263 * Functions to perform power operations on GIC Redistributor
264 ******************************************************************************/
265void gicv3_rdistif_off(unsigned int proc_num)
266{
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000267}
268
269void gicv3_rdistif_on(unsigned int proc_num)
270{
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000271}
272
273/*******************************************************************************
Achin Gupta92712a52015-09-03 14:18:02 +0100274 * This function enables the GIC CPU interface of the calling CPU using only
275 * system register accesses.
276 ******************************************************************************/
277void gicv3_cpuif_enable(unsigned int proc_num)
278{
279 uintptr_t gicr_base;
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000280 u_register_t scr_el3;
Achin Gupta92712a52015-09-03 14:18:02 +0100281 unsigned int icc_sre_el3;
282
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100283 assert(gicv3_driver_data != NULL);
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000284 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100285 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +0100286 assert(IS_IN_EL3());
287
288 /* Mark the connected core as awake */
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000289 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Achin Gupta92712a52015-09-03 14:18:02 +0100290 gicv3_rdistif_mark_core_awake(gicr_base);
291
292 /* Disable the legacy interrupt bypass */
293 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT;
294
295 /*
296 * Enable system register access for EL3 and allow lower exception
297 * levels to configure the same for themselves. If the legacy mode is
298 * not supported, the SRE bit is RAO/WI
299 */
300 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
301 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
302
Louis Mayencourt1c819c32020-01-24 13:30:28 +0000303 scr_el3 = read_scr_el3();
Achin Gupta92712a52015-09-03 14:18:02 +0100304
305 /*
306 * Switch to NS state to write Non secure ICC_SRE_EL1 and
307 * ICC_SRE_EL2 registers.
308 */
309 write_scr_el3(scr_el3 | SCR_NS_BIT);
310 isb();
311
312 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3);
313 write_icc_sre_el1(ICC_SRE_SRE_BIT);
314 isb();
315
316 /* Switch to secure state. */
317 write_scr_el3(scr_el3 & (~SCR_NS_BIT));
318 isb();
319
James kung05403eb2019-05-31 15:40:05 +0800320 /* Write the secure ICC_SRE_EL1 register */
321 write_icc_sre_el1(ICC_SRE_SRE_BIT);
322 isb();
323
Achin Gupta92712a52015-09-03 14:18:02 +0100324 /* Program the idle priority in the PMR */
325 write_icc_pmr_el1(GIC_PRI_MASK);
326
327 /* Enable Group0 interrupts */
328 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT);
329
330 /* Enable Group1 Secure interrupts */
331 write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
332 IGRPEN1_EL3_ENABLE_G1S_BIT);
Boyan Karatotevada21dc2023-03-23 12:46:53 +0000333 /* and restore the original */
334 write_scr_el3(scr_el3);
Achin Gupta92712a52015-09-03 14:18:02 +0100335 isb();
Ming Huang94e19762021-06-04 16:23:22 +0800336 /* Add DSB to ensure visibility of System register writes */
337 dsb();
Achin Gupta92712a52015-09-03 14:18:02 +0100338}
339
340/*******************************************************************************
341 * This function disables the GIC CPU interface of the calling CPU using
342 * only system register accesses.
343 ******************************************************************************/
344void gicv3_cpuif_disable(unsigned int proc_num)
345{
346 uintptr_t gicr_base;
347
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100348 assert(gicv3_driver_data != NULL);
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000349 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100350 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +0100351
352 assert(IS_IN_EL3());
353
354 /* Disable legacy interrupt bypass */
355 write_icc_sre_el3(read_icc_sre_el3() |
356 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT));
357
358 /* Disable Group0 interrupts */
359 write_icc_igrpen0_el1(read_icc_igrpen0_el1() &
360 ~IGRPEN1_EL1_ENABLE_G0_BIT);
361
Sudeep Holla869e3db2016-08-04 16:14:50 +0100362 /* Disable Group1 Secure and Non-Secure interrupts */
Achin Gupta92712a52015-09-03 14:18:02 +0100363 write_icc_igrpen1_el3(read_icc_igrpen1_el3() &
Sudeep Holla869e3db2016-08-04 16:14:50 +0100364 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT |
365 IGRPEN1_EL3_ENABLE_G1S_BIT));
Achin Gupta92712a52015-09-03 14:18:02 +0100366
367 /* Synchronise accesses to group enable registers */
368 isb();
Ming Huang94e19762021-06-04 16:23:22 +0800369 /* Add DSB to ensure visibility of System register writes */
370 dsb();
Achin Gupta92712a52015-09-03 14:18:02 +0100371
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000372 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Manish V Badarkhe173c2962022-05-09 21:55:19 +0100373 assert(gicr_base != 0UL);
374
375 /*
376 * dsb() already issued previously after clearing the CPU group
377 * enabled, apply below workaround to toggle the "DPG*"
378 * bits of GICR_CTLR register for unblocking event.
379 */
380 gicv3_apply_errata_wa_2384374(gicr_base);
381
382 /* Mark the connected core as asleep */
Achin Gupta92712a52015-09-03 14:18:02 +0100383 gicv3_rdistif_mark_core_asleep(gicr_base);
384}
385
386/*******************************************************************************
387 * This function returns the id of the highest priority pending interrupt at
388 * the GIC cpu interface.
389 ******************************************************************************/
390unsigned int gicv3_get_pending_interrupt_id(void)
391{
392 unsigned int id;
393
394 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100395 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
Achin Gupta92712a52015-09-03 14:18:02 +0100396
397 /*
398 * If the ID is special identifier corresponding to G1S or G1NS
399 * interrupt, then read the highest pending group 1 interrupt.
400 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100401 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) {
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100402 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100403 }
Achin Gupta92712a52015-09-03 14:18:02 +0100404
405 return id;
406}
407
408/*******************************************************************************
409 * This function returns the type of the highest priority pending interrupt at
410 * the GIC cpu interface. The return values can be one of the following :
411 * PENDING_G1S_INTID : The interrupt type is secure Group 1.
412 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1.
413 * 0 - 1019 : The interrupt type is secure Group 0.
414 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
415 * sufficient priority to be signaled
416 ******************************************************************************/
417unsigned int gicv3_get_pending_interrupt_type(void)
418{
419 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100420 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
Achin Gupta92712a52015-09-03 14:18:02 +0100421}
422
423/*******************************************************************************
Madhukar Pappireddyb5859d02023-08-03 14:17:54 -0500424 * This function returns the group that has been configured under by the
425 * interrupt controller for the given interrupt id i.e. either group0 or group1
426 * Secure / Non Secure. The return value can be one of the following :
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000427 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
428 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
429 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
Achin Gupta92712a52015-09-03 14:18:02 +0100430 * interrupt.
431 ******************************************************************************/
Madhukar Pappireddyb5859d02023-08-03 14:17:54 -0500432unsigned int gicv3_get_interrupt_group(unsigned int id, unsigned int proc_num)
Achin Gupta92712a52015-09-03 14:18:02 +0100433{
434 unsigned int igroup, grpmodr;
435 uintptr_t gicr_base;
Varun Wadekar61286d22023-03-08 16:47:38 +0000436 uintptr_t gicd_base;
Achin Gupta92712a52015-09-03 14:18:02 +0100437
438 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100439 assert(gicv3_driver_data != NULL);
Achin Gupta92712a52015-09-03 14:18:02 +0100440
441 /* Ensure the parameters are valid */
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100442 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID));
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000443 assert(proc_num < gicv3_driver_data->rdistif_num);
Achin Gupta92712a52015-09-03 14:18:02 +0100444
445 /* All LPI interrupts are Group 1 non secure */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100446 if (id >= MIN_LPI_ID) {
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000447 return INTR_GROUP1NS;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100448 }
Achin Gupta92712a52015-09-03 14:18:02 +0100449
Sona Mathew4a3811f2024-01-01 21:00:44 -0600450 if (!is_valid_interrupt(id)) {
451 panic();
452 }
453
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100454 /* Check interrupt ID */
Sona Mathew4a3811f2024-01-01 21:00:44 -0600455 if (IS_SGI_PPI(id)) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100456 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
Andrew F. Davis25a17a22018-08-30 14:30:54 -0500457 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharand7a901e2016-12-06 16:15:22 +0000458 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100459 igroup = gicr_get_igroupr(gicr_base, id);
460 grpmodr = gicr_get_igrpmodr(gicr_base, id);
Achin Gupta92712a52015-09-03 14:18:02 +0100461 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100462 /* SPIs: 32-1019, ESPIs: 4096-5119 */
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100463 assert(gicv3_driver_data->gicd_base != 0U);
Varun Wadekar61286d22023-03-08 16:47:38 +0000464 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base);
465 igroup = gicd_get_igroupr(gicd_base, id);
466 grpmodr = gicd_get_igrpmodr(gicd_base, id);
Achin Gupta92712a52015-09-03 14:18:02 +0100467 }
468
469 /*
470 * If the IGROUP bit is set, then it is a Group 1 Non secure
471 * interrupt
472 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100473 if (igroup != 0U) {
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000474 return INTR_GROUP1NS;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100475 }
Achin Gupta92712a52015-09-03 14:18:02 +0100476
477 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100478 if (grpmodr != 0U) {
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000479 return INTR_GROUP1S;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100480 }
Achin Gupta92712a52015-09-03 14:18:02 +0100481
482 /* Else it is a Group 0 Secure interrupt */
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000483 return INTR_GROUP0;
Achin Gupta92712a52015-09-03 14:18:02 +0100484}
Soby Mathew327548c2017-07-13 15:19:51 +0100485
486/*****************************************************************************
Soby Mathewf6f1a322017-07-18 16:12:45 +0100487 * Function to save and disable the GIC ITS register context. The power
488 * management of GIC ITS is implementation-defined and this function doesn't
489 * save any memory structures required to support ITS. As the sequence to save
490 * this state is implementation defined, it should be executed in platform
491 * specific code. Calling this function alone and then powering down the GIC and
492 * ITS without implementing the aforementioned platform specific code will
493 * corrupt the ITS state.
494 *
495 * This function must be invoked after the GIC CPU interface is disabled.
496 *****************************************************************************/
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100497void gicv3_its_save_disable(uintptr_t gits_base,
498 gicv3_its_ctx_t * const its_ctx)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100499{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100500 unsigned int i;
Soby Mathewf6f1a322017-07-18 16:12:45 +0100501
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100502 assert(gicv3_driver_data != NULL);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100503 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100504 assert(its_ctx != NULL);
505 assert(gits_base != 0U);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100506
507 its_ctx->gits_ctlr = gits_read_ctlr(gits_base);
508
509 /* Disable the ITS */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100510 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100511
512 /* Wait for quiescent state */
513 gits_wait_for_quiescent_bit(gits_base);
514
515 its_ctx->gits_cbaser = gits_read_cbaser(gits_base);
516 its_ctx->gits_cwriter = gits_read_cwriter(gits_base);
517
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100518 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) {
Soby Mathewf6f1a322017-07-18 16:12:45 +0100519 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100520 }
Soby Mathewf6f1a322017-07-18 16:12:45 +0100521}
522
523/*****************************************************************************
524 * Function to restore the GIC ITS register context. The power
525 * management of GIC ITS is implementation defined and this function doesn't
526 * restore any memory structures required to support ITS. The assumption is
527 * that these structures are in memory and are retained during system suspend.
528 *
529 * This must be invoked before the GIC CPU interface is enabled.
530 *****************************************************************************/
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100531void gicv3_its_restore(uintptr_t gits_base,
532 const gicv3_its_ctx_t * const its_ctx)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100533{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100534 unsigned int i;
Soby Mathewf6f1a322017-07-18 16:12:45 +0100535
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100536 assert(gicv3_driver_data != NULL);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100537 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100538 assert(its_ctx != NULL);
539 assert(gits_base != 0U);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100540
541 /* Assert that the GITS is disabled and quiescent */
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100542 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
543 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100544
545 gits_write_cbaser(gits_base, its_ctx->gits_cbaser);
546 gits_write_cwriter(gits_base, its_ctx->gits_cwriter);
547
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100548 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) {
Soby Mathewf6f1a322017-07-18 16:12:45 +0100549 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100550 }
Soby Mathewf6f1a322017-07-18 16:12:45 +0100551
552 /* Restore the ITS CTLR but leave the ITS disabled */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100553 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100554}
555
556/*****************************************************************************
Soby Mathew327548c2017-07-13 15:19:51 +0100557 * Function to save the GIC Redistributor register context. This function
558 * must be invoked after CPU interface disable and prior to Distributor save.
559 *****************************************************************************/
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100560void gicv3_rdistif_save(unsigned int proc_num,
561 gicv3_redist_ctx_t * const rdist_ctx)
Soby Mathew327548c2017-07-13 15:19:51 +0100562{
563 uintptr_t gicr_base;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100564 unsigned int i, ppi_regs_num, regs_num;
Soby Mathew327548c2017-07-13 15:19:51 +0100565
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100566 assert(gicv3_driver_data != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100567 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100568 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100569 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100570 assert(rdist_ctx != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100571
572 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
573
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100574#if GIC_EXT_INTID
575 /* Calculate number of PPI registers */
576 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
577 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
578 /* All other values except PPInum [0-2] are reserved */
579 if (ppi_regs_num > 3U) {
580 ppi_regs_num = 1U;
581 }
582#else
583 ppi_regs_num = 1U;
584#endif
Soby Mathew327548c2017-07-13 15:19:51 +0100585 /*
586 * Wait for any write to GICR_CTLR to complete before trying to save any
587 * state.
588 */
589 gicr_wait_for_pending_write(gicr_base);
590
591 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base);
592
593 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base);
594 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base);
595
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100596 /* 32 interrupt IDs per register */
597 for (i = 0U; i < ppi_regs_num; ++i) {
598 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i);
599 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i);
600 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i);
601 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i);
602 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i);
Soby Mathew327548c2017-07-13 15:19:51 +0100603 }
604
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100605 /* 16 interrupt IDs per GICR_ICFGR register */
606 regs_num = ppi_regs_num << 1;
607 for (i = 0U; i < regs_num; ++i) {
608 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i);
609 }
610
611 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base);
612
613 /* 4 interrupt IDs per GICR_IPRIORITYR register */
614 regs_num = ppi_regs_num << 3;
615 for (i = 0U; i < regs_num; ++i) {
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100616 rdist_ctx->gicr_ipriorityr[i] =
617 gicr_ipriorityr_read(gicr_base, i);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100618 }
Soby Mathew327548c2017-07-13 15:19:51 +0100619
620 /*
621 * Call the pre-save hook that implements the IMP DEF sequence that may
622 * be required on some GIC implementations. As this may need to access
623 * the Redistributor registers, we pass it proc_num.
624 */
625 gicv3_distif_pre_save(proc_num);
626}
627
628/*****************************************************************************
629 * Function to restore the GIC Redistributor register context. We disable
630 * LPI and per-cpu interrupts before we start restore of the Redistributor.
631 * This function must be invoked after Distributor restore but prior to
632 * CPU interface enable. The pending and active interrupts are restored
633 * after the interrupts are fully configured and enabled.
634 *****************************************************************************/
635void gicv3_rdistif_init_restore(unsigned int proc_num,
636 const gicv3_redist_ctx_t * const rdist_ctx)
637{
638 uintptr_t gicr_base;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100639 unsigned int i, ppi_regs_num, regs_num;
Soby Mathew327548c2017-07-13 15:19:51 +0100640
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100641 assert(gicv3_driver_data != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100642 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100643 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100644 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100645 assert(rdist_ctx != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100646
647 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
648
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100649#if GIC_EXT_INTID
650 /* Calculate number of PPI registers */
651 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >>
652 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1;
653 /* All other values except PPInum [0-2] are reserved */
654 if (ppi_regs_num > 3U) {
655 ppi_regs_num = 1U;
656 }
657#else
658 ppi_regs_num = 1U;
659#endif
Soby Mathew327548c2017-07-13 15:19:51 +0100660 /* Power on redistributor */
661 gicv3_rdistif_on(proc_num);
662
663 /*
664 * Call the post-restore hook that implements the IMP DEF sequence that
665 * may be required on some GIC implementations. As this may need to
666 * access the Redistributor registers, we pass it proc_num.
667 */
668 gicv3_distif_post_restore(proc_num);
669
670 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100671 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them.
672 * This is a more scalable approach as it avoids clearing the enable
673 * bits in the GICD_CTLR.
Soby Mathew327548c2017-07-13 15:19:51 +0100674 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100675 for (i = 0U; i < ppi_regs_num; ++i) {
676 gicr_write_icenabler(gicr_base, i, ~0U);
677 }
678
Soby Mathew327548c2017-07-13 15:19:51 +0100679 /* Wait for pending writes to GICR_ICENABLER */
680 gicr_wait_for_pending_write(gicr_base);
681
682 /*
683 * Disable the LPIs to avoid unpredictable behavior when writing to
684 * GICR_PROPBASER and GICR_PENDBASER.
685 */
686 gicr_write_ctlr(gicr_base,
687 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT));
688
689 /* Restore registers' content */
690 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser);
691 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser);
692
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100693 /* 32 interrupt IDs per register */
694 for (i = 0U; i < ppi_regs_num; ++i) {
695 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i);
696 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i);
697 }
698
699 /* 4 interrupt IDs per GICR_IPRIORITYR register */
700 regs_num = ppi_regs_num << 3;
701 for (i = 0U; i < regs_num; ++i) {
Alexei Fedorovc7510c52020-04-07 18:16:18 +0100702 gicr_ipriorityr_write(gicr_base, i,
703 rdist_ctx->gicr_ipriorityr[i]);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100704 }
Soby Mathew327548c2017-07-13 15:19:51 +0100705
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100706 /* 16 interrupt IDs per GICR_ICFGR register */
707 regs_num = ppi_regs_num << 1;
708 for (i = 0U; i < regs_num; ++i) {
709 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i);
Soby Mathew327548c2017-07-13 15:19:51 +0100710 }
711
Soby Mathew327548c2017-07-13 15:19:51 +0100712 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr);
713
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100714 /* Restore after group and priorities are set.
715 * 32 interrupt IDs per register
716 */
717 for (i = 0U; i < ppi_regs_num; ++i) {
718 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i);
719 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i);
720 }
Soby Mathew327548c2017-07-13 15:19:51 +0100721
722 /*
723 * Wait for all writes to the Distributor to complete before enabling
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100724 * the SGI and (E)PPIs.
Soby Mathew327548c2017-07-13 15:19:51 +0100725 */
726 gicr_wait_for_upstream_pending_write(gicr_base);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100727
728 /* 32 interrupt IDs per GICR_ISENABLER register */
729 for (i = 0U; i < ppi_regs_num; ++i) {
730 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i);
731 }
Soby Mathew327548c2017-07-13 15:19:51 +0100732
733 /*
734 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case
735 * the first write to GICR_CTLR was still in flight (this write only
736 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this
737 * bit).
738 */
739 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr);
740 gicr_wait_for_pending_write(gicr_base);
741}
742
743/*****************************************************************************
744 * Function to save the GIC Distributor register context. This function
745 * must be invoked after CPU interface disable and Redistributor save.
746 *****************************************************************************/
747void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
748{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100749 assert(gicv3_driver_data != NULL);
750 assert(gicv3_driver_data->gicd_base != 0U);
Soby Mathew327548c2017-07-13 15:19:51 +0100751 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100752 assert(dist_ctx != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100753
754 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
Heyi Guo79bc7a72021-01-20 19:05:51 +0800755 unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100756#if GIC_EXT_INTID
Heyi Guo79bc7a72021-01-20 19:05:51 +0800757 unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100758#endif
Heyi Guo79bc7a72021-01-20 19:05:51 +0800759
Soby Mathew327548c2017-07-13 15:19:51 +0100760 /* Wait for pending write to complete */
761 gicd_wait_for_pending_write(gicd_base);
762
763 /* Save the GICD_CTLR */
764 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base);
765
Alexei Fedorov68f26882019-09-13 15:47:13 +0100766 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100767 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP);
768
769 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */
770 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP);
Soby Mathew327548c2017-07-13 15:19:51 +0100771
Alexei Fedorov68f26882019-09-13 15:47:13 +0100772 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100773 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE);
774
775 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */
776 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE);
Soby Mathew327548c2017-07-13 15:19:51 +0100777
Alexei Fedorov68f26882019-09-13 15:47:13 +0100778 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100779 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND);
780
781 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */
782 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND);
Soby Mathew327548c2017-07-13 15:19:51 +0100783
Alexei Fedorov68f26882019-09-13 15:47:13 +0100784 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100785 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE);
786
787 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */
788 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE);
Soby Mathew327548c2017-07-13 15:19:51 +0100789
Alexei Fedorov68f26882019-09-13 15:47:13 +0100790 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100791 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY);
792
793 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */
794 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY);
Soby Mathew327548c2017-07-13 15:19:51 +0100795
Alexei Fedorov68f26882019-09-13 15:47:13 +0100796 /* Save GICD_ICFGR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100797 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG);
798
799 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */
800 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG);
Soby Mathew327548c2017-07-13 15:19:51 +0100801
Alexei Fedorov68f26882019-09-13 15:47:13 +0100802 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100803 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD);
804
805 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */
806 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD);
Soby Mathew327548c2017-07-13 15:19:51 +0100807
Alexei Fedorov68f26882019-09-13 15:47:13 +0100808 /* Save GICD_NSACR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100809 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC);
810
811 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */
812 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC);
Soby Mathew327548c2017-07-13 15:19:51 +0100813
Alexei Fedorov68f26882019-09-13 15:47:13 +0100814 /* Save GICD_IROUTER for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100815 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE);
816
817 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */
818 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE);
Soby Mathew327548c2017-07-13 15:19:51 +0100819
820 /*
821 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when
822 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3
823 * driver.
824 */
825}
826
827/*****************************************************************************
828 * Function to restore the GIC Distributor register context. We disable G0, G1S
829 * and G1NS interrupt groups before we start restore of the Distributor. This
830 * function must be invoked prior to Redistributor restore and CPU interface
831 * enable. The pending and active interrupts are restored after the interrupts
832 * are fully configured and enabled.
833 *****************************************************************************/
834void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
835{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100836 assert(gicv3_driver_data != NULL);
837 assert(gicv3_driver_data->gicd_base != 0U);
Soby Mathew327548c2017-07-13 15:19:51 +0100838 assert(IS_IN_EL3());
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100839 assert(dist_ctx != NULL);
Soby Mathew327548c2017-07-13 15:19:51 +0100840
841 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
842
843 /*
844 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
845 * the ARE_S bit. The Distributor might generate a system error
846 * otherwise.
847 */
848 gicd_clr_ctlr(gicd_base,
849 CTLR_ENABLE_G0_BIT |
850 CTLR_ENABLE_G1S_BIT |
851 CTLR_ENABLE_G1NS_BIT,
852 RWP_TRUE);
853
854 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
855 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
856
Heyi Guo79bc7a72021-01-20 19:05:51 +0800857 unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100858#if GIC_EXT_INTID
Heyi Guo79bc7a72021-01-20 19:05:51 +0800859 unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100860#endif
Alexei Fedorov68f26882019-09-13 15:47:13 +0100861 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100862 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP);
863
864 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */
865 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP);
Soby Mathew327548c2017-07-13 15:19:51 +0100866
Alexei Fedorov68f26882019-09-13 15:47:13 +0100867 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100868 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY);
869
870 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */
871 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY);
Soby Mathew327548c2017-07-13 15:19:51 +0100872
Alexei Fedorov68f26882019-09-13 15:47:13 +0100873 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100874 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG);
875
876 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */
877 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG);
Soby Mathew327548c2017-07-13 15:19:51 +0100878
Alexei Fedorov68f26882019-09-13 15:47:13 +0100879 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100880 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD);
881
882 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */
883 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD);
Soby Mathew327548c2017-07-13 15:19:51 +0100884
Alexei Fedorov68f26882019-09-13 15:47:13 +0100885 /* Restore GICD_NSACR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100886 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC);
887
888 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */
889 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC);
Soby Mathew327548c2017-07-13 15:19:51 +0100890
Alexei Fedorov68f26882019-09-13 15:47:13 +0100891 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100892 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE);
893
894 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */
895 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE);
Soby Mathew327548c2017-07-13 15:19:51 +0100896
897 /*
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100898 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after
899 * the interrupts are configured.
Soby Mathew327548c2017-07-13 15:19:51 +0100900 */
901
Alexei Fedorov68f26882019-09-13 15:47:13 +0100902 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100903 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE);
904
905 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */
906 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE);
Soby Mathew327548c2017-07-13 15:19:51 +0100907
Alexei Fedorov68f26882019-09-13 15:47:13 +0100908 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100909 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND);
910
911 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */
912 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND);
Soby Mathew327548c2017-07-13 15:19:51 +0100913
Alexei Fedorov68f26882019-09-13 15:47:13 +0100914 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100915 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE);
916
917 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */
918 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE);
Soby Mathew327548c2017-07-13 15:19:51 +0100919
920 /* Restore the GICD_CTLR */
921 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr);
922 gicd_wait_for_pending_write(gicd_base);
Soby Mathew327548c2017-07-13 15:19:51 +0100923}
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100924
925/*******************************************************************************
926 * This function gets the priority of the interrupt the processor is currently
927 * servicing.
928 ******************************************************************************/
929unsigned int gicv3_get_running_priority(void)
930{
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100931 return (unsigned int)read_icc_rpr_el1();
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100932}
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100933
934/*******************************************************************************
935 * This function checks if the interrupt identified by id is active (whether the
936 * state is either active, or active and pending). The proc_num is used if the
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100937 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100938 * interface.
939 ******************************************************************************/
940unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
941{
Varun Wadekar61286d22023-03-08 16:47:38 +0000942 uintptr_t gicd_base;
943
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100944 assert(gicv3_driver_data != NULL);
945 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100946 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100947 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100948
Sona Mathew4a3811f2024-01-01 21:00:44 -0600949 if (!is_valid_interrupt(id)) {
950 panic();
951 }
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100952 /* Check interrupt ID */
Sona Mathew4a3811f2024-01-01 21:00:44 -0600953 if (IS_SGI_PPI(id)) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100954 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
955 return gicr_get_isactiver(
956 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100957 }
958
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100959 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Varun Wadekar61286d22023-03-08 16:47:38 +0000960 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base);
961 return gicd_get_isactiver(gicd_base, id);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100962}
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100963
964/*******************************************************************************
965 * This function enables the interrupt identified by id. The proc_num
966 * is used if the interrupt is SGI or PPI, and programs the corresponding
967 * Redistributor interface.
968 ******************************************************************************/
969void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
970{
Varun Wadekar61286d22023-03-08 16:47:38 +0000971 uintptr_t gicd_base;
972
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100973 assert(gicv3_driver_data != NULL);
974 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100975 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100976 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100977
978 /*
979 * Ensure that any shared variable updates depending on out of band
980 * interrupt trigger are observed before enabling interrupt.
981 */
982 dsbishst();
Sona Mathew4a3811f2024-01-01 21:00:44 -0600983 if (!is_valid_interrupt(id)) {
984 panic();
985 }
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100986 /* Check interrupt ID */
Sona Mathew4a3811f2024-01-01 21:00:44 -0600987 if (IS_SGI_PPI(id)) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100988 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
989 gicr_set_isenabler(
990 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100991 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +0100992 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Varun Wadekar61286d22023-03-08 16:47:38 +0000993 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base);
994 gicd_set_isenabler(gicd_base, id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100995 }
996}
997
998/*******************************************************************************
999 * This function disables the interrupt identified by id. The proc_num
1000 * is used if the interrupt is SGI or PPI, and programs the corresponding
1001 * Redistributor interface.
1002 ******************************************************************************/
1003void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num)
1004{
Varun Wadekar61286d22023-03-08 16:47:38 +00001005 uintptr_t gicd_base;
1006
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001007 assert(gicv3_driver_data != NULL);
1008 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001009 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001010 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001011
1012 /*
1013 * Disable interrupt, and ensure that any shared variable updates
1014 * depending on out of band interrupt trigger are observed afterwards.
1015 */
Sona Mathew4a3811f2024-01-01 21:00:44 -06001016 if (!is_valid_interrupt(id)) {
1017 panic();
1018 }
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001019 /* Check interrupt ID */
Sona Mathew4a3811f2024-01-01 21:00:44 -06001020 if (IS_SGI_PPI(id)) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001021 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1022 gicr_set_icenabler(
1023 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001024
1025 /* Write to clear enable requires waiting for pending writes */
1026 gicr_wait_for_pending_write(
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001027 gicv3_driver_data->rdistif_base_addrs[proc_num]);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001028 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001029 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Varun Wadekar61286d22023-03-08 16:47:38 +00001030 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base);
1031 gicd_set_icenabler(gicd_base, id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001032
1033 /* Write to clear enable requires waiting for pending writes */
Varun Wadekar61286d22023-03-08 16:47:38 +00001034 gicd_wait_for_pending_write(gicd_base);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +01001035 }
1036
1037 dsbishst();
1038}
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001039
1040/*******************************************************************************
1041 * This function sets the interrupt priority as supplied for the given interrupt
1042 * id.
1043 ******************************************************************************/
1044void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
1045 unsigned int priority)
1046{
1047 uintptr_t gicr_base;
Varun Wadekar61286d22023-03-08 16:47:38 +00001048 uintptr_t gicd_base;
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001049
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001050 assert(gicv3_driver_data != NULL);
1051 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001052 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001053 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001054
Sona Mathew4a3811f2024-01-01 21:00:44 -06001055 if (!is_valid_interrupt(id)) {
1056 panic();
1057 }
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001058 /* Check interrupt ID */
Sona Mathew4a3811f2024-01-01 21:00:44 -06001059 if (IS_SGI_PPI(id)) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001060 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001061 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
1062 gicr_set_ipriorityr(gicr_base, id, priority);
1063 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001064 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Varun Wadekar61286d22023-03-08 16:47:38 +00001065 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base);
1066 gicd_set_ipriorityr(gicd_base, id, priority);
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +01001067 }
1068}
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001069
1070/*******************************************************************************
1071 * This function assigns group for the interrupt identified by id. The proc_num
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001072 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001073 * Redistributor interface. The group can be any of GICV3_INTR_GROUP*
1074 ******************************************************************************/
Madhukar Pappireddyb5859d02023-08-03 14:17:54 -05001075void gicv3_set_interrupt_group(unsigned int id, unsigned int proc_num,
1076 unsigned int group)
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001077{
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001078 bool igroup = false, grpmod = false;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001079 uintptr_t gicr_base;
Varun Wadekar61286d22023-03-08 16:47:38 +00001080 uintptr_t gicd_base;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001081
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001082 assert(gicv3_driver_data != NULL);
1083 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001084 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001085 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001086
Madhukar Pappireddyb5859d02023-08-03 14:17:54 -05001087 switch (group) {
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001088 case INTR_GROUP1S:
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001089 igroup = false;
1090 grpmod = true;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001091 break;
1092 case INTR_GROUP0:
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001093 igroup = false;
1094 grpmod = false;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001095 break;
1096 case INTR_GROUP1NS:
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001097 igroup = true;
1098 grpmod = false;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001099 break;
1100 default:
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001101 assert(false);
Jonathan Wright39b42212018-03-13 15:24:29 +00001102 break;
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001103 }
1104
Sona Mathew4a3811f2024-01-01 21:00:44 -06001105 if (!is_valid_interrupt(id)) {
1106 panic();
1107 }
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001108 /* Check interrupt ID */
Sona Mathew4a3811f2024-01-01 21:00:44 -06001109 if (IS_SGI_PPI(id)) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001110 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001111 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001112
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001113 igroup ? gicr_set_igroupr(gicr_base, id) :
1114 gicr_clr_igroupr(gicr_base, id);
1115 grpmod ? gicr_set_igrpmodr(gicr_base, id) :
1116 gicr_clr_igrpmodr(gicr_base, id);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001117 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001118 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
1119
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001120 /* Serialize read-modify-write to Distributor registers */
1121 spin_lock(&gic_lock);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001122
Varun Wadekar61286d22023-03-08 16:47:38 +00001123 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base);
1124
1125 igroup ? gicd_set_igroupr(gicd_base, id) :
1126 gicd_clr_igroupr(gicd_base, id);
1127 grpmod ? gicd_set_igrpmodr(gicd_base, id) :
1128 gicd_clr_igrpmodr(gicd_base, id);
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001129
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +01001130 spin_unlock(&gic_lock);
1131 }
1132}
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +01001133
1134/*******************************************************************************
Florian Lugoud4e25032021-09-08 12:40:24 +02001135 * This function raises the specified SGI of the specified group.
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +01001136 *
1137 * The target parameter must be a valid MPIDR in the system.
1138 ******************************************************************************/
Florian Lugoud4e25032021-09-08 12:40:24 +02001139void gicv3_raise_sgi(unsigned int sgi_num, gicv3_irq_group_t group,
1140 u_register_t target)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +01001141{
1142 unsigned int tgt, aff3, aff2, aff1, aff0;
1143 uint64_t sgi_val;
1144
1145 /* Verify interrupt number is in the SGI range */
1146 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID));
1147
1148 /* Extract affinity fields from target */
1149 aff0 = MPIDR_AFFLVL0_VAL(target);
1150 aff1 = MPIDR_AFFLVL1_VAL(target);
1151 aff2 = MPIDR_AFFLVL2_VAL(target);
1152 aff3 = MPIDR_AFFLVL3_VAL(target);
1153
1154 /*
1155 * Make target list from affinity 0, and ensure GICv3 SGI can target
1156 * this PE.
1157 */
1158 assert(aff0 < GICV3_MAX_SGI_TARGETS);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001159 tgt = BIT_32(aff0);
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +01001160
1161 /* Raise SGI to PE specified by its affinity */
1162 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF,
1163 tgt);
1164
1165 /*
1166 * Ensure that any shared variable updates depending on out of band
1167 * interrupt trigger are observed before raising SGI.
1168 */
1169 dsbishst();
Florian Lugoud4e25032021-09-08 12:40:24 +02001170
1171 switch (group) {
1172 case GICV3_G0:
1173 write_icc_sgi0r_el1(sgi_val);
1174 break;
1175 case GICV3_G1NS:
1176 write_icc_asgi1r(sgi_val);
1177 break;
1178 case GICV3_G1S:
1179 write_icc_sgi1r(sgi_val);
1180 break;
1181 default:
1182 assert(false);
1183 break;
1184 }
1185
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +01001186 isb();
1187}
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001188
1189/*******************************************************************************
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001190 * This function sets the interrupt routing for the given (E)SPI interrupt id.
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001191 * The interrupt routing is specified in routing mode and mpidr.
1192 *
1193 * The routing mode can be either of:
1194 * - GICV3_IRM_ANY
1195 * - GICV3_IRM_PE
1196 *
1197 * The mpidr is the affinity of the PE to which the interrupt will be routed,
1198 * and is ignored for routing mode GICV3_IRM_ANY.
1199 ******************************************************************************/
1200void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr)
1201{
1202 unsigned long long aff;
1203 uint64_t router;
Varun Wadekar61286d22023-03-08 16:47:38 +00001204 uintptr_t gicd_base;
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001205
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001206 assert(gicv3_driver_data != NULL);
1207 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001208
1209 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE));
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001210
1211 assert(IS_SPI(id));
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001212
1213 aff = gicd_irouter_val_from_mpidr(mpidr, irm);
Varun Wadekar61286d22023-03-08 16:47:38 +00001214 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base);
1215 gicd_write_irouter(gicd_base, id, aff);
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001216
1217 /*
1218 * In implementations that do not require 1 of N distribution of SPIs,
1219 * IRM might be RAZ/WI. Read back and verify IRM bit.
1220 */
1221 if (irm == GICV3_IRM_ANY) {
Varun Wadekar61286d22023-03-08 16:47:38 +00001222 router = gicd_read_irouter(gicd_base, id);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001223 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) {
Jeenu Viswambharandce70b32017-09-22 08:32:09 +01001224 ERROR("GICv3 implementation doesn't support routing ANY\n");
1225 panic();
1226 }
1227 }
1228}
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001229
1230/*******************************************************************************
1231 * This function clears the pending status of an interrupt identified by id.
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001232 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001233 * corresponding Redistributor interface.
1234 ******************************************************************************/
1235void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
1236{
Varun Wadekar61286d22023-03-08 16:47:38 +00001237 uintptr_t gicd_base;
1238
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001239 assert(gicv3_driver_data != NULL);
1240 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001241 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001242 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001243
1244 /*
1245 * Clear pending interrupt, and ensure that any shared variable updates
1246 * depending on out of band interrupt trigger are observed afterwards.
1247 */
Sona Mathew4a3811f2024-01-01 21:00:44 -06001248 if (!is_valid_interrupt(id)) {
1249 panic();
1250 }
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001251 /* Check interrupt ID */
Sona Mathew4a3811f2024-01-01 21:00:44 -06001252 if (IS_SGI_PPI(id)) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001253 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1254 gicr_set_icpendr(
Sona Mathew4a3811f2024-01-01 21:00:44 -06001255 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001256 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001257 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Varun Wadekar61286d22023-03-08 16:47:38 +00001258 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base);
1259 gicd_set_icpendr(gicd_base, id);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001260 }
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001261
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001262 dsbishst();
1263}
1264
1265/*******************************************************************************
1266 * This function sets the pending status of an interrupt identified by id.
1267 * The proc_num is used if the interrupt is SGI or PPI and programs the
1268 * corresponding Redistributor interface.
1269 ******************************************************************************/
1270void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num)
1271{
Varun Wadekar61286d22023-03-08 16:47:38 +00001272 uintptr_t gicd_base;
1273
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001274 assert(gicv3_driver_data != NULL);
1275 assert(gicv3_driver_data->gicd_base != 0U);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001276 assert(proc_num < gicv3_driver_data->rdistif_num);
Antonio Nino Diazca994e72018-08-21 10:02:33 +01001277 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001278
1279 /*
1280 * Ensure that any shared variable updates depending on out of band
1281 * interrupt trigger are observed before setting interrupt pending.
1282 */
1283 dsbishst();
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001284
Sona Mathew4a3811f2024-01-01 21:00:44 -06001285 if (!is_valid_interrupt(id)) {
1286 panic();
1287 }
1288
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001289 /* Check interrupt ID */
Sona Mathew4a3811f2024-01-01 21:00:44 -06001290 if (IS_SGI_PPI(id)) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001291 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */
1292 gicr_set_ispendr(
1293 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001294 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001295 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */
Varun Wadekar61286d22023-03-08 16:47:38 +00001296 gicd_base = gicv3_get_multichip_base(id, gicv3_driver_data->gicd_base);
1297 gicd_set_ispendr(gicd_base, id);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +01001298 }
1299}
Jeenu Viswambharan62505072017-09-22 08:32:09 +01001300
1301/*******************************************************************************
1302 * This function sets the PMR register with the supplied value. Returns the
1303 * original PMR.
1304 ******************************************************************************/
1305unsigned int gicv3_set_pmr(unsigned int mask)
1306{
1307 unsigned int old_mask;
1308
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001309 old_mask = (unsigned int)read_icc_pmr_el1();
Jeenu Viswambharan62505072017-09-22 08:32:09 +01001310
1311 /*
1312 * Order memory updates w.r.t. PMR write, and ensure they're visible
1313 * before potential out of band interrupt trigger because of PMR update.
1314 * PMR system register writes are self-synchronizing, so no ISB required
1315 * thereafter.
1316 */
1317 dsbishst();
1318 write_icc_pmr_el1(mask);
1319
1320 return old_mask;
1321}
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001322
1323/*******************************************************************************
Arvind Ram Prakash579a23c2024-02-05 16:19:37 -06001324 * This function restores the PMR register to old value and also triggers
1325 * gicv3_apply_errata_wa_2384374() that flushes the GIC buffer allowing any
1326 * pending interrupts to processed. Returns the original PMR.
1327 ******************************************************************************/
1328unsigned int gicv3_deactivate_priority(unsigned int mask)
1329{
1330
1331 unsigned int old_mask, proc_num;
1332 uintptr_t gicr_base;
1333
1334 old_mask = gicv3_set_pmr(mask);
1335
1336 proc_num = plat_my_core_pos();
1337 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
1338 assert(gicr_base != 0UL);
1339
1340 /* Add DSB to ensure visibility of System register writes */
1341 dsb();
1342
1343 gicv3_apply_errata_wa_2384374(gicr_base);
1344
1345 return old_mask;
1346}
1347
1348/*******************************************************************************
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001349 * This function delegates the responsibility of discovering the corresponding
1350 * Redistributor frames to each CPU itself. It is a modified version of
1351 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform
1352 * unlike the previous way in which only the Primary CPU did the discovery of
1353 * all the Redistributor frames for every CPU. It also handles the scenario in
1354 * which the frames of various CPUs are not contiguous in physical memory.
1355 ******************************************************************************/
1356int gicv3_rdistif_probe(const uintptr_t gicr_frame)
1357{
Heyi Guo3a579ae2020-05-19 11:50:40 +08001358 u_register_t mpidr, mpidr_self;
1359 unsigned int proc_num;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001360 uint64_t typer_val;
1361 uintptr_t rdistif_base;
1362 bool gicr_frame_found = false;
1363
1364 assert(gicv3_driver_data->gicr_base == 0U);
1365
Channagoud kadabia037d972022-11-29 16:03:47 -08001366 if (plat_can_cmo()) {
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001367 /* Ensure this function is called with Data Cache enabled */
1368#ifndef __aarch64__
Channagoud kadabia037d972022-11-29 16:03:47 -08001369 assert((read_sctlr() & SCTLR_C_BIT) != 0U);
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001370#else
Channagoud kadabia037d972022-11-29 16:03:47 -08001371 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001372#endif /* !__aarch64__ */
Channagoud kadabia037d972022-11-29 16:03:47 -08001373 }
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001374
Heyi Guo3a579ae2020-05-19 11:50:40 +08001375 mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001376 rdistif_base = gicr_frame;
1377 do {
1378 typer_val = gicr_read_typer(rdistif_base);
Heyi Guo3a579ae2020-05-19 11:50:40 +08001379 mpidr = mpidr_from_gicr_typer(typer_val);
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001380 if (gicv3_driver_data->mpidr_to_core_pos != NULL) {
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001381 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr);
1382 } else {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001383 proc_num = (unsigned int)(typer_val >>
1384 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK;
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001385 }
Heyi Guo3a579ae2020-05-19 11:50:40 +08001386 if (mpidr == mpidr_self) {
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001387 /* The base address doesn't need to be initialized on
1388 * every warm boot.
1389 */
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001390 if (gicv3_driver_data->rdistif_base_addrs[proc_num]
1391 != 0U) {
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001392 return 0;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001393 }
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001394 gicv3_driver_data->rdistif_base_addrs[proc_num] =
1395 rdistif_base;
1396 gicr_frame_found = true;
1397 break;
1398 }
Andre Przywaraf70f4b92021-05-18 15:51:06 +01001399 rdistif_base += gicv3_redist_size(typer_val);
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001400 } while ((typer_val & TYPER_LAST_BIT) == 0U);
1401
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001402 if (!gicr_frame_found) {
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001403 return -1;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001404 }
Madhukar Pappireddy5fd1f9d2019-05-15 18:25:41 -05001405
1406 /*
1407 * Flush the driver data to ensure coherency. This is
1408 * not required if platform has HW_ASSISTED_COHERENCY
1409 * enabled.
1410 */
1411#if !HW_ASSISTED_COHERENCY
1412 /*
1413 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
1414 */
1415 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]),
1416 sizeof(*(gicv3_driver_data->rdistif_base_addrs)));
1417#endif
1418 return 0; /* Found matching GICR frame */
1419}
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001420
1421/******************************************************************************
Sona Mathew4a3811f2024-01-01 21:00:44 -06001422 * This function checks the interrupt ID and returns true for SGIs, (E)PPIs
1423 * and (E)SPIs IDs. Any interrupt ID outside the range is invalid and returns
1424 * false.
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001425 *****************************************************************************/
Sona Mathew4a3811f2024-01-01 21:00:44 -06001426static bool is_valid_interrupt(unsigned int id)
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001427{
Sona Mathew4a3811f2024-01-01 21:00:44 -06001428 /* Valid interrupts:
1429 * SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119
1430 * SPIs: 32-1019, ESPIs: 4096-5119
1431 */
1432 if ((IS_SGI_PPI(id)) || (IS_SPI(id))) {
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001433 return true;
1434 }
1435
Sona Mathew4a3811f2024-01-01 21:00:44 -06001436 return false;
Alexei Fedorova6e6ae02020-04-06 16:27:54 +01001437}