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git01.mediatek.com / filogic / atf / 24afcdd8fa016bb8b2a982b9ff1416eaacdbe576 / . / plat / nvidia / tegra / include / platform_def.h
blob: 958a3f9721e3469e0dd5fd952bb9378cdecb63b6 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
Steven Kao0cb8b332018-02-09 20:50:02 +0800[diff] [blame]2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar8e15d172018-12-21 10:55:42 -0800[diff] [blame]3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]4 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]5 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]6 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]8#ifndef PLATFORM_DEF_H
9#define PLATFORM_DEF_H
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]10
11#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]12#include <lib/utils_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]13
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]14#include <tegra_def.h>
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]15
Kalyani Chidambaram425155a2018-12-19 11:06:14 -0800[diff] [blame]16/*******************************************************************************
17 * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1
18 ******************************************************************************/
19#if !SEPARATE_CODE_AND_RODATA
20#error "SEPARATE_CODE_AND_RODATA should be set to 1"
21#endif
22
Varun Wadekar5fb2c5d2018-12-21 10:55:42 -0800[diff] [blame]23/*
24 * Platform binary types for linking
25 */
26#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
27#define PLATFORM_LINKER_ARCH aarch64
28
Varun Wadekar8e15d172018-12-21 10:55:42 -0800[diff] [blame]29/*
30 * Platform binary types for linking
31 */
32#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
33#define PLATFORM_LINKER_ARCH aarch64
34
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]35/*******************************************************************************
36 * Generic platform constants
37 ******************************************************************************/
38
39/* Size of cacheable stacks */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]40#ifdef IMAGE_BL31
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]41#define PLATFORM_STACK_SIZE U(0x400)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]42#endif
43
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]44#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Varun Wadekar88c4d222015-08-12 09:24:50 +0530[diff] [blame]45#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
46 PLATFORM_MAX_CPUS_PER_CLUSTER)
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]47#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Anthony Zhou7534c202019-03-11 15:50:32 +0800[diff] [blame]48 PLATFORM_CLUSTER_COUNT + U(1))
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]49
50/*******************************************************************************
51 * Platform console related constants
52 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]53#define TEGRA_CONSOLE_BAUDRATE U(115200)
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800[diff] [blame]54#define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000)
55#define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]56
57/*******************************************************************************
58 * Platform memory map related constants
59 ******************************************************************************/
60/* Size of trusted dram */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]61#define TZDRAM_SIZE U(0x00400000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]62#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
63
64/*******************************************************************************
65 * BL31 specific defines.
66 ******************************************************************************/
67#define BL31_BASE TZDRAM_BASE
Varun Wadekar52a15982015-06-05 12:57:27 +0530[diff] [blame]68#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
69#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
70#define BL32_LIMIT TZDRAM_END
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]71
72/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]73 * Some data must be aligned on the biggest cache line size in the platform.
74 * This is known only to the platform as it might have a combination of
75 * integrated and external caches.
76 ******************************************************************************/
77#define CACHE_WRITEBACK_SHIFT 6
Kalyani Chidambaramdd2203b2018-12-14 11:36:43 -0800[diff] [blame]78#define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]79
Varun Wadekar396530b2019-03-01 10:18:35 -0800[diff] [blame]80/*******************************************************************************
81 * Dummy macros to compile io_storage support
82 ******************************************************************************/
83#define MAX_IO_DEVICES U(0)
84#define MAX_IO_HANDLES U(0)
85
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700[diff] [blame]86/*******************************************************************************
Varun Wadekarbef02f02020-04-17 19:09:21 -0700[diff] [blame]87 * Platforms macros to support SDEI
88 ******************************************************************************/
89#define TEGRA_SDEI_SGI_PRIVATE U(8)
90
91/*******************************************************************************
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700[diff] [blame]92 * Platform macros to support exception handling framework
93 ******************************************************************************/
94#define PLAT_PRI_BITS U(3)
David Pu70f65972019-03-18 15:14:49 -0700[diff] [blame]95#define PLAT_RAS_PRI U(0x10)
Varun Wadekarbef02f02020-04-17 19:09:21 -0700[diff] [blame]96#define PLAT_SDEI_CRITICAL_PRI U(0x20)
97#define PLAT_SDEI_NORMAL_PRI U(0x30)
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700[diff] [blame]98#define PLAT_TEGRA_WDT_PRIO U(0x40)
Kalyani Chidambaram425155a2018-12-19 11:06:14 -0800[diff] [blame]99
Sandeep Tripathy6da88e92020-08-26 19:54:41 +0530[diff] [blame]100#define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS,\
101 PLAT_TEGRA_WDT_PRIO)
102
Varun Wadekarbef02f02020-04-17 19:09:21 -0700[diff] [blame]103/*******************************************************************************
104 * SDEI events
105 ******************************************************************************/
106/* SDEI dynamic private event numbers */
107#define TEGRA_SDEI_DP_EVENT_0 U(100)
108#define TEGRA_SDEI_DP_EVENT_1 U(101)
109#define TEGRA_SDEI_DP_EVENT_2 U(102)
110
111/* SDEI dynamic shared event numbers */
112#define TEGRA_SDEI_DS_EVENT_0 U(200)
113#define TEGRA_SDEI_DS_EVENT_1 U(201)
114#define TEGRA_SDEI_DS_EVENT_2 U(202)
115
116/* SDEI explicit events */
117#define TEGRA_SDEI_EP_EVENT_0 U(300)
118#define TEGRA_SDEI_EP_EVENT_1 U(301)
119#define TEGRA_SDEI_EP_EVENT_2 U(302)
120#define TEGRA_SDEI_EP_EVENT_3 U(303)
121#define TEGRA_SDEI_EP_EVENT_4 U(304)
122#define TEGRA_SDEI_EP_EVENT_5 U(305)
123#define TEGRA_SDEI_EP_EVENT_6 U(306)
124#define TEGRA_SDEI_EP_EVENT_7 U(307)
125#define TEGRA_SDEI_EP_EVENT_8 U(308)
126#define TEGRA_SDEI_EP_EVENT_9 U(309)
127#define TEGRA_SDEI_EP_EVENT_10 U(310)
128#define TEGRA_SDEI_EP_EVENT_11 U(311)
129
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]130#endif /* PLATFORM_DEF_H */