blob: 6a507d481a1a7c287351be369531cad736f1f85d [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Varun Wadekarb5132322017-04-10 15:30:17 -07002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Varun Wadekarb316e242015-05-19 16:48:04 +05309
10#include <arch.h>
11#include <common_def.h>
Varun Wadekara78bb1b2015-08-07 10:03:00 +053012#include <tegra_def.h>
Varun Wadekar761ca732017-04-24 14:17:12 -070013#include <utils_def.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053014
15/*******************************************************************************
16 * Generic platform constants
17 ******************************************************************************/
18
19/* Size of cacheable stacks */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090020#ifdef IMAGE_BL31
Varun Wadekar761ca732017-04-24 14:17:12 -070021#define PLATFORM_STACK_SIZE U(0x400)
Varun Wadekarb316e242015-05-19 16:48:04 +053022#endif
23
Varun Wadekar761ca732017-04-24 14:17:12 -070024#define TEGRA_PRIMARY_CPU U(0x0)
Varun Wadekarb316e242015-05-19 16:48:04 +053025
Varun Wadekara78bb1b2015-08-07 10:03:00 +053026#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Varun Wadekar88c4d222015-08-12 09:24:50 +053027#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
28 PLATFORM_MAX_CPUS_PER_CLUSTER)
Varun Wadekara78bb1b2015-08-07 10:03:00 +053029#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Varun Wadekar88c4d222015-08-12 09:24:50 +053030 PLATFORM_CLUSTER_COUNT + 1)
Varun Wadekarb316e242015-05-19 16:48:04 +053031
32/*******************************************************************************
33 * Platform console related constants
34 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070035#define TEGRA_CONSOLE_BAUDRATE U(115200)
36#define TEGRA_BOOT_UART_CLK_IN_HZ U(408000000)
Varun Wadekarb316e242015-05-19 16:48:04 +053037
38/*******************************************************************************
39 * Platform memory map related constants
40 ******************************************************************************/
41/* Size of trusted dram */
Varun Wadekar761ca732017-04-24 14:17:12 -070042#define TZDRAM_SIZE U(0x00400000)
Varun Wadekarb316e242015-05-19 16:48:04 +053043#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
44
45/*******************************************************************************
46 * BL31 specific defines.
47 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070048#define BL31_SIZE U(0x40000)
Varun Wadekarb316e242015-05-19 16:48:04 +053049#define BL31_BASE TZDRAM_BASE
Varun Wadekar52a15982015-06-05 12:57:27 +053050#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
51#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
52#define BL32_LIMIT TZDRAM_END
Varun Wadekarb316e242015-05-19 16:48:04 +053053
54/*******************************************************************************
55 * Platform specific page table and MMU setup constants
56 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070057#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
58#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
Varun Wadekarb316e242015-05-19 16:48:04 +053059
60/*******************************************************************************
61 * Some data must be aligned on the biggest cache line size in the platform.
62 * This is known only to the platform as it might have a combination of
63 * integrated and external caches.
64 ******************************************************************************/
65#define CACHE_WRITEBACK_SHIFT 6
Varun Wadekar761ca732017-04-24 14:17:12 -070066#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
Varun Wadekarb316e242015-05-19 16:48:04 +053067
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000068#endif /* PLATFORM_DEF_H */