| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| Varun Wadekar | b513232 | 2017-04-10 15:30:17 -0700 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 9 | |
| 10 | #include <arch.h> |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 11 | #include <lib/utils_def.h> |
| 12 | #include <plat/common/common_def.h> |
| 13 | |
| Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 14 | #include <tegra_def.h> |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 15 | |
| 16 | /******************************************************************************* |
| 17 | * Generic platform constants |
| 18 | ******************************************************************************/ |
| 19 | |
| 20 | /* Size of cacheable stacks */ |
| Masahiro Yamada | 441bfdd | 2016-12-25 23:36:24 +0900 | [diff] [blame] | 21 | #ifdef IMAGE_BL31 |
| Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 22 | #define PLATFORM_STACK_SIZE U(0x400) |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 23 | #endif |
| 24 | |
| Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 25 | #define TEGRA_PRIMARY_CPU U(0x0) |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 26 | |
| Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 27 | #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 |
| Varun Wadekar | 88c4d22 | 2015-08-12 09:24:50 +0530 | [diff] [blame] | 28 | #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ |
| 29 | PLATFORM_MAX_CPUS_PER_CLUSTER) |
| Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 30 | #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ |
| Varun Wadekar | 88c4d22 | 2015-08-12 09:24:50 +0530 | [diff] [blame] | 31 | PLATFORM_CLUSTER_COUNT + 1) |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 32 | |
| 33 | /******************************************************************************* |
| 34 | * Platform console related constants |
| 35 | ******************************************************************************/ |
| Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 36 | #define TEGRA_CONSOLE_BAUDRATE U(115200) |
| Harvey Hsieh | 9e083c7 | 2017-04-10 16:20:32 +0800 | [diff] [blame^] | 37 | #define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000) |
| 38 | #define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000) |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 39 | |
| 40 | /******************************************************************************* |
| 41 | * Platform memory map related constants |
| 42 | ******************************************************************************/ |
| 43 | /* Size of trusted dram */ |
| Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 44 | #define TZDRAM_SIZE U(0x00400000) |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 45 | #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) |
| 46 | |
| 47 | /******************************************************************************* |
| 48 | * BL31 specific defines. |
| 49 | ******************************************************************************/ |
| Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 50 | #define BL31_SIZE U(0x40000) |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 51 | #define BL31_BASE TZDRAM_BASE |
| Varun Wadekar | 52a1598 | 2015-06-05 12:57:27 +0530 | [diff] [blame] | 52 | #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) |
| 53 | #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) |
| 54 | #define BL32_LIMIT TZDRAM_END |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 55 | |
| 56 | /******************************************************************************* |
| 57 | * Platform specific page table and MMU setup constants |
| 58 | ******************************************************************************/ |
| Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 59 | #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) |
| 60 | #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 61 | |
| 62 | /******************************************************************************* |
| 63 | * Some data must be aligned on the biggest cache line size in the platform. |
| 64 | * This is known only to the platform as it might have a combination of |
| 65 | * integrated and external caches. |
| 66 | ******************************************************************************/ |
| 67 | #define CACHE_WRITEBACK_SHIFT 6 |
| Varun Wadekar | 761ca73 | 2017-04-24 14:17:12 -0700 | [diff] [blame] | 68 | #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 69 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 70 | #endif /* PLATFORM_DEF_H */ |