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git01.mediatek.com / filogic / atf / 425155a261859077378ed11fb9b2e5c315dd4401 / . / plat / nvidia / tegra / include / platform_def.h
blob: 817f480a2351ccbf2faed90660c9ae2c1c46fdb7 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
Steven Kao0cb8b332018-02-09 20:50:02 +0800[diff] [blame]2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]9
10#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]11#include <lib/utils_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]12
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]13#include <tegra_def.h>
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]14
Kalyani Chidambaram425155a2018-12-19 11:06:14 -0800[diff] [blame^]15/*******************************************************************************
16 * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1
17 ******************************************************************************/
18#if !SEPARATE_CODE_AND_RODATA
19#error "SEPARATE_CODE_AND_RODATA should be set to 1"
20#endif
21
Varun Wadekar5fb2c5d2018-12-21 10:55:42 -0800[diff] [blame]22/*
23 * Platform binary types for linking
24 */
25#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
26#define PLATFORM_LINKER_ARCH aarch64
27
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]28/*******************************************************************************
29 * Generic platform constants
30 ******************************************************************************/
31
32/* Size of cacheable stacks */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]33#ifdef IMAGE_BL31
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]34#define PLATFORM_STACK_SIZE U(0x400)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]35#endif
36
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]37#define TEGRA_PRIMARY_CPU U(0x0)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]38
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]39#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Varun Wadekar88c4d222015-08-12 09:24:50 +0530[diff] [blame]40#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
41 PLATFORM_MAX_CPUS_PER_CLUSTER)
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]42#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Varun Wadekar88c4d222015-08-12 09:24:50 +0530[diff] [blame]43 PLATFORM_CLUSTER_COUNT + 1)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]44
45/*******************************************************************************
46 * Platform console related constants
47 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]48#define TEGRA_CONSOLE_BAUDRATE U(115200)
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800[diff] [blame]49#define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000)
50#define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]51
52/*******************************************************************************
53 * Platform memory map related constants
54 ******************************************************************************/
55/* Size of trusted dram */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]56#define TZDRAM_SIZE U(0x00400000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]57#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
58
59/*******************************************************************************
60 * BL31 specific defines.
61 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]62#define BL31_SIZE U(0x40000)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]63#define BL31_BASE TZDRAM_BASE
Varun Wadekar52a15982015-06-05 12:57:27 +0530[diff] [blame]64#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
65#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
66#define BL32_LIMIT TZDRAM_END
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]67
68/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]69 * Some data must be aligned on the biggest cache line size in the platform.
70 * This is known only to the platform as it might have a combination of
71 * integrated and external caches.
72 ******************************************************************************/
73#define CACHE_WRITEBACK_SHIFT 6
Kalyani Chidambaramdd2203b2018-12-14 11:36:43 -0800[diff] [blame]74#define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]75
Varun Wadekar396530b2019-03-01 10:18:35 -0800[diff] [blame]76/*******************************************************************************
77 * Dummy macros to compile io_storage support
78 ******************************************************************************/
79#define MAX_IO_DEVICES U(0)
80#define MAX_IO_HANDLES U(0)
81
Kalyani Chidambaram425155a2018-12-19 11:06:14 -0800[diff] [blame^]82
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]83#endif /* PLATFORM_DEF_H */