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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dimitris Papastamosa65841a2018-01-22 12:58:52 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01008#include <arch_helpers.h>
Dimitris Papastamosa65841a2018-01-22 12:58:52 +00009#include <arm_arch_svc.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <assert.h>
Soby Mathew96168382014-12-17 14:47:57 +000011#include <debug.h>
12#include <platform.h>
dp-arm3cac7862016-09-19 11:18:44 +010013#include <pmf.h>
14#include <runtime_instr.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000015#include <smccc.h>
Soby Mathew981487a2015-07-13 14:10:57 +010016#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010017#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
19/*******************************************************************************
20 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
21 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010022int psci_cpu_on(u_register_t target_cpu,
23 uintptr_t entrypoint,
24 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010025
26{
27 int rc;
Soby Mathew8595b872015-01-06 15:36:38 +000028 entry_point_info_t ep;
Achin Gupta4f6ad662013-10-25 09:08:21 +010029
30 /* Determine if the cpu exists of not */
Soby Mathew981487a2015-07-13 14:10:57 +010031 rc = psci_validate_mpidr(target_cpu);
32 if (rc != PSCI_E_SUCCESS)
Soby Mathew74e52a72014-10-02 16:56:51 +010033 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010034
Soby Mathewf1f97a12015-07-15 12:13:26 +010035 /* Validate the entry point and get the entry_point_info */
36 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew8595b872015-01-06 15:36:38 +000037 if (rc != PSCI_E_SUCCESS)
38 return rc;
39
Soby Mathew8595b872015-01-06 15:36:38 +000040 /*
Soby Mathew981487a2015-07-13 14:10:57 +010041 * To turn this cpu on, specify which power
Achin Gupta0959db52013-12-02 17:33:04 +000042 * levels need to be turned on
43 */
Sandrine Bailleux7497bff2016-04-25 09:28:43 +010044 return psci_cpu_on_start(target_cpu, &ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +010045}
46
47unsigned int psci_version(void)
48{
49 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
50}
51
52int psci_cpu_suspend(unsigned int power_state,
Soby Mathew011ca182015-07-29 17:05:03 +010053 uintptr_t entrypoint,
54 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010055{
56 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010057 unsigned int target_pwrlvl, is_power_down_state;
Soby Mathew8595b872015-01-06 15:36:38 +000058 entry_point_info_t ep;
Soby Mathew981487a2015-07-13 14:10:57 +010059 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
60 plat_local_state_t cpu_pd_state;
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Soby Mathew981487a2015-07-13 14:10:57 +010062 /* Validate the power_state parameter */
63 rc = psci_validate_power_state(power_state, &state_info);
64 if (rc != PSCI_E_SUCCESS) {
65 assert(rc == PSCI_E_INVALID_PARAMS);
66 return rc;
67 }
Vikram Kanigirif100f412014-04-01 19:26:26 +010068
Soby Mathew981487a2015-07-13 14:10:57 +010069 /*
70 * Get the value of the state type bit from the power state parameter.
71 */
72 is_power_down_state = psci_get_pstate_type(power_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +010073
Soby Mathew981487a2015-07-13 14:10:57 +010074 /* Sanity check the requested suspend levels */
Soby Mathew24ab34f2016-05-03 17:11:42 +010075 assert(psci_validate_suspend_req(&state_info, is_power_down_state)
Soby Mathew981487a2015-07-13 14:10:57 +010076 == PSCI_E_SUCCESS);
Soby Mathew74e52a72014-10-02 16:56:51 +010077
Soby Mathew981487a2015-07-13 14:10:57 +010078 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
Sandrine Bailleuxf9f3bbf2016-06-22 16:35:01 +010079 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) {
80 ERROR("Invalid target power level for suspend operation\n");
81 panic();
82 }
Soby Mathew981487a2015-07-13 14:10:57 +010083
84 /* Fast path for CPU standby.*/
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010085 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl) != 0) {
86 if (psci_plat_pm_ops->cpu_standby == NULL)
Soby Mathew74e52a72014-10-02 16:56:51 +010087 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010088
Soby Mathew981487a2015-07-13 14:10:57 +010089 /*
90 * Set the state of the CPU power domain to the platform
91 * specific retention state and enter the standby state.
92 */
93 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
94 psci_set_cpu_local_state(cpu_pd_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010095
96#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +000097 plat_psci_stat_accounting_start(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010098#endif
99
dp-arm3cac7862016-09-19 11:18:44 +0100100#if ENABLE_RUNTIME_INSTRUMENTATION
101 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
102 RT_INSTR_ENTER_HW_LOW_PWR,
103 PMF_NO_CACHE_MAINT);
104#endif
105
Soby Mathew981487a2015-07-13 14:10:57 +0100106 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
Achin Gupta42c52802014-05-09 19:32:25 +0100107
Soby Mathew981487a2015-07-13 14:10:57 +0100108 /* Upon exit from standby, set the state back to RUN. */
109 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Achin Gupta42c52802014-05-09 19:32:25 +0100110
dp-arm3cac7862016-09-19 11:18:44 +0100111#if ENABLE_RUNTIME_INSTRUMENTATION
112 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
113 RT_INSTR_EXIT_HW_LOW_PWR,
114 PMF_NO_CACHE_MAINT);
115#endif
116
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100117#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +0000118 plat_psci_stat_accounting_stop(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100119
120 /* Update PSCI stats */
dp-arm66abfbe2017-01-31 13:01:04 +0000121 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100122#endif
123
Soby Mathew74e52a72014-10-02 16:56:51 +0100124 return PSCI_E_SUCCESS;
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000125 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126
Achin Gupta42c52802014-05-09 19:32:25 +0100127 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100128 * If a power down state has been requested, we need to verify entry
129 * point and program entry information.
Soby Mathew8595b872015-01-06 15:36:38 +0000130 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100131 if (is_power_down_state != 0U) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100132 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew981487a2015-07-13 14:10:57 +0100133 if (rc != PSCI_E_SUCCESS)
134 return rc;
135 }
Soby Mathewf5121572014-09-30 11:19:51 +0100136
Soby Mathew8595b872015-01-06 15:36:38 +0000137 /*
Achin Gupta42c52802014-05-09 19:32:25 +0100138 * Do what is needed to enter the power down state. Upon success,
Soby Mathew981487a2015-07-13 14:10:57 +0100139 * enter the final wfi which will power down this CPU. This function
140 * might return if the power down was abandoned for any reason, e.g.
141 * arrival of an interrupt
Achin Gupta42c52802014-05-09 19:32:25 +0100142 */
Soby Mathew981487a2015-07-13 14:10:57 +0100143 psci_cpu_suspend_start(&ep,
144 target_pwrlvl,
145 &state_info,
146 is_power_down_state);
Soby Mathew74e52a72014-10-02 16:56:51 +0100147
Soby Mathew74e52a72014-10-02 16:56:51 +0100148 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100149}
150
Soby Mathew011ca182015-07-29 17:05:03 +0100151
152int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
Soby Mathew96168382014-12-17 14:47:57 +0000153{
154 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100155 psci_power_state_t state_info;
Soby Mathew96168382014-12-17 14:47:57 +0000156 entry_point_info_t ep;
157
Soby Mathew96168382014-12-17 14:47:57 +0000158 /* Check if the current CPU is the last ON CPU in the system */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100159 if (psci_is_last_on_cpu() == 0U)
Soby Mathew96168382014-12-17 14:47:57 +0000160 return PSCI_E_DENIED;
161
Soby Mathewf1f97a12015-07-15 12:13:26 +0100162 /* Validate the entry point and get the entry_point_info */
163 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew96168382014-12-17 14:47:57 +0000164 if (rc != PSCI_E_SUCCESS)
165 return rc;
166
Soby Mathew981487a2015-07-13 14:10:57 +0100167 /* Query the psci_power_state for system suspend */
168 psci_query_sys_suspend_pwrstate(&state_info);
Soby Mathew96168382014-12-17 14:47:57 +0000169
Soby Mathew981487a2015-07-13 14:10:57 +0100170 /* Ensure that the psci_power_state makes sense */
171 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL);
172 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
173 == PSCI_E_SUCCESS);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100174 assert(is_local_state_off(
175 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0);
Soby Mathew96168382014-12-17 14:47:57 +0000176
177 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100178 * Do what is needed to enter the system suspend state. This function
179 * might return if the power down was abandoned for any reason, e.g.
180 * arrival of an interrupt
Soby Mathew96168382014-12-17 14:47:57 +0000181 */
Soby Mathew981487a2015-07-13 14:10:57 +0100182 psci_cpu_suspend_start(&ep,
183 PLAT_MAX_PWR_LVL,
184 &state_info,
185 PSTATE_TYPE_POWERDOWN);
Soby Mathew96168382014-12-17 14:47:57 +0000186
Soby Mathew96168382014-12-17 14:47:57 +0000187 return PSCI_E_SUCCESS;
188}
189
Achin Gupta4f6ad662013-10-25 09:08:21 +0100190int psci_cpu_off(void)
191{
192 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100193 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100194
Achin Gupta4f6ad662013-10-25 09:08:21 +0100195 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100196 * Do what is needed to power off this CPU and possible higher power
197 * levels if it able to do so. Upon success, enter the final wfi
198 * which will power down this CPU.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100199 */
Soby Mathew981487a2015-07-13 14:10:57 +0100200 rc = psci_do_cpu_off(target_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100201
Achin Gupta3140a9e2013-12-02 16:23:12 +0000202 /*
203 * The only error cpu_off can return is E_DENIED. So check if that's
204 * indeed the case.
205 */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100206 assert(rc == PSCI_E_DENIED);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207
208 return rc;
209}
210
Soby Mathew011ca182015-07-29 17:05:03 +0100211int psci_affinity_info(u_register_t target_affinity,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100212 unsigned int lowest_affinity_level)
213{
Varun Wadekar66231d12017-06-07 09:57:42 -0700214 int target_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215
Soby Mathew981487a2015-07-13 14:10:57 +0100216 /* We dont support level higher than PSCI_CPU_PWR_LVL */
217 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
218 return PSCI_E_INVALID_PARAMS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100219
Soby Mathew981487a2015-07-13 14:10:57 +0100220 /* Calculate the cpu index of the target */
221 target_idx = plat_core_pos_by_mpidr(target_affinity);
222 if (target_idx == -1)
223 return PSCI_E_INVALID_PARAMS;
Achin Gupta75f73672013-12-05 16:33:10 +0000224
Roberto Vargas6dc82142017-11-13 08:24:07 +0000225 /*
226 * Generic management:
227 * Perform cache maintanence ahead of reading the target CPU state to
228 * ensure that the data is not stale.
229 * There is a theoretical edge case where the cache may contain stale
230 * data for the target CPU data - this can occur under the following
231 * conditions:
232 * - the target CPU is in another cluster from the current
233 * - the target CPU was the last CPU to shutdown on its cluster
234 * - the cluster was removed from coherency as part of the CPU shutdown
235 *
236 * In this case the cache maintenace that was performed as part of the
237 * target CPUs shutdown was not seen by the current CPU's cluster. And
238 * so the cache may contain stale data for the target CPU.
239 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100240 flush_cpu_data_by_index((unsigned int)target_idx,
241 psci_svc_cpu_data.aff_info_state);
Roberto Vargas6dc82142017-11-13 08:24:07 +0000242
Soby Mathew981487a2015-07-13 14:10:57 +0100243 return psci_get_aff_info_state_by_idx(target_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100244}
245
Soby Mathew011ca182015-07-29 17:05:03 +0100246int psci_migrate(u_register_t target_cpu)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247{
Soby Mathew110fe362014-10-23 10:35:34 +0100248 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100249 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100250
251 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
252 if (rc != PSCI_TOS_UP_MIG_CAP)
253 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
254 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
255
256 /*
257 * Migrate should only be invoked on the CPU where
258 * the Secure OS is resident.
259 */
260 if (resident_cpu_mpidr != read_mpidr_el1())
261 return PSCI_E_NOT_PRESENT;
262
263 /* Check the validity of the specified target cpu */
Soby Mathew981487a2015-07-13 14:10:57 +0100264 rc = psci_validate_mpidr(target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100265 if (rc != PSCI_E_SUCCESS)
266 return PSCI_E_INVALID_PARAMS;
267
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100268 assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL));
Soby Mathew110fe362014-10-23 10:35:34 +0100269
270 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100271 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL));
Soby Mathew110fe362014-10-23 10:35:34 +0100272
273 return rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100274}
275
Soby Mathew110fe362014-10-23 10:35:34 +0100276int psci_migrate_info_type(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277{
Soby Mathew011ca182015-07-29 17:05:03 +0100278 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100279
280 return psci_spd_migrate_info(&resident_cpu_mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100281}
282
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100283u_register_t psci_migrate_info_up_cpu(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100284{
Soby Mathew011ca182015-07-29 17:05:03 +0100285 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100286 int rc;
287
Achin Gupta4f6ad662013-10-25 09:08:21 +0100288 /*
Soby Mathew110fe362014-10-23 10:35:34 +0100289 * Return value of this depends upon what
290 * psci_spd_migrate_info() returns.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100291 */
Soby Mathew110fe362014-10-23 10:35:34 +0100292 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100293 if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP))
294 return (u_register_t)(register_t) PSCI_E_INVALID_PARAMS;
Soby Mathew110fe362014-10-23 10:35:34 +0100295
296 return resident_cpu_mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100297}
298
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100299int psci_node_hw_state(u_register_t target_cpu,
300 unsigned int power_level)
301{
302 int rc;
303
304 /* Validate target_cpu */
305 rc = psci_validate_mpidr(target_cpu);
306 if (rc != PSCI_E_SUCCESS)
307 return PSCI_E_INVALID_PARAMS;
308
309 /* Validate power_level against PLAT_MAX_PWR_LVL */
310 if (power_level > PLAT_MAX_PWR_LVL)
311 return PSCI_E_INVALID_PARAMS;
312
313 /*
314 * Dispatch this call to platform to query power controller, and pass on
315 * to the caller what it returns
316 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100317 assert(psci_plat_pm_ops->get_node_hw_state != NULL);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100318 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100319 assert(((rc >= HW_ON) && (rc <= HW_STANDBY))
320 || (rc == PSCI_E_NOT_SUPPORTED)
321 || (rc == PSCI_E_INVALID_PARAMS));
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100322 return rc;
323}
324
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000325int psci_features(unsigned int psci_fid)
326{
Soby Mathew011ca182015-07-29 17:05:03 +0100327 unsigned int local_caps = psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000328
Dimitris Papastamosa65841a2018-01-22 12:58:52 +0000329 if (psci_fid == SMCCC_VERSION)
330 return PSCI_E_SUCCESS;
331
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000332 /* Check if it is a 64 bit function */
333 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
334 local_caps &= PSCI_CAP_64BIT_MASK;
335
336 /* Check for invalid fid */
337 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
338 && is_psci_fid(psci_fid)))
339 return PSCI_E_NOT_SUPPORTED;
340
341
342 /* Check if the psci fid is supported or not */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100343 if ((local_caps & define_psci_cap(psci_fid)) == 0U)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000344 return PSCI_E_NOT_SUPPORTED;
345
346 /* Format the feature flags */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100347 if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) ||
348 (psci_fid == PSCI_CPU_SUSPEND_AARCH64)) {
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000349 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100350 * The trusted firmware does not support OS Initiated Mode.
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000351 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100352 unsigned int ret = ((FF_PSTATE << FF_PSTATE_SHIFT) |
353 (((FF_SUPPORTS_OS_INIT_MODE == 1U) ? 0U : 1U)
354 << FF_MODE_SUPPORT_SHIFT));
355 return (int) ret;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000356 }
357
358 /* Return 0 for all other fid's */
359 return PSCI_E_SUCCESS;
360}
361
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000362/*******************************************************************************
363 * PSCI top level handler for servicing SMCs.
364 ******************************************************************************/
Soby Mathewd0194872016-04-29 19:01:30 +0100365u_register_t psci_smc_handler(uint32_t smc_fid,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100366 u_register_t x1,
367 u_register_t x2,
368 u_register_t x3,
369 u_register_t x4,
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000370 void *cookie,
371 void *handle,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100372 u_register_t flags)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000373{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100374 u_register_t ret;
375
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100376 if (is_caller_secure(flags))
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100377 return (u_register_t)SMC_UNK;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000378
Soby Mathew61e615b2015-01-15 11:49:49 +0000379 /* Check the fid against the capabilities */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100380 if ((psci_caps & define_psci_cap(smc_fid)) == 0U)
381 return (u_register_t)SMC_UNK;
Soby Mathew61e615b2015-01-15 11:49:49 +0000382
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100383 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
384 /* 32-bit PSCI function, clear top parameter bits */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000385
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100386 uint32_t r1 = (uint32_t)x1;
387 uint32_t r2 = (uint32_t)x2;
388 uint32_t r3 = (uint32_t)x3;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000389
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100390 switch (smc_fid) {
391 case PSCI_VERSION:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100392 ret = (u_register_t)psci_version();
393 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000394
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100395 case PSCI_CPU_OFF:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100396 ret = (u_register_t)psci_cpu_off();
397 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000398
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100399 case PSCI_CPU_SUSPEND_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100400 ret = (u_register_t)psci_cpu_suspend(r1, r2, r3);
401 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000402
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100403 case PSCI_CPU_ON_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100404 ret = (u_register_t)psci_cpu_on(r1, r2, r3);
405 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000406
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100407 case PSCI_AFFINITY_INFO_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100408 ret = (u_register_t)psci_affinity_info(r1, r2);
409 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000410
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100411 case PSCI_MIG_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100412 ret = (u_register_t)psci_migrate(r1);
413 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000414
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100415 case PSCI_MIG_INFO_TYPE:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100416 ret = (u_register_t)psci_migrate_info_type();
417 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100418
419 case PSCI_MIG_INFO_UP_CPU_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100420 ret = psci_migrate_info_up_cpu();
421 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100422
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100423 case PSCI_NODE_HW_STATE_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100424 ret = (u_register_t)psci_node_hw_state(r1, r2);
425 break;
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100426
Soby Mathew96168382014-12-17 14:47:57 +0000427 case PSCI_SYSTEM_SUSPEND_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100428 ret = (u_register_t)psci_system_suspend(r1, r2);
429 break;
Soby Mathew96168382014-12-17 14:47:57 +0000430
Juan Castillo4dc4a472014-08-12 11:17:06 +0100431 case PSCI_SYSTEM_OFF:
432 psci_system_off();
433 /* We should never return from psci_system_off() */
Jonathan Wrightde701832018-03-13 17:45:42 +0000434 break;
Juan Castillo4dc4a472014-08-12 11:17:06 +0100435
436 case PSCI_SYSTEM_RESET:
437 psci_system_reset();
438 /* We should never return from psci_system_reset() */
Jonathan Wrightde701832018-03-13 17:45:42 +0000439 break;
Juan Castillo4dc4a472014-08-12 11:17:06 +0100440
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000441 case PSCI_FEATURES:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100442 ret = (u_register_t)psci_features(r1);
443 break;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000444
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100445#if ENABLE_PSCI_STAT
446 case PSCI_STAT_RESIDENCY_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100447 ret = psci_stat_residency(r1, r2);
448 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100449
450 case PSCI_STAT_COUNT_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100451 ret = psci_stat_count(r1, r2);
452 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100453#endif
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100454 case PSCI_MEM_PROTECT:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100455 ret = psci_mem_protect(r1);
456 break;
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100457
458 case PSCI_MEM_CHK_RANGE_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100459 ret = psci_mem_chk_range(r1, r2);
460 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100461
Roberto Vargasb820ad02017-07-26 09:23:09 +0100462 case PSCI_SYSTEM_RESET2_AARCH32:
463 /* We should never return from psci_system_reset2() */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100464 ret = psci_system_reset2(r1, r2);
465 break;
Roberto Vargasb820ad02017-07-26 09:23:09 +0100466
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100467 default:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100468 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid);
469 ret = (u_register_t)SMC_UNK;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100470 break;
471 }
472 } else {
473 /* 64-bit PSCI function */
474
475 switch (smc_fid) {
476 case PSCI_CPU_SUSPEND_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100477 ret = (u_register_t)
478 psci_cpu_suspend((unsigned int)x1, x2, x3);
479 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100480
481 case PSCI_CPU_ON_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100482 ret = (u_register_t)psci_cpu_on(x1, x2, x3);
483 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100484
485 case PSCI_AFFINITY_INFO_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100486 ret = (u_register_t)
487 psci_affinity_info(x1, (unsigned int)x2);
488 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100489
490 case PSCI_MIG_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100491 ret = (u_register_t)psci_migrate(x1);
492 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100493
494 case PSCI_MIG_INFO_UP_CPU_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100495 ret = psci_migrate_info_up_cpu();
496 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100497
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100498 case PSCI_NODE_HW_STATE_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100499 ret = (u_register_t)psci_node_hw_state(
500 x1, (unsigned int) x2);
501 break;
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100502
Soby Mathew96168382014-12-17 14:47:57 +0000503 case PSCI_SYSTEM_SUSPEND_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100504 ret = (u_register_t)psci_system_suspend(x1, x2);
505 break;
Soby Mathew96168382014-12-17 14:47:57 +0000506
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100507#if ENABLE_PSCI_STAT
508 case PSCI_STAT_RESIDENCY_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100509 ret = psci_stat_residency(x1, (unsigned int) x2);
510 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100511
512 case PSCI_STAT_COUNT_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100513 ret = psci_stat_count(x1, (unsigned int) x2);
514 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100515#endif
516
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100517 case PSCI_MEM_CHK_RANGE_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100518 ret = psci_mem_chk_range(x1, x2);
519 break;
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100520
Roberto Vargasb820ad02017-07-26 09:23:09 +0100521 case PSCI_SYSTEM_RESET2_AARCH64:
522 /* We should never return from psci_system_reset2() */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100523 ret = psci_system_reset2((uint32_t) x1, x2);
524 break;
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100525
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100526 default:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100527 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid);
528 ret = (u_register_t)SMC_UNK;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100529 break;
530 }
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000531 }
532
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100533 return ret;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000534}