blob: 86df9a11fc22c9abf71ac9ca32576ea01b102b41 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathewa0fedc42016-06-16 14:52:04 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Soby Mathew96168382014-12-17 14:47:57 +000034#include <debug.h>
35#include <platform.h>
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000036#include <runtime_svc.h>
Soby Mathew6cdddaf2015-01-07 11:10:22 +000037#include <std_svc.h>
Soby Mathew981487a2015-07-13 14:10:57 +010038#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010039#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
42 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
43 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010044int psci_cpu_on(u_register_t target_cpu,
45 uintptr_t entrypoint,
46 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
48{
49 int rc;
Soby Mathew8595b872015-01-06 15:36:38 +000050 entry_point_info_t ep;
Achin Gupta4f6ad662013-10-25 09:08:21 +010051
52 /* Determine if the cpu exists of not */
Soby Mathew981487a2015-07-13 14:10:57 +010053 rc = psci_validate_mpidr(target_cpu);
54 if (rc != PSCI_E_SUCCESS)
Soby Mathew74e52a72014-10-02 16:56:51 +010055 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010056
Soby Mathewf1f97a12015-07-15 12:13:26 +010057 /* Validate the entry point and get the entry_point_info */
58 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew8595b872015-01-06 15:36:38 +000059 if (rc != PSCI_E_SUCCESS)
60 return rc;
61
Soby Mathew8595b872015-01-06 15:36:38 +000062 /*
Soby Mathew981487a2015-07-13 14:10:57 +010063 * To turn this cpu on, specify which power
Achin Gupta0959db52013-12-02 17:33:04 +000064 * levels need to be turned on
65 */
Sandrine Bailleux7497bff2016-04-25 09:28:43 +010066 return psci_cpu_on_start(target_cpu, &ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +010067}
68
69unsigned int psci_version(void)
70{
71 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
72}
73
74int psci_cpu_suspend(unsigned int power_state,
Soby Mathew011ca182015-07-29 17:05:03 +010075 uintptr_t entrypoint,
76 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010077{
78 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010079 unsigned int target_pwrlvl, is_power_down_state;
Soby Mathew8595b872015-01-06 15:36:38 +000080 entry_point_info_t ep;
Soby Mathew981487a2015-07-13 14:10:57 +010081 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
82 plat_local_state_t cpu_pd_state;
Achin Gupta4f6ad662013-10-25 09:08:21 +010083
Soby Mathew981487a2015-07-13 14:10:57 +010084 /* Validate the power_state parameter */
85 rc = psci_validate_power_state(power_state, &state_info);
86 if (rc != PSCI_E_SUCCESS) {
87 assert(rc == PSCI_E_INVALID_PARAMS);
88 return rc;
89 }
Vikram Kanigirif100f412014-04-01 19:26:26 +010090
Soby Mathew981487a2015-07-13 14:10:57 +010091 /*
92 * Get the value of the state type bit from the power state parameter.
93 */
94 is_power_down_state = psci_get_pstate_type(power_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +010095
Soby Mathew981487a2015-07-13 14:10:57 +010096 /* Sanity check the requested suspend levels */
97 assert (psci_validate_suspend_req(&state_info, is_power_down_state)
98 == PSCI_E_SUCCESS);
Soby Mathew74e52a72014-10-02 16:56:51 +010099
Soby Mathew981487a2015-07-13 14:10:57 +0100100 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
101
102 /* Fast path for CPU standby.*/
103 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
104 if (!psci_plat_pm_ops->cpu_standby)
Soby Mathew74e52a72014-10-02 16:56:51 +0100105 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +0100106
Soby Mathew981487a2015-07-13 14:10:57 +0100107 /*
108 * Set the state of the CPU power domain to the platform
109 * specific retention state and enter the standby state.
110 */
111 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
112 psci_set_cpu_local_state(cpu_pd_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100113
114#if ENABLE_PSCI_STAT
115 /*
116 * Capture time-stamp before CPU standby
117 * No cache maintenance is needed as caches
118 * are ON through out the CPU standby operation.
119 */
120 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR,
121 PMF_NO_CACHE_MAINT);
122#endif
123
Soby Mathew981487a2015-07-13 14:10:57 +0100124 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
Achin Gupta42c52802014-05-09 19:32:25 +0100125
Soby Mathew981487a2015-07-13 14:10:57 +0100126 /* Upon exit from standby, set the state back to RUN. */
127 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Achin Gupta42c52802014-05-09 19:32:25 +0100128
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100129#if ENABLE_PSCI_STAT
130 /* Capture time-stamp after CPU standby */
131 PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR,
132 PMF_NO_CACHE_MAINT);
133
134 /* Update PSCI stats */
135 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info,
136 PMF_NO_CACHE_MAINT);
137#endif
138
Soby Mathew74e52a72014-10-02 16:56:51 +0100139 return PSCI_E_SUCCESS;
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000140 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141
Achin Gupta42c52802014-05-09 19:32:25 +0100142 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100143 * If a power down state has been requested, we need to verify entry
144 * point and program entry information.
Soby Mathew8595b872015-01-06 15:36:38 +0000145 */
Soby Mathew981487a2015-07-13 14:10:57 +0100146 if (is_power_down_state) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100147 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew981487a2015-07-13 14:10:57 +0100148 if (rc != PSCI_E_SUCCESS)
149 return rc;
150 }
Soby Mathewf5121572014-09-30 11:19:51 +0100151
Soby Mathew8595b872015-01-06 15:36:38 +0000152 /*
Achin Gupta42c52802014-05-09 19:32:25 +0100153 * Do what is needed to enter the power down state. Upon success,
Soby Mathew981487a2015-07-13 14:10:57 +0100154 * enter the final wfi which will power down this CPU. This function
155 * might return if the power down was abandoned for any reason, e.g.
156 * arrival of an interrupt
Achin Gupta42c52802014-05-09 19:32:25 +0100157 */
Soby Mathew981487a2015-07-13 14:10:57 +0100158 psci_cpu_suspend_start(&ep,
159 target_pwrlvl,
160 &state_info,
161 is_power_down_state);
Soby Mathew74e52a72014-10-02 16:56:51 +0100162
Soby Mathew74e52a72014-10-02 16:56:51 +0100163 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100164}
165
Soby Mathew011ca182015-07-29 17:05:03 +0100166
167int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
Soby Mathew96168382014-12-17 14:47:57 +0000168{
169 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100170 psci_power_state_t state_info;
Soby Mathew96168382014-12-17 14:47:57 +0000171 entry_point_info_t ep;
172
Soby Mathew96168382014-12-17 14:47:57 +0000173 /* Check if the current CPU is the last ON CPU in the system */
174 if (!psci_is_last_on_cpu())
175 return PSCI_E_DENIED;
176
Soby Mathewf1f97a12015-07-15 12:13:26 +0100177 /* Validate the entry point and get the entry_point_info */
178 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew96168382014-12-17 14:47:57 +0000179 if (rc != PSCI_E_SUCCESS)
180 return rc;
181
Soby Mathew981487a2015-07-13 14:10:57 +0100182 /* Query the psci_power_state for system suspend */
183 psci_query_sys_suspend_pwrstate(&state_info);
Soby Mathew96168382014-12-17 14:47:57 +0000184
Soby Mathew981487a2015-07-13 14:10:57 +0100185 /* Ensure that the psci_power_state makes sense */
186 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL);
187 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
188 == PSCI_E_SUCCESS);
189 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]));
Soby Mathew96168382014-12-17 14:47:57 +0000190
191 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100192 * Do what is needed to enter the system suspend state. This function
193 * might return if the power down was abandoned for any reason, e.g.
194 * arrival of an interrupt
Soby Mathew96168382014-12-17 14:47:57 +0000195 */
Soby Mathew981487a2015-07-13 14:10:57 +0100196 psci_cpu_suspend_start(&ep,
197 PLAT_MAX_PWR_LVL,
198 &state_info,
199 PSTATE_TYPE_POWERDOWN);
Soby Mathew96168382014-12-17 14:47:57 +0000200
Soby Mathew96168382014-12-17 14:47:57 +0000201 return PSCI_E_SUCCESS;
202}
203
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204int psci_cpu_off(void)
205{
206 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100207 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100208
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100210 * Do what is needed to power off this CPU and possible higher power
211 * levels if it able to do so. Upon success, enter the final wfi
212 * which will power down this CPU.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100213 */
Soby Mathew981487a2015-07-13 14:10:57 +0100214 rc = psci_do_cpu_off(target_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215
Achin Gupta3140a9e2013-12-02 16:23:12 +0000216 /*
217 * The only error cpu_off can return is E_DENIED. So check if that's
218 * indeed the case.
219 */
Achin Gupta42c52802014-05-09 19:32:25 +0100220 assert (rc == PSCI_E_DENIED);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100221
222 return rc;
223}
224
Soby Mathew011ca182015-07-29 17:05:03 +0100225int psci_affinity_info(u_register_t target_affinity,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100226 unsigned int lowest_affinity_level)
227{
Soby Mathew981487a2015-07-13 14:10:57 +0100228 unsigned int target_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229
Soby Mathew981487a2015-07-13 14:10:57 +0100230 /* We dont support level higher than PSCI_CPU_PWR_LVL */
231 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
232 return PSCI_E_INVALID_PARAMS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100233
Soby Mathew981487a2015-07-13 14:10:57 +0100234 /* Calculate the cpu index of the target */
235 target_idx = plat_core_pos_by_mpidr(target_affinity);
236 if (target_idx == -1)
237 return PSCI_E_INVALID_PARAMS;
Achin Gupta75f73672013-12-05 16:33:10 +0000238
Soby Mathew981487a2015-07-13 14:10:57 +0100239 return psci_get_aff_info_state_by_idx(target_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100240}
241
Soby Mathew011ca182015-07-29 17:05:03 +0100242int psci_migrate(u_register_t target_cpu)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243{
Soby Mathew110fe362014-10-23 10:35:34 +0100244 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100245 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100246
247 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
248 if (rc != PSCI_TOS_UP_MIG_CAP)
249 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
250 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
251
252 /*
253 * Migrate should only be invoked on the CPU where
254 * the Secure OS is resident.
255 */
256 if (resident_cpu_mpidr != read_mpidr_el1())
257 return PSCI_E_NOT_PRESENT;
258
259 /* Check the validity of the specified target cpu */
Soby Mathew981487a2015-07-13 14:10:57 +0100260 rc = psci_validate_mpidr(target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100261 if (rc != PSCI_E_SUCCESS)
262 return PSCI_E_INVALID_PARAMS;
263
264 assert(psci_spd_pm && psci_spd_pm->svc_migrate);
265
266 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
267 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
268
269 return rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100270}
271
Soby Mathew110fe362014-10-23 10:35:34 +0100272int psci_migrate_info_type(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100273{
Soby Mathew011ca182015-07-29 17:05:03 +0100274 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100275
276 return psci_spd_migrate_info(&resident_cpu_mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277}
278
Soby Mathew110fe362014-10-23 10:35:34 +0100279long psci_migrate_info_up_cpu(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100280{
Soby Mathew011ca182015-07-29 17:05:03 +0100281 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100282 int rc;
283
Achin Gupta4f6ad662013-10-25 09:08:21 +0100284 /*
Soby Mathew110fe362014-10-23 10:35:34 +0100285 * Return value of this depends upon what
286 * psci_spd_migrate_info() returns.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100287 */
Soby Mathew110fe362014-10-23 10:35:34 +0100288 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
289 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP)
290 return PSCI_E_INVALID_PARAMS;
291
292 return resident_cpu_mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100293}
294
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000295int psci_features(unsigned int psci_fid)
296{
Soby Mathew011ca182015-07-29 17:05:03 +0100297 unsigned int local_caps = psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000298
299 /* Check if it is a 64 bit function */
300 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
301 local_caps &= PSCI_CAP_64BIT_MASK;
302
303 /* Check for invalid fid */
304 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
305 && is_psci_fid(psci_fid)))
306 return PSCI_E_NOT_SUPPORTED;
307
308
309 /* Check if the psci fid is supported or not */
310 if (!(local_caps & define_psci_cap(psci_fid)))
311 return PSCI_E_NOT_SUPPORTED;
312
313 /* Format the feature flags */
314 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 ||
315 psci_fid == PSCI_CPU_SUSPEND_AARCH64) {
316 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100317 * The trusted firmware does not support OS Initiated Mode.
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000318 */
Soby Mathew981487a2015-07-13 14:10:57 +0100319 return (FF_PSTATE << FF_PSTATE_SHIFT) |
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000320 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT);
321 }
322
323 /* Return 0 for all other fid's */
324 return PSCI_E_SUCCESS;
325}
326
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000327/*******************************************************************************
328 * PSCI top level handler for servicing SMCs.
329 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +0100330uintptr_t psci_smc_handler(uint32_t smc_fid,
331 u_register_t x1,
332 u_register_t x2,
333 u_register_t x3,
334 u_register_t x4,
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000335 void *cookie,
336 void *handle,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100337 u_register_t flags)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000338{
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100339 if (is_caller_secure(flags))
340 SMC_RET1(handle, SMC_UNK);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000341
Soby Mathew61e615b2015-01-15 11:49:49 +0000342 /* Check the fid against the capabilities */
343 if (!(psci_caps & define_psci_cap(smc_fid)))
344 SMC_RET1(handle, SMC_UNK);
345
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100346 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
347 /* 32-bit PSCI function, clear top parameter bits */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000348
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100349 x1 = (uint32_t)x1;
350 x2 = (uint32_t)x2;
351 x3 = (uint32_t)x3;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000352
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100353 switch (smc_fid) {
354 case PSCI_VERSION:
355 SMC_RET1(handle, psci_version());
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000356
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100357 case PSCI_CPU_OFF:
Achin Guptae1aa5162014-06-26 09:58:52 +0100358 SMC_RET1(handle, psci_cpu_off());
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000359
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100360 case PSCI_CPU_SUSPEND_AARCH32:
Achin Guptae1aa5162014-06-26 09:58:52 +0100361 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000362
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100363 case PSCI_CPU_ON_AARCH32:
364 SMC_RET1(handle, psci_cpu_on(x1, x2, x3));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000365
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100366 case PSCI_AFFINITY_INFO_AARCH32:
367 SMC_RET1(handle, psci_affinity_info(x1, x2));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000368
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100369 case PSCI_MIG_AARCH32:
370 SMC_RET1(handle, psci_migrate(x1));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000371
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100372 case PSCI_MIG_INFO_TYPE:
373 SMC_RET1(handle, psci_migrate_info_type());
374
375 case PSCI_MIG_INFO_UP_CPU_AARCH32:
376 SMC_RET1(handle, psci_migrate_info_up_cpu());
377
Soby Mathew96168382014-12-17 14:47:57 +0000378 case PSCI_SYSTEM_SUSPEND_AARCH32:
379 SMC_RET1(handle, psci_system_suspend(x1, x2));
380
Juan Castillo4dc4a472014-08-12 11:17:06 +0100381 case PSCI_SYSTEM_OFF:
382 psci_system_off();
383 /* We should never return from psci_system_off() */
384
385 case PSCI_SYSTEM_RESET:
386 psci_system_reset();
387 /* We should never return from psci_system_reset() */
388
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000389 case PSCI_FEATURES:
390 SMC_RET1(handle, psci_features(x1));
391
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100392#if ENABLE_PSCI_STAT
393 case PSCI_STAT_RESIDENCY_AARCH32:
394 SMC_RET1(handle, psci_stat_residency(x1, x2));
395
396 case PSCI_STAT_COUNT_AARCH32:
397 SMC_RET1(handle, psci_stat_count(x1, x2));
398#endif
399
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100400 default:
401 break;
402 }
403 } else {
404 /* 64-bit PSCI function */
405
406 switch (smc_fid) {
407 case PSCI_CPU_SUSPEND_AARCH64:
Achin Guptae1aa5162014-06-26 09:58:52 +0100408 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3));
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100409
410 case PSCI_CPU_ON_AARCH64:
411 SMC_RET1(handle, psci_cpu_on(x1, x2, x3));
412
413 case PSCI_AFFINITY_INFO_AARCH64:
414 SMC_RET1(handle, psci_affinity_info(x1, x2));
415
416 case PSCI_MIG_AARCH64:
417 SMC_RET1(handle, psci_migrate(x1));
418
419 case PSCI_MIG_INFO_UP_CPU_AARCH64:
420 SMC_RET1(handle, psci_migrate_info_up_cpu());
421
Soby Mathew96168382014-12-17 14:47:57 +0000422 case PSCI_SYSTEM_SUSPEND_AARCH64:
423 SMC_RET1(handle, psci_system_suspend(x1, x2));
424
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100425#if ENABLE_PSCI_STAT
426 case PSCI_STAT_RESIDENCY_AARCH64:
427 SMC_RET1(handle, psci_stat_residency(x1, x2));
428
429 case PSCI_STAT_COUNT_AARCH64:
430 SMC_RET1(handle, psci_stat_count(x1, x2));
431#endif
432
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100433 default:
434 break;
435 }
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000436 }
437
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100438 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid);
439 SMC_RET1(handle, SMC_UNK);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000440}