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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch_helpers.h>
8#include <arm_def.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01009#include <assert.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <bl_common.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010011#include <debug.h>
12#include <desc_image_load.h>
Soby Mathew1ced6b82017-06-12 12:37:10 +010013#include <generic_delay_timer.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010014#ifdef SPD_opteed
15#include <optee_utils.h>
16#endif
Dan Handley9df48042015-03-19 18:58:55 +000017#include <plat_arm.h>
dp-arm7f297ca2017-05-02 11:49:33 +010018#include <platform.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010019#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000020#include <string.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000021#include <utils.h>
Dan Handley9df48042015-03-19 18:58:55 +000022
Dan Handley9df48042015-03-19 18:58:55 +000023/* Data structure which holds the extents of the trusted SRAM for BL2 */
24static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
25
Soby Mathewc44110d2018-02-20 12:50:47 +000026/*
Soby Mathewaf14b462018-06-01 16:53:38 +010027 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is
28 * for `meminfo_t` data structure and fw_configs passed from BL1.
Soby Mathewc44110d2018-02-20 12:50:47 +000029 */
Soby Mathewaf14b462018-06-01 16:53:38 +010030CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
Soby Mathewc44110d2018-02-20 12:50:47 +000031
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010032/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000033#pragma weak bl2_early_platform_setup2
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010034#pragma weak bl2_platform_setup
35#pragma weak bl2_plat_arch_setup
36#pragma weak bl2_plat_sec_mem_layout
37
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010038#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
39 bl2_tzram_layout.total_base, \
40 bl2_tzram_layout.total_size, \
41 MT_MEMORY | MT_RW | MT_SECURE)
42
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010043
Daniel Boulby07d26872018-06-27 16:45:48 +010044#pragma weak arm_bl2_plat_handle_post_image_load
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010045
Dan Handley9df48042015-03-19 18:58:55 +000046/*******************************************************************************
47 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
48 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
49 * Copy it to a safe location before its reclaimed by later BL2 functionality.
50 ******************************************************************************/
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020051void arm_bl2_early_platform_setup(uintptr_t tb_fw_config,
52 struct meminfo *mem_layout)
Dan Handley9df48042015-03-19 18:58:55 +000053{
54 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010055 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000056
57 /* Setup the BL2 memory layout */
58 bl2_tzram_layout = *mem_layout;
59
60 /* Initialise the IO layer and register platform IO devices */
61 plat_arm_io_setup();
Soby Mathew96a1c6b2018-01-15 14:45:33 +000062
Soby Mathewcc364842018-02-21 01:16:39 +000063 if (tb_fw_config != 0U)
Soby Mathew96a1c6b2018-01-15 14:45:33 +000064 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config);
Dan Handley9df48042015-03-19 18:58:55 +000065}
66
Soby Mathew7d5a2e72018-01-10 15:59:31 +000067void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +000068{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000069 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
70
Soby Mathew1ced6b82017-06-12 12:37:10 +010071 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +000072}
73
74/*
Soby Mathew45e39e22018-03-26 15:16:46 +010075 * Perform BL2 preload setup. Currently we initialise the dynamic
76 * configuration here.
Dan Handley9df48042015-03-19 18:58:55 +000077 */
Soby Mathew45e39e22018-03-26 15:16:46 +010078void bl2_plat_preload_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +000079{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000080 arm_bl2_dyn_cfg_init();
Soby Mathew45e39e22018-03-26 15:16:46 +010081}
Soby Mathew96a1c6b2018-01-15 14:45:33 +000082
Soby Mathew45e39e22018-03-26 15:16:46 +010083/*
84 * Perform ARM standard platform setup.
85 */
86void arm_bl2_platform_setup(void)
87{
Dan Handley9df48042015-03-19 18:58:55 +000088 /* Initialize the secure environment */
89 plat_arm_security_setup();
Roberto Vargasa1c16b62017-08-03 09:16:43 +010090
91#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargas550eb082018-01-05 16:00:05 +000092 arm_nor_psci_do_static_mem_protect();
Roberto Vargasa1c16b62017-08-03 09:16:43 +010093#endif
Dan Handley9df48042015-03-19 18:58:55 +000094}
95
96void bl2_platform_setup(void)
97{
98 arm_bl2_platform_setup();
99}
100
101/*******************************************************************************
102 * Perform the very early platform specific architectural setup here. At the
103 * moment this is only initializes the mmu in a quick and dirty way.
104 ******************************************************************************/
105void arm_bl2_plat_arch_setup(void)
106{
Soby Mathewb9856482018-09-18 11:42:42 +0100107#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
108 /*
109 * Ensure ARM platforms don't use coherent memory in BL2 unless
110 * cryptocell integration is enabled.
111 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100112 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000113#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100114
115 const mmap_region_t bl_regions[] = {
116 MAP_BL2_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100117 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100118#if USE_ROMLIB
119 ARM_MAP_ROMLIB_CODE,
120 ARM_MAP_ROMLIB_DATA,
121#endif
Soby Mathewb9856482018-09-18 11:42:42 +0100122#if ARM_CRYPTOCELL_INTEG
123 ARM_MAP_BL_COHERENT_RAM,
124#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100125 {0}
126 };
127
128 arm_setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100129
130#ifdef AARCH32
Antonio Nino Diaz533d3a82018-08-07 16:35:19 +0100131 enable_mmu_svc_mon(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100132#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100133 enable_mmu_el1(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100134#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100135
136 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000137}
138
139void bl2_plat_arch_setup(void)
140{
141 arm_bl2_plat_arch_setup();
142}
143
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000144int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100145{
146 int err = 0;
147 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100148#ifdef SPD_opteed
149 bl_mem_params_node_t *pager_mem_params = NULL;
150 bl_mem_params_node_t *paged_mem_params = NULL;
151#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100152 assert(bl_mem_params);
153
154 switch (image_id) {
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100155#ifdef AARCH64
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100156 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100157#ifdef SPD_opteed
158 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
159 assert(pager_mem_params);
160
161 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
162 assert(paged_mem_params);
163
164 err = parse_optee_header(&bl_mem_params->ep_info,
165 &pager_mem_params->image_info,
166 &paged_mem_params->image_info);
167 if (err != 0) {
168 WARN("OPTEE header parse error.\n");
169 }
170#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100171 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
172 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100173#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100174
175 case BL33_IMAGE_ID:
176 /* BL33 expects to receive the primary CPU MPID (through r0) */
177 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
178 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
179 break;
180
181#ifdef SCP_BL2_BASE
182 case SCP_BL2_IMAGE_ID:
183 /* The subsequent handling of SCP_BL2 is platform specific */
184 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
185 if (err) {
186 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
187 }
188 break;
189#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000190 default:
191 /* Do nothing in default case */
192 break;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100193 }
194
195 return err;
196}
197
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000198/*******************************************************************************
199 * This function can be used by the platforms to update/use image
200 * information for given `image_id`.
201 ******************************************************************************/
Daniel Boulby07d26872018-06-27 16:45:48 +0100202int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000203{
204 return arm_bl2_handle_post_image_load(image_id);
205}
206
Daniel Boulby07d26872018-06-27 16:45:48 +0100207int bl2_plat_handle_post_image_load(unsigned int image_id)
208{
209 return arm_bl2_plat_handle_post_image_load(image_id);
210}