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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Zelaleme8dadb12020-02-05 14:12:39 -06002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
10#include <platform_def.h>
11
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
15#include <common/desc_image_load.h>
16#include <drivers/generic_delay_timer.h>
Louis Mayencourt81bd9162019-10-17 15:14:25 +010017#include <lib/fconf/fconf.h>
Manish V Badarkhe99a8e142020-06-11 22:32:11 +010018#include <lib/fconf/fconf_dyn_cfg_getter.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010019#ifdef SPD_opteed
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <lib/optee_utils.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010021#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <lib/utils.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000023#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <plat/common/platform.h>
25
Dan Handley9df48042015-03-19 18:58:55 +000026/* Data structure which holds the extents of the trusted SRAM for BL2 */
27static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
28
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +010029/* Base address of fw_config received from BL1 */
Jimmy Brissond7297c72020-08-05 14:05:53 -050030static uintptr_t config_base;
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +010031
Soby Mathewc44110d2018-02-20 12:50:47 +000032/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010033 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is
Soby Mathewaf14b462018-06-01 16:53:38 +010034 * for `meminfo_t` data structure and fw_configs passed from BL1.
Soby Mathewc44110d2018-02-20 12:50:47 +000035 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010036CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
Soby Mathewc44110d2018-02-20 12:50:47 +000037
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010038/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000039#pragma weak bl2_early_platform_setup2
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010040#pragma weak bl2_platform_setup
41#pragma weak bl2_plat_arch_setup
42#pragma weak bl2_plat_sec_mem_layout
Alexei Fedorovc7176172020-07-13 12:11:05 +010043#if MEASURED_BOOT
44#pragma weak bl2_plat_get_hash
45#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010046
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010047#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
48 bl2_tzram_layout.total_base, \
49 bl2_tzram_layout.total_size, \
50 MT_MEMORY | MT_RW | MT_SECURE)
51
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010052
Daniel Boulby07d26872018-06-27 16:45:48 +010053#pragma weak arm_bl2_plat_handle_post_image_load
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010054
Dan Handley9df48042015-03-19 18:58:55 +000055/*******************************************************************************
56 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
57 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
58 * Copy it to a safe location before its reclaimed by later BL2 functionality.
59 ******************************************************************************/
Manish V Badarkhe1da211a2020-05-31 10:17:59 +010060void arm_bl2_early_platform_setup(uintptr_t fw_config,
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020061 struct meminfo *mem_layout)
Dan Handley9df48042015-03-19 18:58:55 +000062{
63 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010064 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000065
66 /* Setup the BL2 memory layout */
67 bl2_tzram_layout = *mem_layout;
68
Jimmy Brissond7297c72020-08-05 14:05:53 -050069 config_base = fw_config;
Louis Mayencourt81bd9162019-10-17 15:14:25 +010070
Dan Handley9df48042015-03-19 18:58:55 +000071 /* Initialise the IO layer and register platform IO devices */
72 plat_arm_io_setup();
73}
74
Soby Mathew7d5a2e72018-01-10 15:59:31 +000075void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +000076{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000077 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
78
Soby Mathew1ced6b82017-06-12 12:37:10 +010079 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +000080}
81
82/*
Soby Mathew45e39e22018-03-26 15:16:46 +010083 * Perform BL2 preload setup. Currently we initialise the dynamic
84 * configuration here.
Dan Handley9df48042015-03-19 18:58:55 +000085 */
Soby Mathew45e39e22018-03-26 15:16:46 +010086void bl2_plat_preload_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +000087{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000088 arm_bl2_dyn_cfg_init();
Soby Mathew45e39e22018-03-26 15:16:46 +010089}
Soby Mathew96a1c6b2018-01-15 14:45:33 +000090
Soby Mathew45e39e22018-03-26 15:16:46 +010091/*
92 * Perform ARM standard platform setup.
93 */
94void arm_bl2_platform_setup(void)
95{
Dan Handley9df48042015-03-19 18:58:55 +000096 /* Initialize the secure environment */
97 plat_arm_security_setup();
Roberto Vargasa1c16b62017-08-03 09:16:43 +010098
99#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargas550eb082018-01-05 16:00:05 +0000100 arm_nor_psci_do_static_mem_protect();
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100101#endif
Dan Handley9df48042015-03-19 18:58:55 +0000102}
103
104void bl2_platform_setup(void)
105{
106 arm_bl2_platform_setup();
107}
108
109/*******************************************************************************
110 * Perform the very early platform specific architectural setup here. At the
111 * moment this is only initializes the mmu in a quick and dirty way.
112 ******************************************************************************/
113void arm_bl2_plat_arch_setup(void)
114{
Soby Mathewb9856482018-09-18 11:42:42 +0100115#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
116 /*
117 * Ensure ARM platforms don't use coherent memory in BL2 unless
118 * cryptocell integration is enabled.
119 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100120 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000121#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100122
123 const mmap_region_t bl_regions[] = {
124 MAP_BL2_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100125 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100126#if USE_ROMLIB
127 ARM_MAP_ROMLIB_CODE,
128 ARM_MAP_ROMLIB_DATA,
129#endif
Soby Mathewb9856482018-09-18 11:42:42 +0100130#if ARM_CRYPTOCELL_INTEG
131 ARM_MAP_BL_COHERENT_RAM,
132#endif
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100133 ARM_MAP_BL_CONFIG_REGION,
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100134 {0}
135 };
136
Roberto Vargas344ff022018-10-19 16:44:18 +0100137 setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100138
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700139#ifdef __aarch64__
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100140 enable_mmu_el1(0);
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700141#else
142 enable_mmu_svc_mon(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100143#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100144
145 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000146}
147
148void bl2_plat_arch_setup(void)
149{
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100150 const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
151
Dan Handley9df48042015-03-19 18:58:55 +0000152 arm_bl2_plat_arch_setup();
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100153
154 /* Fill the properties struct with the info from the config dtb */
Jimmy Brissond7297c72020-08-05 14:05:53 -0500155 fconf_populate("FW_CONFIG", config_base);
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100156
157 /* TB_FW_CONFIG was also loaded by BL1 */
158 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID);
159 assert(tb_fw_config_info != NULL);
160
161 fconf_populate("TB_FW", tb_fw_config_info->config_addr);
Dan Handley9df48042015-03-19 18:58:55 +0000162}
163
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000164int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100165{
166 int err = 0;
167 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100168#ifdef SPD_opteed
169 bl_mem_params_node_t *pager_mem_params = NULL;
170 bl_mem_params_node_t *paged_mem_params = NULL;
171#endif
Zelaleme8dadb12020-02-05 14:12:39 -0600172 assert(bl_mem_params != NULL);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100173
174 switch (image_id) {
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700175#ifdef __aarch64__
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100176 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100177#ifdef SPD_opteed
178 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
179 assert(pager_mem_params);
180
181 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
182 assert(paged_mem_params);
183
184 err = parse_optee_header(&bl_mem_params->ep_info,
185 &pager_mem_params->image_info,
186 &paged_mem_params->image_info);
187 if (err != 0) {
188 WARN("OPTEE header parse error.\n");
189 }
190#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100191 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
192 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100193#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100194
195 case BL33_IMAGE_ID:
196 /* BL33 expects to receive the primary CPU MPID (through r0) */
197 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
198 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
199 break;
200
201#ifdef SCP_BL2_BASE
202 case SCP_BL2_IMAGE_ID:
203 /* The subsequent handling of SCP_BL2 is platform specific */
204 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
205 if (err) {
206 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
207 }
208 break;
209#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000210 default:
211 /* Do nothing in default case */
212 break;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100213 }
214
215 return err;
216}
217
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000218/*******************************************************************************
219 * This function can be used by the platforms to update/use image
220 * information for given `image_id`.
221 ******************************************************************************/
Daniel Boulby07d26872018-06-27 16:45:48 +0100222int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000223{
Olivier Deprez042db532020-03-19 09:27:11 +0100224#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
Manish Pandey1fa6ecb2020-02-25 11:38:19 +0000225 /* For Secure Partitions we don't need post processing */
226 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) &&
227 (image_id < MAX_NUMBER_IDS)) {
228 return 0;
229 }
230#endif
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000231 return arm_bl2_handle_post_image_load(image_id);
232}
233
Daniel Boulby07d26872018-06-27 16:45:48 +0100234int bl2_plat_handle_post_image_load(unsigned int image_id)
235{
236 return arm_bl2_plat_handle_post_image_load(image_id);
237}
Alexei Fedorovc7176172020-07-13 12:11:05 +0100238
239#if MEASURED_BOOT
240/* Read TCG_DIGEST_SIZE bytes of BL2 hash data */
241void bl2_plat_get_hash(void *data)
242{
243 arm_bl2_get_hash(data);
244}
245#endif