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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Zelaleme8dadb12020-02-05 14:12:39 -06002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
10#include <platform_def.h>
11
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
15#include <common/desc_image_load.h>
16#include <drivers/generic_delay_timer.h>
Louis Mayencourt81bd9162019-10-17 15:14:25 +010017#include <lib/fconf/fconf.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010018#ifdef SPD_opteed
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <lib/optee_utils.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010020#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000021#include <lib/utils.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000022#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <plat/common/platform.h>
24
Dan Handley9df48042015-03-19 18:58:55 +000025/* Data structure which holds the extents of the trusted SRAM for BL2 */
26static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
27
Soby Mathewc44110d2018-02-20 12:50:47 +000028/*
Soby Mathewaf14b462018-06-01 16:53:38 +010029 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is
30 * for `meminfo_t` data structure and fw_configs passed from BL1.
Soby Mathewc44110d2018-02-20 12:50:47 +000031 */
Soby Mathewaf14b462018-06-01 16:53:38 +010032CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
Soby Mathewc44110d2018-02-20 12:50:47 +000033
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010034/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000035#pragma weak bl2_early_platform_setup2
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010036#pragma weak bl2_platform_setup
37#pragma weak bl2_plat_arch_setup
38#pragma weak bl2_plat_sec_mem_layout
39
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010040#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
41 bl2_tzram_layout.total_base, \
42 bl2_tzram_layout.total_size, \
43 MT_MEMORY | MT_RW | MT_SECURE)
44
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010045
Daniel Boulby07d26872018-06-27 16:45:48 +010046#pragma weak arm_bl2_plat_handle_post_image_load
Dimitris Papastamos9576baa2018-06-08 13:17:26 +010047
Dan Handley9df48042015-03-19 18:58:55 +000048/*******************************************************************************
49 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
50 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
51 * Copy it to a safe location before its reclaimed by later BL2 functionality.
52 ******************************************************************************/
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020053void arm_bl2_early_platform_setup(uintptr_t tb_fw_config,
54 struct meminfo *mem_layout)
Dan Handley9df48042015-03-19 18:58:55 +000055{
56 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010057 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000058
59 /* Setup the BL2 memory layout */
60 bl2_tzram_layout = *mem_layout;
61
Louis Mayencourt81bd9162019-10-17 15:14:25 +010062 /* Fill the properties struct with the info from the config dtb */
63 if (tb_fw_config != 0U) {
Madhukar Pappireddy81519692019-12-06 15:46:42 -060064 fconf_populate("TB_FW", tb_fw_config);
Louis Mayencourt81bd9162019-10-17 15:14:25 +010065 }
66
Dan Handley9df48042015-03-19 18:58:55 +000067 /* Initialise the IO layer and register platform IO devices */
68 plat_arm_io_setup();
69}
70
Soby Mathew7d5a2e72018-01-10 15:59:31 +000071void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +000072{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000073 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
74
Soby Mathew1ced6b82017-06-12 12:37:10 +010075 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +000076}
77
78/*
Soby Mathew45e39e22018-03-26 15:16:46 +010079 * Perform BL2 preload setup. Currently we initialise the dynamic
80 * configuration here.
Dan Handley9df48042015-03-19 18:58:55 +000081 */
Soby Mathew45e39e22018-03-26 15:16:46 +010082void bl2_plat_preload_setup(void)
Dan Handley9df48042015-03-19 18:58:55 +000083{
Soby Mathew96a1c6b2018-01-15 14:45:33 +000084 arm_bl2_dyn_cfg_init();
Soby Mathew45e39e22018-03-26 15:16:46 +010085}
Soby Mathew96a1c6b2018-01-15 14:45:33 +000086
Soby Mathew45e39e22018-03-26 15:16:46 +010087/*
88 * Perform ARM standard platform setup.
89 */
90void arm_bl2_platform_setup(void)
91{
Dan Handley9df48042015-03-19 18:58:55 +000092 /* Initialize the secure environment */
93 plat_arm_security_setup();
Roberto Vargasa1c16b62017-08-03 09:16:43 +010094
95#if defined(PLAT_ARM_MEM_PROT_ADDR)
Roberto Vargas550eb082018-01-05 16:00:05 +000096 arm_nor_psci_do_static_mem_protect();
Roberto Vargasa1c16b62017-08-03 09:16:43 +010097#endif
Dan Handley9df48042015-03-19 18:58:55 +000098}
99
100void bl2_platform_setup(void)
101{
102 arm_bl2_platform_setup();
103}
104
105/*******************************************************************************
106 * Perform the very early platform specific architectural setup here. At the
107 * moment this is only initializes the mmu in a quick and dirty way.
108 ******************************************************************************/
109void arm_bl2_plat_arch_setup(void)
110{
Soby Mathewb9856482018-09-18 11:42:42 +0100111#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
112 /*
113 * Ensure ARM platforms don't use coherent memory in BL2 unless
114 * cryptocell integration is enabled.
115 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100116 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000117#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100118
119 const mmap_region_t bl_regions[] = {
120 MAP_BL2_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100121 ARM_MAP_BL_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100122#if USE_ROMLIB
123 ARM_MAP_ROMLIB_CODE,
124 ARM_MAP_ROMLIB_DATA,
125#endif
Soby Mathewb9856482018-09-18 11:42:42 +0100126#if ARM_CRYPTOCELL_INTEG
127 ARM_MAP_BL_COHERENT_RAM,
128#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100129 {0}
130 };
131
Roberto Vargas344ff022018-10-19 16:44:18 +0100132 setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100133
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700134#ifdef __aarch64__
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100135 enable_mmu_el1(0);
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700136#else
137 enable_mmu_svc_mon(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100138#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100139
140 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000141}
142
143void bl2_plat_arch_setup(void)
144{
145 arm_bl2_plat_arch_setup();
146}
147
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000148int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100149{
150 int err = 0;
151 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100152#ifdef SPD_opteed
153 bl_mem_params_node_t *pager_mem_params = NULL;
154 bl_mem_params_node_t *paged_mem_params = NULL;
155#endif
Zelaleme8dadb12020-02-05 14:12:39 -0600156 assert(bl_mem_params != NULL);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100157
158 switch (image_id) {
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700159#ifdef __aarch64__
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100160 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100161#ifdef SPD_opteed
162 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
163 assert(pager_mem_params);
164
165 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
166 assert(paged_mem_params);
167
168 err = parse_optee_header(&bl_mem_params->ep_info,
169 &pager_mem_params->image_info,
170 &paged_mem_params->image_info);
171 if (err != 0) {
172 WARN("OPTEE header parse error.\n");
173 }
174#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100175 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
176 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100177#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100178
179 case BL33_IMAGE_ID:
180 /* BL33 expects to receive the primary CPU MPID (through r0) */
181 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
182 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
183 break;
184
185#ifdef SCP_BL2_BASE
186 case SCP_BL2_IMAGE_ID:
187 /* The subsequent handling of SCP_BL2 is platform specific */
188 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
189 if (err) {
190 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
191 }
192 break;
193#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000194 default:
195 /* Do nothing in default case */
196 break;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100197 }
198
199 return err;
200}
201
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000202/*******************************************************************************
203 * This function can be used by the platforms to update/use image
204 * information for given `image_id`.
205 ******************************************************************************/
Daniel Boulby07d26872018-06-27 16:45:48 +0100206int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000207{
Olivier Deprez042db532020-03-19 09:27:11 +0100208#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
Manish Pandey1fa6ecb2020-02-25 11:38:19 +0000209 /* For Secure Partitions we don't need post processing */
210 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) &&
211 (image_id < MAX_NUMBER_IDS)) {
212 return 0;
213 }
214#endif
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000215 return arm_bl2_handle_post_image_load(image_id);
216}
217
Daniel Boulby07d26872018-06-27 16:45:48 +0100218int bl2_plat_handle_post_image_load(unsigned int image_id)
219{
220 return arm_bl2_plat_handle_post_image_load(image_id);
221}