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Isla Mitchellea84d6b2017-08-03 16:04:46 +01001/*
Bipin Ravi86499742022-01-18 01:59:06 -06002 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
Isla Mitchellea84d6b2017-08-03 16:04:46 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
John Tsichritzis56369c12019-02-19 13:49:06 +00007#ifndef NEOVERSE_N1_H
8#define NEOVERSE_N1_H
Antonio Nino Diaz9fe40fd2018-10-25 17:11:02 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Isla Mitchellea84d6b2017-08-03 16:04:46 +010011
John Tsichritzis56369c12019-02-19 13:49:06 +000012/* Neoverse N1 MIDR for revision 0 */
Bipin Ravi86499742022-01-18 01:59:06 -060013#define NEOVERSE_N1_MIDR U(0x410fd0c0)
14
15/* Neoverse N1 loop count for CVE-2022-23960 mitigation */
16#define NEOVERSE_N1_BHB_LOOP_COUNT U(24)
Isla Mitchellea84d6b2017-08-03 16:04:46 +010017
laurenw-arm94accd32019-08-20 15:51:24 -050018/* Exception Syndrome register EC code for IC Trap */
Bipin Ravi86499742022-01-18 01:59:06 -060019#define NEOVERSE_N1_EC_IC_TRAP U(0x1f)
laurenw-arm94accd32019-08-20 15:51:24 -050020
Isla Mitchellea84d6b2017-08-03 16:04:46 +010021/*******************************************************************************
Louis Mayencourtb58142b2019-04-18 14:34:11 +010022 * CPU Power Control register specific definitions.
Isla Mitchellea84d6b2017-08-03 16:04:46 +010023 ******************************************************************************/
Bipin Ravi86499742022-01-18 01:59:06 -060024#define NEOVERSE_N1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
Isla Mitchellea84d6b2017-08-03 16:04:46 +010025
John Tsichritzis56369c12019-02-19 13:49:06 +000026/* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */
Bipin Ravi86499742022-01-18 01:59:06 -060027#define NEOVERSE_N1_CORE_PWRDN_EN_MASK U(0x1)
Isla Mitchellea84d6b2017-08-03 16:04:46 +010028
Bipin Ravi86499742022-01-18 01:59:06 -060029#define NEOVERSE_N1_ACTLR_AMEN_BIT (U(1) << 4)
Dimitris Papastamos89736dd2018-02-13 11:28:02 +000030
Bipin Ravi86499742022-01-18 01:59:06 -060031#define NEOVERSE_N1_AMU_NR_COUNTERS U(5)
32#define NEOVERSE_N1_AMU_GROUP0_MASK U(0x1f)
Dimitris Papastamos89736dd2018-02-13 11:28:02 +000033
Louis Mayencourtb58142b2019-04-18 14:34:11 +010034/*******************************************************************************
35 * CPU Extended Control register specific definitions.
36 ******************************************************************************/
Bipin Ravi86499742022-01-18 01:59:06 -060037#define NEOVERSE_N1_CPUECTLR_EL1 S3_0_C15_C1_4
Louis Mayencourtb58142b2019-04-18 14:34:11 +010038
Bipin Ravi86499742022-01-18 01:59:06 -060039#define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
lauwal0100396bf2019-06-24 11:47:30 -050040#define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
Manish Pandey3880a362020-01-24 11:54:44 +000041#define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
lauwal01197f14c2019-06-24 11:38:53 -050042
Louis Mayencourtb58142b2019-04-18 14:34:11 +010043/*******************************************************************************
44 * CPU Auxiliary Control register specific definitions.
45 ******************************************************************************/
Bipin Ravi86499742022-01-18 01:59:06 -060046#define NEOVERSE_N1_CPUACTLR_EL1 S3_0_C15_C1_0
lauwal01bd555f42019-06-24 11:23:50 -050047
Bipin Ravi86499742022-01-18 01:59:06 -060048#define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
49#define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
lauwal01bd555f42019-06-24 11:23:50 -050050
Bipin Ravi86499742022-01-18 01:59:06 -060051#define NEOVERSE_N1_CPUACTLR2_EL1 S3_0_C15_C1_1
Louis Mayencourtb58142b2019-04-18 14:34:11 +010052
Bipin Ravi86499742022-01-18 01:59:06 -060053#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
54#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
55#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
56#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
57#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
58#define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
lauwal01363ee3c2019-06-24 11:28:34 -050059
Bipin Ravi86499742022-01-18 01:59:06 -060060#define NEOVERSE_N1_CPUACTLR3_EL1 S3_0_C15_C1_2
lauwal0107c2a232019-06-24 11:42:02 -050061
Bipin Ravi86499742022-01-18 01:59:06 -060062#define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
Louis Mayencourtb58142b2019-04-18 14:34:11 +010063
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +010064/* Instruction patching registers */
Bipin Ravi86499742022-01-18 01:59:06 -060065#define CPUPSELR_EL3 S3_6_C15_C8_0
66#define CPUPCR_EL3 S3_6_C15_C8_1
67#define CPUPOR_EL3 S3_6_C15_C8_2
68#define CPUPMR_EL3 S3_6_C15_C8_3
Dimitris Papastamos7ca21db2018-03-26 16:46:01 +010069
John Tsichritzis56369c12019-02-19 13:49:06 +000070#endif /* NEOVERSE_N1_H */