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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handleyed6ff952014-05-14 17:44:19 +010031#include <platform_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000035ENTRY(bl1_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
37MEMORY {
Juan Castillo0c70c572014-08-12 13:04:43 +010038 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT
39 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT
Achin Gupta4f6ad662013-10-25 09:08:21 +010040}
41
42SECTIONS
43{
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010044 . = BL1_RO_BASE;
45 ASSERT(. == ALIGN(4096),
46 "BL1_RO_BASE address is not aligned on a page boundary.")
47
48 ro . : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000049 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000050 *bl1_entrypoint.o(.text*)
51 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000052 *(.rodata*)
Achin Guptab739f222014-01-18 16:50:09 +000053 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000054 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010055 } >ROM
56
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000057 /*
58 * The .data section gets copied from ROM to RAM at runtime.
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010059 * Its LMA must be 16-byte aligned.
60 * Its VMA must be page-aligned as it marks the first read/write page.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000061 */
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010062 . = BL1_RW_BASE;
63 ASSERT(. == ALIGN(4096),
64 "BL1_RW_BASE address is not aligned on a page boundary.")
65 .data . : ALIGN(16) {
Achin Gupta4f6ad662013-10-25 09:08:21 +010066 __DATA_RAM_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000067 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000068 __DATA_RAM_END__ = .;
69 } >RAM AT>ROM
Achin Gupta4f6ad662013-10-25 09:08:21 +010070
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010071 stacks . (NOLOAD) : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000072 __STACKS_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010073 *(tzfw_normal_stacks)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000074 __STACKS_END__ = .;
75 } >RAM
76
77 /*
78 * The .bss section gets initialised to 0 at runtime.
79 * Its base address must be 16-byte aligned.
80 */
81 .bss : ALIGN(16) {
82 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000083 *(.bss*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000084 *(COMMON)
85 __BSS_END__ = .;
86 } >RAM
Achin Gupta4f6ad662013-10-25 09:08:21 +010087
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000088 /*
Achin Guptaa0cd9892014-02-09 13:30:38 +000089 * The xlat_table section is for full, aligned page tables (4K).
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +000090 * Removing them from .bss avoids forcing 4K alignment on
91 * the .bss section and eliminates the unecessary zero init
92 */
93 xlat_table (NOLOAD) : {
94 *(xlat_table)
95 } >RAM
96
97 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000098 * The base address of the coherent memory section must be page-aligned (4K)
99 * to guarantee that the coherent data are stored on their own pages and
100 * are not mixed with normal data. This is required to set up the correct
101 * memory attributes for the coherent data page tables.
102 */
103 coherent_ram (NOLOAD) : ALIGN(4096) {
104 __COHERENT_RAM_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105 *(tzfw_coherent_mem)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000106 __COHERENT_RAM_END_UNALIGNED__ = .;
107 /*
108 * Memory page(s) mapped to this section will be marked
109 * as device memory. No other unexpected data must creep in.
110 * Ensure the rest of the current memory page is unused.
111 */
112 . = NEXT(4096);
113 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100114 } >RAM
115
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000116 __BL1_RAM_START__ = ADDR(.data);
117 __BL1_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100118
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000119 __DATA_ROM_START__ = LOADADDR(.data);
120 __DATA_SIZE__ = SIZEOF(.data);
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100121 /*
122 * The .data section is the last PROGBITS section so its end marks the end
123 * of the read-only part of BL1's binary.
124 */
125 ASSERT(__DATA_ROM_START__ + __DATA_SIZE__ <= BL1_RO_LIMIT,
126 "BL1's RO section has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000128 __BSS_SIZE__ = SIZEOF(.bss);
129
130 __COHERENT_RAM_UNALIGNED_SIZE__ =
131 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100132
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100133 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100134}