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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
Joel Hutton5cc3bc82018-03-21 11:40:57 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05305 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <errno.h>
9#include <stddef.h>
10#include <string.h>
11
12#include <platform_def.h>
13
Varun Wadekarb316e242015-05-19 16:48:04 +053014#include <arch.h>
15#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <bl31/bl31.h>
17#include <common/bl_common.h>
18#include <common/debug.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053019#include <cortex_a53.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010020#include <cortex_a57.h>
Varun Wadekarbaf903e2015-09-22 15:00:06 +053021#include <denver.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000022#include <drivers/console.h>
23#include <lib/mmio.h>
24#include <lib/utils.h>
25#include <lib/utils_def.h>
26#include <plat/common/platform.h>
27
Varun Wadekarb316e242015-05-19 16:48:04 +053028#include <memctrl.h>
Varun Wadekar0dc91812015-12-30 15:06:41 -080029#include <tegra_def.h>
Harvey Hsieh9e083c72017-04-10 16:20:32 +080030#include <tegra_platform.h>
Varun Wadekarb316e242015-05-19 16:48:04 +053031#include <tegra_private.h>
32
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080033/* length of Trusty's input parameters (in bytes) */
34#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
35
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010036extern void memcpy16(void *dest, const void *src, unsigned int length);
Varun Wadekarb41a4142016-05-23 15:56:14 -070037
Varun Wadekarb316e242015-05-19 16:48:04 +053038/*******************************************************************************
39 * Declarations of linker defined symbols which will help us find the layout
40 * of trusted SRAM
41 ******************************************************************************/
Joel Hutton5cc3bc82018-03-21 11:40:57 +000042
43IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
44IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
45IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE);
46IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END);
47IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START);
48IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END);
Varun Wadekarb316e242015-05-19 16:48:04 +053049
Varun Wadekarb316e242015-05-19 16:48:04 +053050extern uint64_t tegra_bl31_phys_base;
Varun Wadekard2014c62015-10-29 10:37:28 +053051extern uint64_t tegra_console_base;
Varun Wadekarb316e242015-05-19 16:48:04 +053052
Varun Wadekarb316e242015-05-19 16:48:04 +053053
Varun Wadekar52a15982015-06-05 12:57:27 +053054static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
Varun Wadekarb316e242015-05-19 16:48:04 +053055static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
Varun Wadekarc8bfe2e2015-07-31 10:03:01 +053056 .tzdram_size = (uint64_t)TZDRAM_SIZE
Varun Wadekarb316e242015-05-19 16:48:04 +053057};
Arve Hjønnevåg8f539492018-02-21 17:36:44 -080058static unsigned long bl32_mem_size;
59static unsigned long bl32_boot_params;
Varun Wadekarb316e242015-05-19 16:48:04 +053060
61/*******************************************************************************
62 * This variable holds the non-secure image entry address
63 ******************************************************************************/
64extern uint64_t ns_image_entrypoint;
65
66/*******************************************************************************
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070067 * The following platform setup functions are weakly defined. They
68 * provide typical implementations that will be overridden by a SoC.
69 ******************************************************************************/
70#pragma weak plat_early_platform_setup
Varun Wadekard22d4ad2016-05-23 11:41:07 -070071#pragma weak plat_get_bl31_params
72#pragma weak plat_get_bl31_plat_params
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070073
74void plat_early_platform_setup(void)
75{
76 ; /* do nothing */
77}
78
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +010079struct tegra_bl31_params *plat_get_bl31_params(void)
Varun Wadekard22d4ad2016-05-23 11:41:07 -070080{
81 return NULL;
82}
83
84plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
85{
86 return NULL;
87}
88
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -070089/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +053090 * Return a pointer to the 'entry_point_info' structure of the next image for
91 * security state specified. BL33 corresponds to the non-secure image type
92 * while BL32 corresponds to the secure image type.
93 ******************************************************************************/
94entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
95{
96 if (type == NON_SECURE)
97 return &bl33_image_ep_info;
98
Varun Wadekar197a75f2016-06-06 10:46:28 -070099 /* return BL32 entry point info if it is valid */
100 if (type == SECURE && bl32_image_ep_info.pc)
Varun Wadekar52a15982015-06-05 12:57:27 +0530101 return &bl32_image_ep_info;
102
Varun Wadekarb316e242015-05-19 16:48:04 +0530103 return NULL;
104}
105
106/*******************************************************************************
107 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
108 * passes this platform specific information.
109 ******************************************************************************/
110plat_params_from_bl2_t *bl31_get_plat_params(void)
111{
112 return &plat_bl31_params_from_bl2;
113}
114
115/*******************************************************************************
116 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
117 * info.
118 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100119void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
120 u_register_t arg2, u_register_t arg3)
Varun Wadekarb316e242015-05-19 16:48:04 +0530121{
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100122 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
123 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
Varun Wadekarb41a4142016-05-23 15:56:14 -0700124 image_info_t bl32_img_info = { {0} };
125 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800126 uint32_t console_clock;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530127
Varun Wadekarb316e242015-05-19 16:48:04 +0530128 /*
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700129 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
130 * there's no argument to relay from a previous bootloader. Platforms
131 * might use custom ways to get arguments, so provide handlers which
132 * they can override.
133 */
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100134 if (arg_from_bl2 == NULL)
135 arg_from_bl2 = plat_get_bl31_params();
Varun Wadekard22d4ad2016-05-23 11:41:07 -0700136 if (plat_params == NULL)
137 plat_params = plat_get_bl31_plat_params();
138
139 /*
Varun Wadekar52a15982015-06-05 12:57:27 +0530140 * Copy BL3-3, BL3-2 entry point information.
Varun Wadekarb316e242015-05-19 16:48:04 +0530141 * They are stored in Secure RAM, in BL2's address space.
142 */
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100143 assert(arg_from_bl2);
144 assert(arg_from_bl2->bl33_ep_info);
145 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530146
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100147 if (arg_from_bl2->bl32_ep_info) {
148 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
149 bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
150 bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800151 }
Varun Wadekarb316e242015-05-19 16:48:04 +0530152
153 /*
Varun Wadekar6bb62462015-10-06 12:49:31 +0530154 * Parse platform specific parameters - TZDRAM aperture base and size
Varun Wadekarb316e242015-05-19 16:48:04 +0530155 */
Varun Wadekar6bb62462015-10-06 12:49:31 +0530156 assert(plat_params);
157 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
158 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
Varun Wadekard2014c62015-10-29 10:37:28 +0530159 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800160 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
Varun Wadekard2014c62015-10-29 10:37:28 +0530161
162 /*
Varun Wadekar1ec441e2016-03-24 15:34:24 -0700163 * It is very important that we run either from TZDRAM or TZSRAM base.
164 * Add an explicit check here.
165 */
166 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) &&
167 (TEGRA_TZRAM_BASE != BL31_BASE))
168 panic();
169
170 /*
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800171 * Reference clock used by the FPGAs is a lot slower.
172 */
173 if (tegra_platform_is_fpga() == 1U) {
174 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
175 } else {
176 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
177 }
178
179 /*
Varun Wadekard2014c62015-10-29 10:37:28 +0530180 * Get the base address of the UART controller to be used for the
181 * console
182 */
Varun Wadekard2014c62015-10-29 10:37:28 +0530183 tegra_console_base = plat_get_console_from_id(plat_params->uart_id);
184
Damon Duan777baa52016-11-07 19:37:50 +0800185 if (tegra_console_base != (uint64_t)0) {
186 /*
187 * Configure the UART port to be used as the console
188 */
Harvey Hsieh9e083c72017-04-10 16:20:32 +0800189 console_init(tegra_console_base, console_clock,
190 TEGRA_CONSOLE_BAUDRATE);
Damon Duan777baa52016-11-07 19:37:50 +0800191 }
Varun Wadekard2014c62015-10-29 10:37:28 +0530192
Varun Wadekar5118b532016-06-04 22:08:50 -0700193 /*
Steven Kao27e64312016-10-21 14:16:59 +0800194 * Initialize delay timer
195 */
196 tegra_delay_timer_init();
197
198 /*
Varun Wadekar5118b532016-06-04 22:08:50 -0700199 * Do initial security configuration to allow DRAM/device access.
200 */
201 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
202 plat_bl31_params_from_bl2.tzdram_size);
203
Varun Wadekarb41a4142016-05-23 15:56:14 -0700204 /*
205 * The previous bootloader might not have placed the BL32 image
206 * inside the TZDRAM. We check the BL32 image info to find out
207 * the base/PC values and relocate the image if necessary.
208 */
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100209 if (arg_from_bl2->bl32_image_info) {
Varun Wadekarb41a4142016-05-23 15:56:14 -0700210
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100211 bl32_img_info = *arg_from_bl2->bl32_image_info;
Varun Wadekarb41a4142016-05-23 15:56:14 -0700212
213 /* Relocate BL32 if it resides outside of the TZDRAM */
214 tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
215 tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
216 plat_bl31_params_from_bl2.tzdram_size;
217 bl32_start = bl32_img_info.image_base;
218 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
219
220 assert(tzdram_end > tzdram_start);
221 assert(bl32_end > bl32_start);
222 assert(bl32_image_ep_info.pc > tzdram_start);
223 assert(bl32_image_ep_info.pc < tzdram_end);
224
225 /* relocate BL32 */
226 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) {
227
228 INFO("Relocate BL32 to TZDRAM\n");
229
230 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
231 (void *)(uintptr_t)bl32_start,
232 bl32_img_info.image_size);
233
234 /* clean up non-secure intermediate buffer */
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100235 zeromem((void *)(uintptr_t)bl32_start,
Varun Wadekarb41a4142016-05-23 15:56:14 -0700236 bl32_img_info.image_size);
237 }
238 }
239
Varun Wadekar3f0a8ad2016-03-28 15:56:47 -0700240 /* Early platform setup for Tegra SoCs */
241 plat_early_platform_setup();
242
Sandrine Bailleuxfff61b62018-06-21 11:41:43 +0200243 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
244 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
245 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
Varun Wadekarb316e242015-05-19 16:48:04 +0530246}
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800247
248#ifdef SPD_trusty
249void plat_trusty_set_boot_args(aapcs64_params_t *args)
250{
251 args->arg0 = bl32_mem_size;
252 args->arg1 = bl32_boot_params;
253 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
Varun Wadekarc2099802018-12-28 13:50:20 -0800254
255 /* update EKS size */
256 if (args->arg4 != 0U) {
257 args->arg2 = args->arg4;
258 }
Arve Hjønnevåg8f539492018-02-21 17:36:44 -0800259}
260#endif
Varun Wadekarb316e242015-05-19 16:48:04 +0530261
262/*******************************************************************************
263 * Initialize the gic, configure the SCR.
264 ******************************************************************************/
265void bl31_platform_setup(void)
266{
267 uint32_t tmp_reg;
268
Varun Wadekarb7b45752015-12-28 14:55:41 -0800269 /* Initialize the gic cpu and distributor interfaces */
270 plat_gic_setup();
271
Varun Wadekarb316e242015-05-19 16:48:04 +0530272 /*
273 * Setup secondary CPU POR infrastructure.
274 */
275 plat_secondary_setup();
276
277 /*
278 * Initial Memory Controller configuration.
279 */
280 tegra_memctrl_setup();
281
282 /*
Varun Wadekar0dc91812015-12-30 15:06:41 -0800283 * Set up the TZRAM memory aperture to allow only secure world
284 * access
285 */
286 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
287
Varun Wadekarb316e242015-05-19 16:48:04 +0530288 /* Set the next EL to be AArch64 */
289 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT;
290 write_scr(tmp_reg);
291
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530292 INFO("BL3-1: Tegra platform setup complete\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530293}
294
295/*******************************************************************************
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800296 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
297 ******************************************************************************/
298void bl31_plat_runtime_setup(void)
299{
Varun Wadekarc92050b2017-03-29 14:57:29 -0700300 /*
301 * During boot, USB3 and flash media (SDMMC/SATA) devices need
302 * access to IRAM. Because these clients connect to the MC and
303 * do not have a direct path to the IRAM, the MC implements AHB
304 * redirection during boot to allow path to IRAM. In this mode
305 * accesses to a programmed memory address aperture are directed
306 * to the AHB bus, allowing access to the IRAM. This mode must be
307 * disabled before we jump to the non-secure world.
308 */
309 tegra_memctrl_disable_ahb_redirection();
Varun Wadekar1dcffa92016-01-08 17:48:42 -0800310}
311
312/*******************************************************************************
Varun Wadekarb316e242015-05-19 16:48:04 +0530313 * Perform the very early platform specific architectural setup here. At the
314 * moment this only intializes the mmu in a quick and dirty way.
315 ******************************************************************************/
316void bl31_plat_arch_setup(void)
317{
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800318 unsigned long rw_start = BL31_RW_START;
319 unsigned long rw_size = BL31_RW_END - BL31_RW_START;
320 unsigned long rodata_start = BL31_RODATA_BASE;
321 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
Joel Hutton5cc3bc82018-03-21 11:40:57 +0000322 unsigned long code_base = TEXT_START;
323 unsigned long code_size = TEXT_END - TEXT_START;
Varun Wadekarb316e242015-05-19 16:48:04 +0530324 const mmap_region_t *plat_mmio_map = NULL;
Varun Wadekarb316e242015-05-19 16:48:04 +0530325#if USE_COHERENT_MEM
Varun Wadekar207cc732015-07-08 12:57:50 +0530326 unsigned long coh_start, coh_size;
Varun Wadekarb316e242015-05-19 16:48:04 +0530327#endif
Varun Wadekard1513632016-03-18 13:01:12 -0700328 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
Varun Wadekarb316e242015-05-19 16:48:04 +0530329
330 /* add memory regions */
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800331 mmap_add_region(rw_start, rw_start,
332 rw_size,
Varun Wadekarb316e242015-05-19 16:48:04 +0530333 MT_MEMORY | MT_RW | MT_SECURE);
Varun Wadekar3fb854f2017-02-28 08:23:59 -0800334 mmap_add_region(rodata_start, rodata_start,
335 rodata_size,
336 MT_RO_DATA | MT_SECURE);
337 mmap_add_region(code_base, code_base,
338 code_size,
339 MT_CODE | MT_SECURE);
Varun Wadekar207cc732015-07-08 12:57:50 +0530340
Varun Wadekard1513632016-03-18 13:01:12 -0700341 /* map TZDRAM used by BL31 as coherent memory */
342 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
343 mmap_add_region(params_from_bl2->tzdram_base,
344 params_from_bl2->tzdram_base,
345 BL31_SIZE,
346 MT_DEVICE | MT_RW | MT_SECURE);
347 }
348
Varun Wadekarb316e242015-05-19 16:48:04 +0530349#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900350 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
351 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
Varun Wadekar207cc732015-07-08 12:57:50 +0530352
Varun Wadekarb316e242015-05-19 16:48:04 +0530353 mmap_add_region(coh_start, coh_start,
354 coh_size,
355 MT_DEVICE | MT_RW | MT_SECURE);
356#endif
357
Steven Kao4d160ac2016-12-23 16:05:13 +0800358 /* map on-chip free running uS timer */
359 mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
360 page_align((uint64_t)TEGRA_TMRUS_BASE, 0),
361 (uint64_t)TEGRA_TMRUS_SIZE,
362 MT_DEVICE | MT_RO | MT_SECURE);
363
Varun Wadekarb316e242015-05-19 16:48:04 +0530364 /* add MMIO space */
365 plat_mmio_map = plat_get_mmio_map();
366 if (plat_mmio_map)
367 mmap_add(plat_mmio_map);
368 else
369 WARN("MMIO map not available\n");
370
371 /* set up translation tables */
372 init_xlat_tables();
373
374 /* enable the MMU */
375 enable_mmu_el3(0);
Varun Wadekarbaf903e2015-09-22 15:00:06 +0530376
377 INFO("BL3-1: Tegra: MMU enabled\n");
Varun Wadekarb316e242015-05-19 16:48:04 +0530378}
Varun Wadekar7a269e22015-06-10 14:04:32 +0530379
380/*******************************************************************************
381 * Check if the given NS DRAM range is valid
382 ******************************************************************************/
383int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
384{
Varun Wadekar55902982017-01-25 13:35:27 -0800385 uint64_t end = base + size_in_bytes;
Varun Wadekar7a269e22015-06-10 14:04:32 +0530386
387 /*
388 * Check if the NS DRAM address is valid
389 */
Varun Wadekar55902982017-01-25 13:35:27 -0800390 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) {
Varun Wadekar7a269e22015-06-10 14:04:32 +0530391 ERROR("NS address is out-of-bounds!\n");
392 return -EFAULT;
393 }
394
395 /*
396 * TZDRAM aperture contains the BL31 and BL32 images, so we need
397 * to check if the NS DRAM range overlaps the TZDRAM aperture.
398 */
399 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) {
400 ERROR("NS address overlaps TZDRAM!\n");
401 return -ENOTSUP;
402 }
403
404 /* valid NS address */
405 return 0;
406}