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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -06002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <assert.h>
Soby Mathew981487a2015-07-13 14:10:57 +01008#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch.h>
11#include <arch_helpers.h>
12#include <common/debug.h>
13#include <lib/pmf/pmf.h>
14#include <lib/runtime_instr.h>
15#include <lib/smccc.h>
16#include <plat/common/platform.h>
17#include <services/arm_arch_svc.h>
18
Dan Handley714a0d22014-04-09 13:13:04 +010019#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
21/*******************************************************************************
22 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
23 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010024int psci_cpu_on(u_register_t target_cpu,
25 uintptr_t entrypoint,
26 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010027
28{
29 int rc;
Soby Mathew8595b872015-01-06 15:36:38 +000030 entry_point_info_t ep;
Achin Gupta4f6ad662013-10-25 09:08:21 +010031
32 /* Determine if the cpu exists of not */
Soby Mathew981487a2015-07-13 14:10:57 +010033 rc = psci_validate_mpidr(target_cpu);
34 if (rc != PSCI_E_SUCCESS)
Soby Mathew74e52a72014-10-02 16:56:51 +010035 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010036
Soby Mathewf1f97a12015-07-15 12:13:26 +010037 /* Validate the entry point and get the entry_point_info */
38 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew8595b872015-01-06 15:36:38 +000039 if (rc != PSCI_E_SUCCESS)
40 return rc;
41
Soby Mathew8595b872015-01-06 15:36:38 +000042 /*
Soby Mathew981487a2015-07-13 14:10:57 +010043 * To turn this cpu on, specify which power
Achin Gupta0959db52013-12-02 17:33:04 +000044 * levels need to be turned on
45 */
Sandrine Bailleux7497bff2016-04-25 09:28:43 +010046 return psci_cpu_on_start(target_cpu, &ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +010047}
48
49unsigned int psci_version(void)
50{
51 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
52}
53
54int psci_cpu_suspend(unsigned int power_state,
Soby Mathew011ca182015-07-29 17:05:03 +010055 uintptr_t entrypoint,
56 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010057{
58 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010059 unsigned int target_pwrlvl, is_power_down_state;
Soby Mathew8595b872015-01-06 15:36:38 +000060 entry_point_info_t ep;
Soby Mathew981487a2015-07-13 14:10:57 +010061 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
62 plat_local_state_t cpu_pd_state;
Achin Gupta4f6ad662013-10-25 09:08:21 +010063
Soby Mathew981487a2015-07-13 14:10:57 +010064 /* Validate the power_state parameter */
65 rc = psci_validate_power_state(power_state, &state_info);
66 if (rc != PSCI_E_SUCCESS) {
67 assert(rc == PSCI_E_INVALID_PARAMS);
68 return rc;
69 }
Vikram Kanigirif100f412014-04-01 19:26:26 +010070
Soby Mathew981487a2015-07-13 14:10:57 +010071 /*
72 * Get the value of the state type bit from the power state parameter.
73 */
74 is_power_down_state = psci_get_pstate_type(power_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +010075
Soby Mathew981487a2015-07-13 14:10:57 +010076 /* Sanity check the requested suspend levels */
Soby Mathew24ab34f2016-05-03 17:11:42 +010077 assert(psci_validate_suspend_req(&state_info, is_power_down_state)
Soby Mathew981487a2015-07-13 14:10:57 +010078 == PSCI_E_SUCCESS);
Soby Mathew74e52a72014-10-02 16:56:51 +010079
Soby Mathew981487a2015-07-13 14:10:57 +010080 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
Sandrine Bailleuxf9f3bbf2016-06-22 16:35:01 +010081 if (target_pwrlvl == PSCI_INVALID_PWR_LVL) {
82 ERROR("Invalid target power level for suspend operation\n");
83 panic();
84 }
Soby Mathew981487a2015-07-13 14:10:57 +010085
86 /* Fast path for CPU standby.*/
Antonio Nino Diazde11a5b2018-08-01 16:42:10 +010087 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010088 if (psci_plat_pm_ops->cpu_standby == NULL)
Soby Mathew74e52a72014-10-02 16:56:51 +010089 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010090
Soby Mathew981487a2015-07-13 14:10:57 +010091 /*
92 * Set the state of the CPU power domain to the platform
93 * specific retention state and enter the standby state.
94 */
95 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
96 psci_set_cpu_local_state(cpu_pd_state);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010097
98#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +000099 plat_psci_stat_accounting_start(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100100#endif
101
dp-arm3cac7862016-09-19 11:18:44 +0100102#if ENABLE_RUNTIME_INSTRUMENTATION
103 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
104 RT_INSTR_ENTER_HW_LOW_PWR,
105 PMF_NO_CACHE_MAINT);
106#endif
107
Soby Mathew981487a2015-07-13 14:10:57 +0100108 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
Achin Gupta42c52802014-05-09 19:32:25 +0100109
Soby Mathew981487a2015-07-13 14:10:57 +0100110 /* Upon exit from standby, set the state back to RUN. */
111 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Achin Gupta42c52802014-05-09 19:32:25 +0100112
dp-arm3cac7862016-09-19 11:18:44 +0100113#if ENABLE_RUNTIME_INSTRUMENTATION
114 PMF_CAPTURE_TIMESTAMP(rt_instr_svc,
115 RT_INSTR_EXIT_HW_LOW_PWR,
116 PMF_NO_CACHE_MAINT);
117#endif
118
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100119#if ENABLE_PSCI_STAT
dp-arm66abfbe2017-01-31 13:01:04 +0000120 plat_psci_stat_accounting_stop(&state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100121
122 /* Update PSCI stats */
dp-arm66abfbe2017-01-31 13:01:04 +0000123 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100124#endif
125
Soby Mathew74e52a72014-10-02 16:56:51 +0100126 return PSCI_E_SUCCESS;
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000127 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128
Achin Gupta42c52802014-05-09 19:32:25 +0100129 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100130 * If a power down state has been requested, we need to verify entry
131 * point and program entry information.
Soby Mathew8595b872015-01-06 15:36:38 +0000132 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100133 if (is_power_down_state != 0U) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100134 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew981487a2015-07-13 14:10:57 +0100135 if (rc != PSCI_E_SUCCESS)
136 return rc;
137 }
Soby Mathewf5121572014-09-30 11:19:51 +0100138
Soby Mathew8595b872015-01-06 15:36:38 +0000139 /*
Achin Gupta42c52802014-05-09 19:32:25 +0100140 * Do what is needed to enter the power down state. Upon success,
Soby Mathew981487a2015-07-13 14:10:57 +0100141 * enter the final wfi which will power down this CPU. This function
142 * might return if the power down was abandoned for any reason, e.g.
143 * arrival of an interrupt
Achin Gupta42c52802014-05-09 19:32:25 +0100144 */
Soby Mathew981487a2015-07-13 14:10:57 +0100145 psci_cpu_suspend_start(&ep,
146 target_pwrlvl,
147 &state_info,
148 is_power_down_state);
Soby Mathew74e52a72014-10-02 16:56:51 +0100149
Soby Mathew74e52a72014-10-02 16:56:51 +0100150 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100151}
152
Soby Mathew011ca182015-07-29 17:05:03 +0100153
154int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
Soby Mathew96168382014-12-17 14:47:57 +0000155{
156 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100157 psci_power_state_t state_info;
Soby Mathew96168382014-12-17 14:47:57 +0000158 entry_point_info_t ep;
159
Soby Mathew96168382014-12-17 14:47:57 +0000160 /* Check if the current CPU is the last ON CPU in the system */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100161 if (psci_is_last_on_cpu() == 0U)
Soby Mathew96168382014-12-17 14:47:57 +0000162 return PSCI_E_DENIED;
163
Soby Mathewf1f97a12015-07-15 12:13:26 +0100164 /* Validate the entry point and get the entry_point_info */
165 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew96168382014-12-17 14:47:57 +0000166 if (rc != PSCI_E_SUCCESS)
167 return rc;
168
Soby Mathew981487a2015-07-13 14:10:57 +0100169 /* Query the psci_power_state for system suspend */
170 psci_query_sys_suspend_pwrstate(&state_info);
Soby Mathew96168382014-12-17 14:47:57 +0000171
ldts1821db22018-10-11 08:40:32 +0200172 /*
173 * Check if platform allows suspend to Highest power level
174 * (System level)
175 */
176 if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL)
177 return PSCI_E_DENIED;
178
Soby Mathew981487a2015-07-13 14:10:57 +0100179 /* Ensure that the psci_power_state makes sense */
Soby Mathew981487a2015-07-13 14:10:57 +0100180 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
181 == PSCI_E_SUCCESS);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100182 assert(is_local_state_off(
183 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0);
Soby Mathew96168382014-12-17 14:47:57 +0000184
185 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100186 * Do what is needed to enter the system suspend state. This function
187 * might return if the power down was abandoned for any reason, e.g.
188 * arrival of an interrupt
Soby Mathew96168382014-12-17 14:47:57 +0000189 */
Soby Mathew981487a2015-07-13 14:10:57 +0100190 psci_cpu_suspend_start(&ep,
191 PLAT_MAX_PWR_LVL,
192 &state_info,
193 PSTATE_TYPE_POWERDOWN);
Soby Mathew96168382014-12-17 14:47:57 +0000194
Soby Mathew96168382014-12-17 14:47:57 +0000195 return PSCI_E_SUCCESS;
196}
197
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198int psci_cpu_off(void)
199{
200 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100201 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100202
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100204 * Do what is needed to power off this CPU and possible higher power
205 * levels if it able to do so. Upon success, enter the final wfi
206 * which will power down this CPU.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207 */
Soby Mathew981487a2015-07-13 14:10:57 +0100208 rc = psci_do_cpu_off(target_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100209
Achin Gupta3140a9e2013-12-02 16:23:12 +0000210 /*
211 * The only error cpu_off can return is E_DENIED. So check if that's
212 * indeed the case.
213 */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100214 assert(rc == PSCI_E_DENIED);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215
216 return rc;
217}
218
Soby Mathew011ca182015-07-29 17:05:03 +0100219int psci_affinity_info(u_register_t target_affinity,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100220 unsigned int lowest_affinity_level)
221{
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600222 int ret;
223 unsigned int target_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224
Soby Mathew981487a2015-07-13 14:10:57 +0100225 /* We dont support level higher than PSCI_CPU_PWR_LVL */
226 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
227 return PSCI_E_INVALID_PARAMS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100228
Soby Mathew981487a2015-07-13 14:10:57 +0100229 /* Calculate the cpu index of the target */
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600230 ret = plat_core_pos_by_mpidr(target_affinity);
231 if (ret == -1) {
Soby Mathew981487a2015-07-13 14:10:57 +0100232 return PSCI_E_INVALID_PARAMS;
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600233 }
234 target_idx = (unsigned int)ret;
Achin Gupta75f73672013-12-05 16:33:10 +0000235
Roberto Vargas6dc82142017-11-13 08:24:07 +0000236 /*
237 * Generic management:
238 * Perform cache maintanence ahead of reading the target CPU state to
239 * ensure that the data is not stale.
240 * There is a theoretical edge case where the cache may contain stale
241 * data for the target CPU data - this can occur under the following
242 * conditions:
243 * - the target CPU is in another cluster from the current
244 * - the target CPU was the last CPU to shutdown on its cluster
245 * - the cluster was removed from coherency as part of the CPU shutdown
246 *
247 * In this case the cache maintenace that was performed as part of the
248 * target CPUs shutdown was not seen by the current CPU's cluster. And
249 * so the cache may contain stale data for the target CPU.
250 */
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -0600251 flush_cpu_data_by_index(target_idx,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100252 psci_svc_cpu_data.aff_info_state);
Roberto Vargas6dc82142017-11-13 08:24:07 +0000253
Soby Mathew981487a2015-07-13 14:10:57 +0100254 return psci_get_aff_info_state_by_idx(target_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255}
256
Soby Mathew011ca182015-07-29 17:05:03 +0100257int psci_migrate(u_register_t target_cpu)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258{
Soby Mathew110fe362014-10-23 10:35:34 +0100259 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100260 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100261
262 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
263 if (rc != PSCI_TOS_UP_MIG_CAP)
264 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
265 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
266
267 /*
268 * Migrate should only be invoked on the CPU where
269 * the Secure OS is resident.
270 */
271 if (resident_cpu_mpidr != read_mpidr_el1())
272 return PSCI_E_NOT_PRESENT;
273
274 /* Check the validity of the specified target cpu */
Soby Mathew981487a2015-07-13 14:10:57 +0100275 rc = psci_validate_mpidr(target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100276 if (rc != PSCI_E_SUCCESS)
277 return PSCI_E_INVALID_PARAMS;
278
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100279 assert((psci_spd_pm != NULL) && (psci_spd_pm->svc_migrate != NULL));
Soby Mathew110fe362014-10-23 10:35:34 +0100280
281 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100282 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL));
Soby Mathew110fe362014-10-23 10:35:34 +0100283
284 return rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100285}
286
Soby Mathew110fe362014-10-23 10:35:34 +0100287int psci_migrate_info_type(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100288{
Soby Mathew011ca182015-07-29 17:05:03 +0100289 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100290
291 return psci_spd_migrate_info(&resident_cpu_mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100292}
293
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100294u_register_t psci_migrate_info_up_cpu(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100295{
Soby Mathew011ca182015-07-29 17:05:03 +0100296 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100297 int rc;
298
Achin Gupta4f6ad662013-10-25 09:08:21 +0100299 /*
Soby Mathew110fe362014-10-23 10:35:34 +0100300 * Return value of this depends upon what
301 * psci_spd_migrate_info() returns.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100302 */
Soby Mathew110fe362014-10-23 10:35:34 +0100303 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100304 if ((rc != PSCI_TOS_NOT_UP_MIG_CAP) && (rc != PSCI_TOS_UP_MIG_CAP))
305 return (u_register_t)(register_t) PSCI_E_INVALID_PARAMS;
Soby Mathew110fe362014-10-23 10:35:34 +0100306
307 return resident_cpu_mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100308}
309
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100310int psci_node_hw_state(u_register_t target_cpu,
311 unsigned int power_level)
312{
313 int rc;
314
315 /* Validate target_cpu */
316 rc = psci_validate_mpidr(target_cpu);
317 if (rc != PSCI_E_SUCCESS)
318 return PSCI_E_INVALID_PARAMS;
319
320 /* Validate power_level against PLAT_MAX_PWR_LVL */
321 if (power_level > PLAT_MAX_PWR_LVL)
322 return PSCI_E_INVALID_PARAMS;
323
324 /*
325 * Dispatch this call to platform to query power controller, and pass on
326 * to the caller what it returns
327 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100328 assert(psci_plat_pm_ops->get_node_hw_state != NULL);
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100329 rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100330 assert(((rc >= HW_ON) && (rc <= HW_STANDBY))
331 || (rc == PSCI_E_NOT_SUPPORTED)
332 || (rc == PSCI_E_INVALID_PARAMS));
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100333 return rc;
334}
335
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000336int psci_features(unsigned int psci_fid)
337{
Soby Mathew011ca182015-07-29 17:05:03 +0100338 unsigned int local_caps = psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000339
Dimitris Papastamosa65841a2018-01-22 12:58:52 +0000340 if (psci_fid == SMCCC_VERSION)
341 return PSCI_E_SUCCESS;
342
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000343 /* Check if it is a 64 bit function */
344 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
345 local_caps &= PSCI_CAP_64BIT_MASK;
346
347 /* Check for invalid fid */
348 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
349 && is_psci_fid(psci_fid)))
350 return PSCI_E_NOT_SUPPORTED;
351
352
353 /* Check if the psci fid is supported or not */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100354 if ((local_caps & define_psci_cap(psci_fid)) == 0U)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000355 return PSCI_E_NOT_SUPPORTED;
356
357 /* Format the feature flags */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100358 if ((psci_fid == PSCI_CPU_SUSPEND_AARCH32) ||
359 (psci_fid == PSCI_CPU_SUSPEND_AARCH64)) {
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000360 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100361 * The trusted firmware does not support OS Initiated Mode.
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000362 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100363 unsigned int ret = ((FF_PSTATE << FF_PSTATE_SHIFT) |
364 (((FF_SUPPORTS_OS_INIT_MODE == 1U) ? 0U : 1U)
365 << FF_MODE_SUPPORT_SHIFT));
366 return (int) ret;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000367 }
368
369 /* Return 0 for all other fid's */
370 return PSCI_E_SUCCESS;
371}
372
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000373/*******************************************************************************
374 * PSCI top level handler for servicing SMCs.
375 ******************************************************************************/
Soby Mathewd0194872016-04-29 19:01:30 +0100376u_register_t psci_smc_handler(uint32_t smc_fid,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100377 u_register_t x1,
378 u_register_t x2,
379 u_register_t x3,
380 u_register_t x4,
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000381 void *cookie,
382 void *handle,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100383 u_register_t flags)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000384{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100385 u_register_t ret;
386
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100387 if (is_caller_secure(flags))
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100388 return (u_register_t)SMC_UNK;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000389
Soby Mathew61e615b2015-01-15 11:49:49 +0000390 /* Check the fid against the capabilities */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100391 if ((psci_caps & define_psci_cap(smc_fid)) == 0U)
392 return (u_register_t)SMC_UNK;
Soby Mathew61e615b2015-01-15 11:49:49 +0000393
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100394 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
395 /* 32-bit PSCI function, clear top parameter bits */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000396
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100397 uint32_t r1 = (uint32_t)x1;
398 uint32_t r2 = (uint32_t)x2;
399 uint32_t r3 = (uint32_t)x3;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000400
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100401 switch (smc_fid) {
402 case PSCI_VERSION:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100403 ret = (u_register_t)psci_version();
404 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000405
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100406 case PSCI_CPU_OFF:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100407 ret = (u_register_t)psci_cpu_off();
408 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000409
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100410 case PSCI_CPU_SUSPEND_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100411 ret = (u_register_t)psci_cpu_suspend(r1, r2, r3);
412 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000413
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100414 case PSCI_CPU_ON_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100415 ret = (u_register_t)psci_cpu_on(r1, r2, r3);
416 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000417
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100418 case PSCI_AFFINITY_INFO_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100419 ret = (u_register_t)psci_affinity_info(r1, r2);
420 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000421
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100422 case PSCI_MIG_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100423 ret = (u_register_t)psci_migrate(r1);
424 break;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000425
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100426 case PSCI_MIG_INFO_TYPE:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100427 ret = (u_register_t)psci_migrate_info_type();
428 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100429
430 case PSCI_MIG_INFO_UP_CPU_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100431 ret = psci_migrate_info_up_cpu();
432 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100433
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100434 case PSCI_NODE_HW_STATE_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100435 ret = (u_register_t)psci_node_hw_state(r1, r2);
436 break;
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100437
Soby Mathew96168382014-12-17 14:47:57 +0000438 case PSCI_SYSTEM_SUSPEND_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100439 ret = (u_register_t)psci_system_suspend(r1, r2);
440 break;
Soby Mathew96168382014-12-17 14:47:57 +0000441
Juan Castillo4dc4a472014-08-12 11:17:06 +0100442 case PSCI_SYSTEM_OFF:
443 psci_system_off();
444 /* We should never return from psci_system_off() */
Jonathan Wrightde701832018-03-13 17:45:42 +0000445 break;
Juan Castillo4dc4a472014-08-12 11:17:06 +0100446
447 case PSCI_SYSTEM_RESET:
448 psci_system_reset();
449 /* We should never return from psci_system_reset() */
Jonathan Wrightde701832018-03-13 17:45:42 +0000450 break;
Juan Castillo4dc4a472014-08-12 11:17:06 +0100451
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000452 case PSCI_FEATURES:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100453 ret = (u_register_t)psci_features(r1);
454 break;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000455
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100456#if ENABLE_PSCI_STAT
457 case PSCI_STAT_RESIDENCY_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100458 ret = psci_stat_residency(r1, r2);
459 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100460
461 case PSCI_STAT_COUNT_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100462 ret = psci_stat_count(r1, r2);
463 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100464#endif
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100465 case PSCI_MEM_PROTECT:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100466 ret = psci_mem_protect(r1);
467 break;
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100468
469 case PSCI_MEM_CHK_RANGE_AARCH32:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100470 ret = psci_mem_chk_range(r1, r2);
471 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100472
Roberto Vargasb820ad02017-07-26 09:23:09 +0100473 case PSCI_SYSTEM_RESET2_AARCH32:
474 /* We should never return from psci_system_reset2() */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100475 ret = psci_system_reset2(r1, r2);
476 break;
Roberto Vargasb820ad02017-07-26 09:23:09 +0100477
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100478 default:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100479 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid);
480 ret = (u_register_t)SMC_UNK;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100481 break;
482 }
483 } else {
484 /* 64-bit PSCI function */
485
486 switch (smc_fid) {
487 case PSCI_CPU_SUSPEND_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100488 ret = (u_register_t)
489 psci_cpu_suspend((unsigned int)x1, x2, x3);
490 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100491
492 case PSCI_CPU_ON_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100493 ret = (u_register_t)psci_cpu_on(x1, x2, x3);
494 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100495
496 case PSCI_AFFINITY_INFO_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100497 ret = (u_register_t)
498 psci_affinity_info(x1, (unsigned int)x2);
499 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100500
501 case PSCI_MIG_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100502 ret = (u_register_t)psci_migrate(x1);
503 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100504
505 case PSCI_MIG_INFO_UP_CPU_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100506 ret = psci_migrate_info_up_cpu();
507 break;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100508
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100509 case PSCI_NODE_HW_STATE_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100510 ret = (u_register_t)psci_node_hw_state(
511 x1, (unsigned int) x2);
512 break;
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100513
Soby Mathew96168382014-12-17 14:47:57 +0000514 case PSCI_SYSTEM_SUSPEND_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100515 ret = (u_register_t)psci_system_suspend(x1, x2);
516 break;
Soby Mathew96168382014-12-17 14:47:57 +0000517
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100518#if ENABLE_PSCI_STAT
519 case PSCI_STAT_RESIDENCY_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100520 ret = psci_stat_residency(x1, (unsigned int) x2);
521 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100522
523 case PSCI_STAT_COUNT_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100524 ret = psci_stat_count(x1, (unsigned int) x2);
525 break;
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100526#endif
527
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100528 case PSCI_MEM_CHK_RANGE_AARCH64:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100529 ret = psci_mem_chk_range(x1, x2);
530 break;
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100531
Roberto Vargasb820ad02017-07-26 09:23:09 +0100532 case PSCI_SYSTEM_RESET2_AARCH64:
533 /* We should never return from psci_system_reset2() */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100534 ret = psci_system_reset2((uint32_t) x1, x2);
535 break;
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100536
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100537 default:
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100538 WARN("Unimplemented PSCI Call: 0x%x\n", smc_fid);
539 ret = (u_register_t)SMC_UNK;
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100540 break;
541 }
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000542 }
543
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100544 return ret;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000545}