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Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
Varun Wadekarcad7b082015-12-28 18:12:59 -08002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +05305 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef TEGRA_DEF_H
8#define TEGRA_DEF_H
Varun Wadekar921b9062015-08-25 17:03:14 +05309
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Varun Wadekar761ca732017-04-24 14:17:12 -070011
Varun Wadekar921b9062015-08-25 17:03:14 +053012/*******************************************************************************
Varun Wadekaracf1cad2016-12-12 14:24:17 -080013 * MCE apertures used by the ARI interface
14 *
15 * Aperture 0 - Cpu0 (ARM Cortex A-57)
16 * Aperture 1 - Cpu1 (ARM Cortex A-57)
17 * Aperture 2 - Cpu2 (ARM Cortex A-57)
18 * Aperture 3 - Cpu3 (ARM Cortex A-57)
19 * Aperture 4 - Cpu4 (Denver15)
20 * Aperture 5 - Cpu5 (Denver15)
21 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070022#define MCE_ARI_APERTURE_0_OFFSET U(0x0)
23#define MCE_ARI_APERTURE_1_OFFSET U(0x10000)
24#define MCE_ARI_APERTURE_2_OFFSET U(0x20000)
25#define MCE_ARI_APERTURE_3_OFFSET U(0x30000)
26#define MCE_ARI_APERTURE_4_OFFSET U(0x40000)
27#define MCE_ARI_APERTURE_5_OFFSET U(0x50000)
Varun Wadekaracf1cad2016-12-12 14:24:17 -080028#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
29
30/* number of apertures */
Varun Wadekar761ca732017-04-24 14:17:12 -070031#define MCE_ARI_APERTURES_MAX U(6)
Varun Wadekaracf1cad2016-12-12 14:24:17 -080032
33/* each ARI aperture is 64KB */
Varun Wadekar761ca732017-04-24 14:17:12 -070034#define MCE_ARI_APERTURE_SIZE U(0x10000)
Varun Wadekaracf1cad2016-12-12 14:24:17 -080035
36/*******************************************************************************
37 * CPU core id macros for the MCE_ONLINE_CORE ARI
38 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070039#define MCE_CORE_ID_MAX U(8)
40#define MCE_CORE_ID_MASK U(0x7)
Varun Wadekaracf1cad2016-12-12 14:24:17 -080041
42/*******************************************************************************
Varun Wadekar42236572016-01-18 19:03:19 -080043 * These values are used by the PSCI implementation during the `CPU_SUSPEND`
44 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
45 * parameter.
46 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070047#define PSTATE_ID_CORE_IDLE U(6)
48#define PSTATE_ID_CORE_POWERDN U(7)
49#define PSTATE_ID_SOC_POWERDN U(2)
Varun Wadekar42236572016-01-18 19:03:19 -080050
51/*******************************************************************************
52 * Platform power states (used by PSCI framework)
53 *
54 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
55 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
Varun Wadekar921b9062015-08-25 17:03:14 +053056 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070057#define PLAT_MAX_RET_STATE U(1)
58#define PLAT_MAX_OFF_STATE U(8)
Varun Wadekar921b9062015-08-25 17:03:14 +053059
60/*******************************************************************************
Varun Wadekarcad7b082015-12-28 18:12:59 -080061 * Secure IRQ definitions
62 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070063#define TEGRA186_TOP_WDT_IRQ U(49)
64#define TEGRA186_AON_WDT_IRQ U(50)
Varun Wadekarcad7b082015-12-28 18:12:59 -080065
Varun Wadekar761ca732017-04-24 14:17:12 -070066#define TEGRA186_SEC_IRQ_TARGET_MASK U(0xF3) /* 4 A57 - 2 Denver */
Varun Wadekarcad7b082015-12-28 18:12:59 -080067
68/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +053069 * Tegra Miscellanous register constants
70 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070071#define TEGRA_MISC_BASE U(0x00100000)
72#define HARDWARE_REVISION_OFFSET U(0x4)
Varun Wadekare2bc7f22016-04-02 15:41:20 -070073
Varun Wadekar761ca732017-04-24 14:17:12 -070074#define MISCREG_PFCFG U(0x200C)
Varun Wadekar921b9062015-08-25 17:03:14 +053075
76/*******************************************************************************
Varun Wadekara0f26972016-03-11 17:18:51 -080077 * Tegra TSA Controller constants
78 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070079#define TEGRA_TSA_BASE U(0x02400000)
Varun Wadekara0f26972016-03-11 17:18:51 -080080
81/*******************************************************************************
Varun Wadekarf5fc53f2016-12-15 11:54:51 -080082 * TSA configuration registers
83 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -070084#define TSA_CONFIG_STATIC0_CSW_SESWR U(0x4010)
85#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET U(0x1100)
86#define TSA_CONFIG_STATIC0_CSW_ETRW U(0x4038)
87#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET U(0x1100)
88#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB U(0x5010)
89#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET U(0x1100)
90#define TSA_CONFIG_STATIC0_CSW_AXISW U(0x7008)
91#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET U(0x1100)
92#define TSA_CONFIG_STATIC0_CSW_HDAW U(0xA008)
93#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET U(0x100)
94#define TSA_CONFIG_STATIC0_CSW_AONDMAW U(0xB018)
95#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET U(0x1100)
96#define TSA_CONFIG_STATIC0_CSW_SCEDMAW U(0xD018)
97#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET U(0x1100)
98#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW U(0xD028)
99#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET U(0x1100)
100#define TSA_CONFIG_STATIC0_CSW_APEDMAW U(0x12018)
101#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET U(0x1100)
102#define TSA_CONFIG_STATIC0_CSW_UFSHCW U(0x13008)
103#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET U(0x1100)
104#define TSA_CONFIG_STATIC0_CSW_AFIW U(0x13018)
105#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET U(0x1100)
106#define TSA_CONFIG_STATIC0_CSW_SATAW U(0x13028)
107#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET U(0x1100)
108#define TSA_CONFIG_STATIC0_CSW_EQOSW U(0x13038)
109#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET U(0x1100)
110#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW U(0x15008)
111#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET U(0x1100)
112#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW U(0x15018)
113#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET U(0x1100)
Varun Wadekarf5fc53f2016-12-15 11:54:51 -0800114
Varun Wadekar761ca732017-04-24 14:17:12 -0700115#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (U(0x3) << 11)
116#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (U(0) << 11)
Varun Wadekarf5fc53f2016-12-15 11:54:51 -0800117
118/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530119 * Tegra Memory Controller constants
120 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700121#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
122#define TEGRA_MC_BASE U(0x02C10000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530123
Varun Wadekar153982c2016-12-21 14:50:18 -0800124/* General Security Carveout register macros */
Varun Wadekar761ca732017-04-24 14:17:12 -0700125#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
126#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
127#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0)
128#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
129#define MC_GSC_BASE_LO_SHIFT U(12)
130#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
131#define MC_GSC_BASE_HI_SHIFT U(0)
132#define MC_GSC_BASE_HI_MASK U(3)
Varun Wadekar153982c2016-12-21 14:50:18 -0800133
Varun Wadekar64443ca2016-12-12 16:14:57 -0800134/* TZDRAM carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700135#define MC_SECURITY_CFG0_0 U(0x70)
136#define MC_SECURITY_CFG1_0 U(0x74)
137#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800138
139/* Video Memory carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700140#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
141#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
142#define MC_VIDEO_PROTECT_SIZE_MB U(0x64C)
Varun Wadekar153982c2016-12-21 14:50:18 -0800143
144/*
145 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
146 * non-overlapping Video memory region
147 */
Varun Wadekar761ca732017-04-24 14:17:12 -0700148#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
149#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
150#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
151#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
152#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800153
154/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700155#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
156#define MC_TZRAM_BASE_LO U(0x2194)
157#define MC_TZRAM_BASE_HI U(0x2198)
158#define MC_TZRAM_SIZE U(0x219C)
159#define MC_TZRAM_CLIENT_ACCESS_CFG0 U(0x21A0)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800160
Varun Wadekar921b9062015-08-25 17:03:14 +0530161/*******************************************************************************
162 * Tegra UART Controller constants
163 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700164#define TEGRA_UARTA_BASE U(0x03100000)
165#define TEGRA_UARTB_BASE U(0x03110000)
166#define TEGRA_UARTC_BASE U(0x0C280000)
167#define TEGRA_UARTD_BASE U(0x03130000)
168#define TEGRA_UARTE_BASE U(0x03140000)
169#define TEGRA_UARTF_BASE U(0x03150000)
170#define TEGRA_UARTG_BASE U(0x0C290000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530171
172/*******************************************************************************
Varun Wadekar4debe052016-05-18 13:39:16 -0700173 * Tegra Fuse Controller related constants
174 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700175#define TEGRA_FUSE_BASE U(0x03820000)
176#define OPT_SUBREVISION U(0x248)
177#define SUBREVISION_MASK U(0xFF)
Varun Wadekar4debe052016-05-18 13:39:16 -0700178
179/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530180 * GICv2 & interrupt handling related constants
181 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700182#define TEGRA_GICD_BASE U(0x03881000)
183#define TEGRA_GICC_BASE U(0x03882000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530184
185/*******************************************************************************
Varun Wadekarb8776152016-03-03 13:52:52 -0800186 * Security Engine related constants
187 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700188#define TEGRA_SE0_BASE U(0x03AC0000)
189#define SE_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
190#define TEGRA_PKA1_BASE U(0x03AD0000)
191#define PKA_MUTEX_WATCHDOG_NS_LIMIT U(0x8144)
192#define TEGRA_RNG1_BASE U(0x03AE0000)
193#define RNG_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
Varun Wadekarb8776152016-03-03 13:52:52 -0800194
195/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530196 * Tegra Clock and Reset Controller constants
197 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700198#define TEGRA_CAR_RESET_BASE U(0x05000000)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700199#define TEGRA_GPU_RESET_REG_OFFSET U(0x30)
200#define GPU_RESET_BIT (U(1) << 0)
Varun Wadekar921b9062015-08-25 17:03:14 +0530201
202/*******************************************************************************
203 * Tegra micro-seconds timer constants
204 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700205#define TEGRA_TMRUS_BASE U(0x0C2E0000)
206#define TEGRA_TMRUS_SIZE U(0x1000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530207
208/*******************************************************************************
209 * Tegra Power Mgmt Controller constants
210 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700211#define TEGRA_PMC_BASE U(0x0C360000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530212
213/*******************************************************************************
214 * Tegra scratch registers constants
215 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700216#define TEGRA_SCRATCH_BASE U(0x0C390000)
217#define SECURE_SCRATCH_RSV1_LO U(0x658)
218#define SECURE_SCRATCH_RSV1_HI U(0x65C)
219#define SECURE_SCRATCH_RSV6 U(0x680)
220#define SECURE_SCRATCH_RSV11_LO U(0x6A8)
221#define SECURE_SCRATCH_RSV11_HI U(0x6AC)
222#define SECURE_SCRATCH_RSV53_LO U(0x7F8)
223#define SECURE_SCRATCH_RSV53_HI U(0x7FC)
224#define SECURE_SCRATCH_RSV54_HI U(0x804)
225#define SECURE_SCRATCH_RSV55_LO U(0x808)
226#define SECURE_SCRATCH_RSV55_HI U(0x80C)
Varun Wadekar921b9062015-08-25 17:03:14 +0530227
228/*******************************************************************************
Varun Wadekard64db962016-09-23 14:28:16 -0700229 * Tegra Memory Mapped Control Register Access constants
Varun Wadekar921b9062015-08-25 17:03:14 +0530230 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700231#define TEGRA_MMCRAB_BASE U(0x0E000000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530232
233/*******************************************************************************
Varun Wadekard64db962016-09-23 14:28:16 -0700234 * Tegra Memory Mapped Activity Monitor Register Access constants
235 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700236#define TEGRA_ARM_ACTMON_CTR_BASE U(0x0E060000)
237#define TEGRA_DENVER_ACTMON_CTR_BASE U(0x0E070000)
Varun Wadekard64db962016-09-23 14:28:16 -0700238
239/*******************************************************************************
Varun Wadekar921b9062015-08-25 17:03:14 +0530240 * Tegra SMMU Controller constants
241 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700242#define TEGRA_SMMU0_BASE U(0x12000000)
Varun Wadekar921b9062015-08-25 17:03:14 +0530243
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800244/*******************************************************************************
245 * Tegra TZRAM constants
246 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700247#define TEGRA_TZRAM_BASE U(0x30000000)
248#define TEGRA_TZRAM_SIZE U(0x40000)
Varun Wadekar13e7dc42015-12-30 15:15:08 -0800249
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000250#endif /* TEGRA_DEF_H */